![Thomas Gleixner](/assets/img/avatar_default.png)
Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
225 lines
5.3 KiB
C
225 lines
5.3 KiB
C
#include <linux/init.h>
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#include <linux/mm.h>
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#include <asm/mtrr.h>
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#include <asm/msr.h>
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#include "mtrr.h"
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static struct {
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unsigned long high;
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unsigned long low;
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} centaur_mcr[8];
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static u8 centaur_mcr_reserved;
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static u8 centaur_mcr_type; /* 0 for winchip, 1 for winchip2 */
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/*
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* Report boot time MCR setups
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*/
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static int
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centaur_get_free_region(unsigned long base, unsigned long size, int replace_reg)
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/* [SUMMARY] Get a free MTRR.
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<base> The starting (base) address of the region.
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<size> The size (in bytes) of the region.
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[RETURNS] The index of the region on success, else -1 on error.
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*/
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{
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int i, max;
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mtrr_type ltype;
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unsigned long lbase, lsize;
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max = num_var_ranges;
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if (replace_reg >= 0 && replace_reg < max)
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return replace_reg;
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for (i = 0; i < max; ++i) {
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if (centaur_mcr_reserved & (1 << i))
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continue;
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mtrr_if->get(i, &lbase, &lsize, <ype);
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if (lsize == 0)
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return i;
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}
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return -ENOSPC;
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}
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void
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mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi)
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{
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centaur_mcr[mcr].low = lo;
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centaur_mcr[mcr].high = hi;
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}
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static void
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centaur_get_mcr(unsigned int reg, unsigned long *base,
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unsigned long *size, mtrr_type * type)
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{
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*base = centaur_mcr[reg].high >> PAGE_SHIFT;
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*size = -(centaur_mcr[reg].low & 0xfffff000) >> PAGE_SHIFT;
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*type = MTRR_TYPE_WRCOMB; /* If it is there, it is write-combining */
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if (centaur_mcr_type == 1 && ((centaur_mcr[reg].low & 31) & 2))
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*type = MTRR_TYPE_UNCACHABLE;
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if (centaur_mcr_type == 1 && (centaur_mcr[reg].low & 31) == 25)
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*type = MTRR_TYPE_WRBACK;
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if (centaur_mcr_type == 0 && (centaur_mcr[reg].low & 31) == 31)
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*type = MTRR_TYPE_WRBACK;
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}
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static void centaur_set_mcr(unsigned int reg, unsigned long base,
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unsigned long size, mtrr_type type)
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{
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unsigned long low, high;
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if (size == 0) {
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/* Disable */
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high = low = 0;
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} else {
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high = base << PAGE_SHIFT;
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if (centaur_mcr_type == 0)
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low = -size << PAGE_SHIFT | 0x1f; /* only support write-combining... */
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else {
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if (type == MTRR_TYPE_UNCACHABLE)
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low = -size << PAGE_SHIFT | 0x02; /* NC */
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else
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low = -size << PAGE_SHIFT | 0x09; /* WWO,WC */
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}
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}
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centaur_mcr[reg].high = high;
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centaur_mcr[reg].low = low;
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wrmsr(MSR_IDT_MCR0 + reg, low, high);
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}
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#if 0
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/*
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* Initialise the later (saner) Winchip MCR variant. In this version
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* the BIOS can pass us the registers it has used (but not their values)
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* and the control register is read/write
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*/
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static void __init
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centaur_mcr1_init(void)
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{
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unsigned i;
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u32 lo, hi;
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/* Unfortunately, MCR's are read-only, so there is no way to
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* find out what the bios might have done.
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*/
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rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
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if (((lo >> 17) & 7) == 1) { /* Type 1 Winchip2 MCR */
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lo &= ~0x1C0; /* clear key */
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lo |= 0x040; /* set key to 1 */
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wrmsr(MSR_IDT_MCR_CTRL, lo, hi); /* unlock MCR */
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}
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centaur_mcr_type = 1;
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/*
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* Clear any unconfigured MCR's.
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*/
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for (i = 0; i < 8; ++i) {
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if (centaur_mcr[i].high == 0 && centaur_mcr[i].low == 0) {
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if (!(lo & (1 << (9 + i))))
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wrmsr(MSR_IDT_MCR0 + i, 0, 0);
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else
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/*
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* If the BIOS set up an MCR we cannot see it
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* but we don't wish to obliterate it
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*/
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centaur_mcr_reserved |= (1 << i);
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}
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}
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/*
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* Throw the main write-combining switch...
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* However if OOSTORE is enabled then people have already done far
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* cleverer things and we should behave.
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*/
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lo |= 15; /* Write combine enables */
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wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
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}
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/*
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* Initialise the original winchip with read only MCR registers
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* no used bitmask for the BIOS to pass on and write only control
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*/
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static void __init
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centaur_mcr0_init(void)
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{
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unsigned i;
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/* Unfortunately, MCR's are read-only, so there is no way to
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* find out what the bios might have done.
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*/
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/* Clear any unconfigured MCR's.
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* This way we are sure that the centaur_mcr array contains the actual
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* values. The disadvantage is that any BIOS tweaks are thus undone.
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*
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*/
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for (i = 0; i < 8; ++i) {
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if (centaur_mcr[i].high == 0 && centaur_mcr[i].low == 0)
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wrmsr(MSR_IDT_MCR0 + i, 0, 0);
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}
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wrmsr(MSR_IDT_MCR_CTRL, 0x01F0001F, 0); /* Write only */
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}
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/*
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* Initialise Winchip series MCR registers
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*/
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static void __init
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centaur_mcr_init(void)
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{
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struct set_mtrr_context ctxt;
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set_mtrr_prepare_save(&ctxt);
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set_mtrr_cache_disable(&ctxt);
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if (boot_cpu_data.x86_model == 4)
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centaur_mcr0_init();
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else if (boot_cpu_data.x86_model == 8 || boot_cpu_data.x86_model == 9)
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centaur_mcr1_init();
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set_mtrr_done(&ctxt);
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}
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#endif
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static int centaur_validate_add_page(unsigned long base,
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unsigned long size, unsigned int type)
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{
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/*
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* FIXME: Winchip2 supports uncached
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*/
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if (type != MTRR_TYPE_WRCOMB &&
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(centaur_mcr_type == 0 || type != MTRR_TYPE_UNCACHABLE)) {
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printk(KERN_WARNING
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"mtrr: only write-combining%s supported\n",
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centaur_mcr_type ? " and uncacheable are"
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: " is");
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return -EINVAL;
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}
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return 0;
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}
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static struct mtrr_ops centaur_mtrr_ops = {
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.vendor = X86_VENDOR_CENTAUR,
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// .init = centaur_mcr_init,
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.set = centaur_set_mcr,
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.get = centaur_get_mcr,
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.get_free_region = centaur_get_free_region,
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.validate_add_page = centaur_validate_add_page,
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.have_wrcomb = positive_have_wrcomb,
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};
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int __init centaur_init_mtrr(void)
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{
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set_mtrr_ops(¢aur_mtrr_ops);
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return 0;
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}
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//arch_initcall(centaur_init_mtrr);
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