![Ben Skeggs](/assets/img/avatar_default.png)
NVA3+ has an extra bit here compared to NV50:NVA3 chipsets. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
221 lines
6 KiB
C
221 lines
6 KiB
C
/*
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* Copyright 2010 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "drmP.h"
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#include "nouveau_drv.h"
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#include "nouveau_mm.h"
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static int types[0x80] = {
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1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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1, 1, 1, 1, 0, 0, 0, 0, 2, 2, 2, 2, 0, 0, 0, 0,
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1, 1, 1, 1, 1, 1, 1, 0, 2, 2, 2, 2, 2, 2, 2, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 0, 0,
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0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 2, 2, 2, 2,
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1, 0, 2, 0, 1, 0, 2, 0, 1, 1, 2, 2, 1, 1, 0, 0
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};
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bool
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nv50_vram_flags_valid(struct drm_device *dev, u32 tile_flags)
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{
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int type = (tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) >> 8;
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if (likely(type < ARRAY_SIZE(types) && types[type]))
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return true;
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return false;
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}
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void
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nv50_vram_del(struct drm_device *dev, struct nouveau_mem **pmem)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_mm *mm = &dev_priv->engine.vram.mm;
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struct nouveau_mm_node *this;
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struct nouveau_mem *mem;
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mem = *pmem;
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*pmem = NULL;
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if (unlikely(mem == NULL))
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return;
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mutex_lock(&mm->mutex);
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while (!list_empty(&mem->regions)) {
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this = list_first_entry(&mem->regions, struct nouveau_mm_node, rl_entry);
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list_del(&this->rl_entry);
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nouveau_mm_put(mm, this);
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}
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if (mem->tag) {
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drm_mm_put_block(mem->tag);
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mem->tag = NULL;
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}
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mutex_unlock(&mm->mutex);
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kfree(mem);
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}
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int
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nv50_vram_new(struct drm_device *dev, u64 size, u32 align, u32 size_nc,
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u32 memtype, struct nouveau_mem **pmem)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_mm *mm = &dev_priv->engine.vram.mm;
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struct nouveau_mm_node *r;
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struct nouveau_mem *mem;
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int comp = (memtype & 0x300) >> 8;
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int type = (memtype & 0x07f);
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int ret;
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if (!types[type])
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return -EINVAL;
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size >>= 12;
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align >>= 12;
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size_nc >>= 12;
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mem = kzalloc(sizeof(*mem), GFP_KERNEL);
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if (!mem)
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return -ENOMEM;
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mutex_lock(&mm->mutex);
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if (comp) {
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if (align == 16) {
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struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
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int n = (size >> 4) * comp;
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mem->tag = drm_mm_search_free(&pfb->tag_heap, n, 0, 0);
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if (mem->tag)
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mem->tag = drm_mm_get_block(mem->tag, n, 0);
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}
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if (unlikely(!mem->tag))
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comp = 0;
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}
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INIT_LIST_HEAD(&mem->regions);
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mem->dev = dev_priv->dev;
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mem->memtype = (comp << 7) | type;
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mem->size = size;
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do {
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ret = nouveau_mm_get(mm, types[type], size, size_nc, align, &r);
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if (ret) {
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mutex_unlock(&mm->mutex);
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nv50_vram_del(dev, &mem);
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return ret;
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}
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list_add_tail(&r->rl_entry, &mem->regions);
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size -= r->length;
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} while (size);
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mutex_unlock(&mm->mutex);
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r = list_first_entry(&mem->regions, struct nouveau_mm_node, rl_entry);
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mem->offset = (u64)r->offset << 12;
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*pmem = mem;
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return 0;
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}
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static u32
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nv50_vram_rblock(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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int i, parts, colbits, rowbitsa, rowbitsb, banks;
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u64 rowsize, predicted;
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u32 r0, r4, rt, ru, rblock_size;
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r0 = nv_rd32(dev, 0x100200);
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r4 = nv_rd32(dev, 0x100204);
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rt = nv_rd32(dev, 0x100250);
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ru = nv_rd32(dev, 0x001540);
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NV_DEBUG(dev, "memcfg 0x%08x 0x%08x 0x%08x 0x%08x\n", r0, r4, rt, ru);
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for (i = 0, parts = 0; i < 8; i++) {
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if (ru & (0x00010000 << i))
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parts++;
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}
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colbits = (r4 & 0x0000f000) >> 12;
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rowbitsa = ((r4 & 0x000f0000) >> 16) + 8;
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rowbitsb = ((r4 & 0x00f00000) >> 20) + 8;
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banks = 1 << (((r4 & 0x03000000) >> 24) + 2);
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rowsize = parts * banks * (1 << colbits) * 8;
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predicted = rowsize << rowbitsa;
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if (r0 & 0x00000004)
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predicted += rowsize << rowbitsb;
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if (predicted != dev_priv->vram_size) {
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NV_WARN(dev, "memory controller reports %dMiB VRAM\n",
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(u32)(dev_priv->vram_size >> 20));
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NV_WARN(dev, "we calculated %dMiB VRAM\n",
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(u32)(predicted >> 20));
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}
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rblock_size = rowsize;
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if (rt & 1)
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rblock_size *= 3;
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NV_DEBUG(dev, "rblock %d bytes\n", rblock_size);
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return rblock_size;
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}
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int
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nv50_vram_init(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_vram_engine *vram = &dev_priv->engine.vram;
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const u32 rsvd_head = ( 256 * 1024) >> 12; /* vga memory */
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const u32 rsvd_tail = (1024 * 1024) >> 12; /* vbios etc */
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u32 rblock, length;
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dev_priv->vram_size = nv_rd32(dev, 0x10020c);
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dev_priv->vram_size |= (dev_priv->vram_size & 0xff) << 32;
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dev_priv->vram_size &= 0xffffffff00ULL;
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/* IGPs, no funky reordering happens here, they don't have VRAM */
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if (dev_priv->chipset == 0xaa ||
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dev_priv->chipset == 0xac ||
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dev_priv->chipset == 0xaf) {
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dev_priv->vram_sys_base = (u64)nv_rd32(dev, 0x100e10) << 12;
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rblock = 4096 >> 12;
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} else {
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rblock = nv50_vram_rblock(dev) >> 12;
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}
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length = (dev_priv->vram_size >> 12) - rsvd_head - rsvd_tail;
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return nouveau_mm_init(&vram->mm, rsvd_head, length, rblock);
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}
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void
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nv50_vram_fini(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_vram_engine *vram = &dev_priv->engine.vram;
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nouveau_mm_fini(&vram->mm);
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}
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