![Marcin Slusarz](/assets/img/avatar_default.png)
This seems to be a typo... Signed-off-by: Marcin Slusarz <marcin.slusarz@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
183 lines
4.7 KiB
C
183 lines
4.7 KiB
C
/*
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* Copyright 2010 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "drmP.h"
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#include "nouveau_drv.h"
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#include "nouveau_vm.h"
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void
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nv50_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 pde,
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struct nouveau_gpuobj *pgt[2])
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{
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u64 phys = 0xdeadcafe00000000ULL;
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u32 coverage = 0;
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if (pgt[0]) {
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phys = 0x00000003 | pgt[0]->vinst; /* present, 4KiB pages */
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coverage = (pgt[0]->size >> 3) << 12;
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} else
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if (pgt[1]) {
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phys = 0x00000001 | pgt[1]->vinst; /* present */
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coverage = (pgt[1]->size >> 3) << 16;
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}
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if (phys & 1) {
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if (coverage <= 32 * 1024 * 1024)
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phys |= 0x60;
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else if (coverage <= 64 * 1024 * 1024)
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phys |= 0x40;
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else if (coverage <= 128 * 1024 * 1024)
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phys |= 0x20;
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}
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nv_wo32(pgd, (pde * 8) + 0, lower_32_bits(phys));
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nv_wo32(pgd, (pde * 8) + 4, upper_32_bits(phys));
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}
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static inline u64
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nv50_vm_addr(struct nouveau_vma *vma, u64 phys, u32 memtype, u32 target)
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{
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struct drm_nouveau_private *dev_priv = vma->vm->dev->dev_private;
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phys |= 1; /* present */
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phys |= (u64)memtype << 40;
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/* IGPs don't have real VRAM, re-target to stolen system memory */
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if (target == 0 && dev_priv->vram_sys_base) {
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phys += dev_priv->vram_sys_base;
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target = 3;
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}
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phys |= target << 4;
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if (vma->access & NV_MEM_ACCESS_SYS)
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phys |= (1 << 6);
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if (!(vma->access & NV_MEM_ACCESS_WO))
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phys |= (1 << 3);
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return phys;
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}
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void
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nv50_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
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struct nouveau_mem *mem, u32 pte, u32 cnt, u64 phys, u64 delta)
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{
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u32 comp = (mem->memtype & 0x180) >> 7;
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u32 block;
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int i;
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phys = nv50_vm_addr(vma, phys, mem->memtype, 0);
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pte <<= 3;
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cnt <<= 3;
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while (cnt) {
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u32 offset_h = upper_32_bits(phys);
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u32 offset_l = lower_32_bits(phys);
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for (i = 7; i >= 0; i--) {
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block = 1 << (i + 3);
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if (cnt >= block && !(pte & (block - 1)))
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break;
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}
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offset_l |= (i << 7);
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phys += block << (vma->node->type - 3);
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cnt -= block;
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if (comp) {
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u32 tag = mem->tag->start + ((delta >> 16) * comp);
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offset_h |= (tag << 17);
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delta += block << (vma->node->type - 3);
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}
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while (block) {
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nv_wo32(pgt, pte + 0, offset_l);
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nv_wo32(pgt, pte + 4, offset_h);
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pte += 8;
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block -= 8;
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}
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}
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}
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void
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nv50_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
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struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list)
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{
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pte <<= 3;
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while (cnt--) {
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u64 phys = nv50_vm_addr(vma, (u64)*list++, mem->memtype, 2);
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nv_wo32(pgt, pte + 0, lower_32_bits(phys));
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nv_wo32(pgt, pte + 4, upper_32_bits(phys));
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pte += 8;
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}
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}
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void
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nv50_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
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{
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pte <<= 3;
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while (cnt--) {
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nv_wo32(pgt, pte + 0, 0x00000000);
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nv_wo32(pgt, pte + 4, 0x00000000);
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pte += 8;
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}
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}
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void
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nv50_vm_flush(struct nouveau_vm *vm)
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{
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struct drm_nouveau_private *dev_priv = vm->dev->dev_private;
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struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
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struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
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int i;
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pinstmem->flush(vm->dev);
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/* BAR */
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if (vm == dev_priv->bar1_vm || vm == dev_priv->bar3_vm) {
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nv50_vm_flush_engine(vm->dev, 6);
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return;
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}
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pfifo->tlb_flush(vm->dev);
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for (i = 0; i < NVOBJ_ENGINE_NR; i++) {
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if (atomic_read(&vm->engref[i]))
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dev_priv->eng[i]->tlb_flush(vm->dev, i);
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}
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}
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void
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nv50_vm_flush_engine(struct drm_device *dev, int engine)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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unsigned long flags;
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spin_lock_irqsave(&dev_priv->vm_lock, flags);
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nv_wr32(dev, 0x100c80, (engine << 16) | 1);
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if (!nv_wait(dev, 0x100c80, 0x00000001, 0x00000000))
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NV_ERROR(dev, "vm flush timeout: engine %d\n", engine);
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spin_unlock_irqrestore(&dev_priv->vm_lock, flags);
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}
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