![Ben Skeggs](/assets/img/avatar_default.png)
- moves out of nouveau_bios.c and demagics the logical state definitions - simplifies chipset-specific driver interface - makes most of gpio irq handling common, will use for nv4x hpd later - api extended to allow both direct gpio access, and access using the logical function states - api extended to allow for future use of gpio extender chips - pre-nv50 was handled very badly, the main issue being that all GPIOs were being treated as output-only. - fixes nvd0 so gpio changes actually stick, magic reg needs bashing Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
140 lines
3.6 KiB
C
140 lines
3.6 KiB
C
/*
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* Copyright 2010 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "drmP.h"
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#include "nouveau_drv.h"
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#include "nouveau_hw.h"
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#include "nouveau_gpio.h"
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#include "nv50_display.h"
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static int
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nv50_gpio_location(int line, u32 *reg, u32 *shift)
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{
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const uint32_t nv50_gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 };
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if (line >= 32)
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return -EINVAL;
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*reg = nv50_gpio_reg[line >> 3];
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*shift = (line & 7) << 2;
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return 0;
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}
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int
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nv50_gpio_drive(struct drm_device *dev, int line, int dir, int out)
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{
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u32 reg, shift;
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if (nv50_gpio_location(line, ®, &shift))
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return -EINVAL;
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nv_mask(dev, reg, 7 << shift, (((dir ^ 1) << 1) | out) << shift);
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return 0;
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}
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int
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nv50_gpio_sense(struct drm_device *dev, int line)
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{
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u32 reg, shift;
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if (nv50_gpio_location(line, ®, &shift))
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return -EINVAL;
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return !!(nv_rd32(dev, reg) & (4 << shift));
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}
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void
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nv50_gpio_irq_enable(struct drm_device *dev, int line, bool on)
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{
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u32 reg = line < 16 ? 0xe050 : 0xe070;
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u32 mask = 0x00010001 << (line & 0xf);
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nv_wr32(dev, reg + 4, mask);
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nv_mask(dev, reg + 0, mask, on ? mask : 0);
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}
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int
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nvd0_gpio_drive(struct drm_device *dev, int line, int dir, int out)
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{
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u32 data = ((dir ^ 1) << 13) | (out << 12);
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nv_mask(dev, 0x00d610 + (line * 4), 0x00003000, data);
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nv_mask(dev, 0x00d604, 0x00000001, 0x00000001); /* update? */
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return 0;
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}
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int
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nvd0_gpio_sense(struct drm_device *dev, int line)
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{
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return !!(nv_rd32(dev, 0x00d610 + (line * 4)) & 0x00004000);
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}
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static void
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nv50_gpio_isr(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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u32 intr0, intr1 = 0;
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u32 hi, lo;
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intr0 = nv_rd32(dev, 0xe054) & nv_rd32(dev, 0xe050);
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if (dev_priv->chipset >= 0x90)
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intr1 = nv_rd32(dev, 0xe074) & nv_rd32(dev, 0xe070);
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hi = (intr0 & 0x0000ffff) | (intr1 << 16);
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lo = (intr0 >> 16) | (intr1 & 0xffff0000);
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nouveau_gpio_isr(dev, 0, hi | lo);
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nv_wr32(dev, 0xe054, intr0);
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if (dev_priv->chipset >= 0x90)
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nv_wr32(dev, 0xe074, intr1);
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}
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int
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nv50_gpio_init(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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/* disable, and ack any pending gpio interrupts */
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nv_wr32(dev, 0xe050, 0x00000000);
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nv_wr32(dev, 0xe054, 0xffffffff);
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if (dev_priv->chipset >= 0x90) {
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nv_wr32(dev, 0xe070, 0x00000000);
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nv_wr32(dev, 0xe074, 0xffffffff);
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}
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nouveau_irq_register(dev, 21, nv50_gpio_isr);
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return 0;
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}
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void
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nv50_gpio_fini(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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nv_wr32(dev, 0xe050, 0x00000000);
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if (dev_priv->chipset >= 0x90)
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nv_wr32(dev, 0xe070, 0x00000000);
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nouveau_irq_unregister(dev, 21);
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}
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