![Ben Skeggs](/assets/img/avatar_default.png)
- moves out of nouveau_bios.c and demagics the logical state definitions - simplifies chipset-specific driver interface - makes most of gpio irq handling common, will use for nv4x hpd later - api extended to allow both direct gpio access, and access using the logical function states - api extended to allow for future use of gpio extender chips - pre-nv50 was handled very badly, the main issue being that all GPIOs were being treated as output-only. - fixes nvd0 so gpio changes actually stick, magic reg needs bashing Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
733 lines
18 KiB
C
733 lines
18 KiB
C
/*
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* Copyright 2009 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "drmP.h"
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#include "nouveau_drv.h"
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#include "nouveau_i2c.h"
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#include "nouveau_connector.h"
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#include "nouveau_encoder.h"
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#include "nouveau_crtc.h"
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#include "nouveau_gpio.h"
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/******************************************************************************
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* aux channel util functions
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*****************************************************************************/
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#define AUX_DBG(fmt, args...) do { \
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if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_AUXCH) { \
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NV_PRINTK(KERN_DEBUG, dev, "AUXCH(%d): " fmt, ch, ##args); \
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} \
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} while (0)
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#define AUX_ERR(fmt, args...) NV_ERROR(dev, "AUXCH(%d): " fmt, ch, ##args)
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static void
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auxch_fini(struct drm_device *dev, int ch)
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{
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nv_mask(dev, 0x00e4e4 + (ch * 0x50), 0x00310000, 0x00000000);
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}
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static int
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auxch_init(struct drm_device *dev, int ch)
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{
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const u32 unksel = 1; /* nfi which to use, or if it matters.. */
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const u32 ureq = unksel ? 0x00100000 : 0x00200000;
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const u32 urep = unksel ? 0x01000000 : 0x02000000;
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u32 ctrl, timeout;
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/* wait up to 1ms for any previous transaction to be done... */
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timeout = 1000;
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do {
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ctrl = nv_rd32(dev, 0x00e4e4 + (ch * 0x50));
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udelay(1);
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if (!timeout--) {
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AUX_ERR("begin idle timeout 0x%08x", ctrl);
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return -EBUSY;
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}
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} while (ctrl & 0x03010000);
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/* set some magic, and wait up to 1ms for it to appear */
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nv_mask(dev, 0x00e4e4 + (ch * 0x50), 0x00300000, ureq);
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timeout = 1000;
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do {
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ctrl = nv_rd32(dev, 0x00e4e4 + (ch * 0x50));
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udelay(1);
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if (!timeout--) {
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AUX_ERR("magic wait 0x%08x\n", ctrl);
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auxch_fini(dev, ch);
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return -EBUSY;
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}
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} while ((ctrl & 0x03000000) != urep);
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return 0;
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}
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static int
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auxch_tx(struct drm_device *dev, int ch, u8 type, u32 addr, u8 *data, u8 size)
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{
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u32 ctrl, stat, timeout, retries;
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u32 xbuf[4] = {};
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int ret, i;
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AUX_DBG("%d: 0x%08x %d\n", type, addr, size);
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ret = auxch_init(dev, ch);
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if (ret)
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goto out;
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stat = nv_rd32(dev, 0x00e4e8 + (ch * 0x50));
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if (!(stat & 0x10000000)) {
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AUX_DBG("sink not detected\n");
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ret = -ENXIO;
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goto out;
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}
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if (!(type & 1)) {
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memcpy(xbuf, data, size);
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for (i = 0; i < 16; i += 4) {
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AUX_DBG("wr 0x%08x\n", xbuf[i / 4]);
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nv_wr32(dev, 0x00e4c0 + (ch * 0x50) + i, xbuf[i / 4]);
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}
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}
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ctrl = nv_rd32(dev, 0x00e4e4 + (ch * 0x50));
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ctrl &= ~0x0001f0ff;
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ctrl |= type << 12;
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ctrl |= size - 1;
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nv_wr32(dev, 0x00e4e0 + (ch * 0x50), addr);
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/* retry transaction a number of times on failure... */
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ret = -EREMOTEIO;
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for (retries = 0; retries < 32; retries++) {
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/* reset, and delay a while if this is a retry */
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nv_wr32(dev, 0x00e4e4 + (ch * 0x50), 0x80000000 | ctrl);
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nv_wr32(dev, 0x00e4e4 + (ch * 0x50), 0x00000000 | ctrl);
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if (retries)
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udelay(400);
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/* transaction request, wait up to 1ms for it to complete */
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nv_wr32(dev, 0x00e4e4 + (ch * 0x50), 0x00010000 | ctrl);
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timeout = 1000;
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do {
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ctrl = nv_rd32(dev, 0x00e4e4 + (ch * 0x50));
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udelay(1);
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if (!timeout--) {
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AUX_ERR("tx req timeout 0x%08x\n", ctrl);
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goto out;
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}
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} while (ctrl & 0x00010000);
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/* read status, and check if transaction completed ok */
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stat = nv_mask(dev, 0x00e4e8 + (ch * 0x50), 0, 0);
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if (!(stat & 0x000f0f00)) {
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ret = 0;
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break;
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}
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AUX_DBG("%02d 0x%08x 0x%08x\n", retries, ctrl, stat);
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}
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if (type & 1) {
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for (i = 0; i < 16; i += 4) {
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xbuf[i / 4] = nv_rd32(dev, 0x00e4d0 + (ch * 0x50) + i);
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AUX_DBG("rd 0x%08x\n", xbuf[i / 4]);
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}
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memcpy(data, xbuf, size);
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}
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out:
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auxch_fini(dev, ch);
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return ret;
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}
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static u32
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dp_link_bw_get(struct drm_device *dev, int or, int link)
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{
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u32 ctrl = nv_rd32(dev, 0x614300 + (or * 0x800));
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if (!(ctrl & 0x000c0000))
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return 162000;
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return 270000;
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}
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static int
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dp_lane_count_get(struct drm_device *dev, int or, int link)
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{
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u32 ctrl = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
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switch (ctrl & 0x000f0000) {
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case 0x00010000: return 1;
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case 0x00030000: return 2;
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default:
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return 4;
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}
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}
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void
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nouveau_dp_tu_update(struct drm_device *dev, int or, int link, u32 clk, u32 bpp)
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{
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const u32 symbol = 100000;
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int bestTU = 0, bestVTUi = 0, bestVTUf = 0, bestVTUa = 0;
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int TU, VTUi, VTUf, VTUa;
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u64 link_data_rate, link_ratio, unk;
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u32 best_diff = 64 * symbol;
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u32 link_nr, link_bw, r;
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/* calculate packed data rate for each lane */
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link_nr = dp_lane_count_get(dev, or, link);
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link_data_rate = (clk * bpp / 8) / link_nr;
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/* calculate ratio of packed data rate to link symbol rate */
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link_bw = dp_link_bw_get(dev, or, link);
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link_ratio = link_data_rate * symbol;
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r = do_div(link_ratio, link_bw);
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for (TU = 64; TU >= 32; TU--) {
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/* calculate average number of valid symbols in each TU */
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u32 tu_valid = link_ratio * TU;
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u32 calc, diff;
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/* find a hw representation for the fraction.. */
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VTUi = tu_valid / symbol;
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calc = VTUi * symbol;
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diff = tu_valid - calc;
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if (diff) {
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if (diff >= (symbol / 2)) {
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VTUf = symbol / (symbol - diff);
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if (symbol - (VTUf * diff))
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VTUf++;
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if (VTUf <= 15) {
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VTUa = 1;
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calc += symbol - (symbol / VTUf);
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} else {
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VTUa = 0;
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VTUf = 1;
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calc += symbol;
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}
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} else {
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VTUa = 0;
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VTUf = min((int)(symbol / diff), 15);
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calc += symbol / VTUf;
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}
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diff = calc - tu_valid;
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} else {
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/* no remainder, but the hw doesn't like the fractional
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* part to be zero. decrement the integer part and
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* have the fraction add a whole symbol back
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*/
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VTUa = 0;
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VTUf = 1;
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VTUi--;
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}
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if (diff < best_diff) {
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best_diff = diff;
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bestTU = TU;
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bestVTUa = VTUa;
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bestVTUf = VTUf;
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bestVTUi = VTUi;
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if (diff == 0)
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break;
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}
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}
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if (!bestTU) {
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NV_ERROR(dev, "DP: unable to find suitable config\n");
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return;
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}
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/* XXX close to vbios numbers, but not right */
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unk = (symbol - link_ratio) * bestTU;
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unk *= link_ratio;
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r = do_div(unk, symbol);
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r = do_div(unk, symbol);
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unk += 6;
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nv_mask(dev, NV50_SOR_DP_CTRL(or, link), 0x000001fc, bestTU << 2);
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nv_mask(dev, NV50_SOR_DP_SCFG(or, link), 0x010f7f3f, bestVTUa << 24 |
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bestVTUf << 16 |
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bestVTUi << 8 |
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unk);
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}
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u8 *
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nouveau_dp_bios_data(struct drm_device *dev, struct dcb_entry *dcb, u8 **entry)
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{
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struct bit_entry d;
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u8 *table;
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int i;
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if (bit_table(dev, 'd', &d)) {
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NV_ERROR(dev, "BIT 'd' table not found\n");
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return NULL;
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}
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if (d.version != 1) {
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NV_ERROR(dev, "BIT 'd' table version %d unknown\n", d.version);
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return NULL;
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}
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table = ROMPTR(dev, d.data[0]);
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if (!table) {
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NV_ERROR(dev, "displayport table pointer invalid\n");
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return NULL;
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}
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switch (table[0]) {
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case 0x20:
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case 0x21:
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case 0x30:
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break;
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default:
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NV_ERROR(dev, "displayport table 0x%02x unknown\n", table[0]);
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return NULL;
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}
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for (i = 0; i < table[3]; i++) {
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*entry = ROMPTR(dev, table[table[1] + (i * table[2])]);
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if (*entry && bios_encoder_match(dcb, ROM32((*entry)[0])))
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return table;
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}
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NV_ERROR(dev, "displayport encoder table not found\n");
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return NULL;
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}
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/******************************************************************************
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* link training
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*****************************************************************************/
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struct dp_state {
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struct dcb_entry *dcb;
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u8 *table;
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u8 *entry;
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int auxch;
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int crtc;
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int or;
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int link;
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u8 *dpcd;
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int link_nr;
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u32 link_bw;
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u8 stat[6];
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u8 conf[4];
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};
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static void
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dp_set_link_config(struct drm_device *dev, struct dp_state *dp)
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{
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int or = dp->or, link = dp->link;
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u8 *entry, sink[2];
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u32 dp_ctrl;
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u16 script;
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NV_DEBUG_KMS(dev, "%d lanes at %d KB/s\n", dp->link_nr, dp->link_bw);
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/* set selected link rate on source */
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switch (dp->link_bw) {
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case 270000:
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nv_mask(dev, 0x614300 + (or * 0x800), 0x000c0000, 0x00040000);
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sink[0] = DP_LINK_BW_2_7;
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break;
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default:
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nv_mask(dev, 0x614300 + (or * 0x800), 0x000c0000, 0x00000000);
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sink[0] = DP_LINK_BW_1_62;
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break;
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}
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/* offset +0x0a of each dp encoder table entry is a pointer to another
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* table, that has (among other things) pointers to more scripts that
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* need to be executed, this time depending on link speed.
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*/
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entry = ROMPTR(dev, dp->entry[10]);
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if (entry) {
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if (dp->table[0] < 0x30) {
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while (dp->link_bw < (ROM16(entry[0]) * 10))
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entry += 4;
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script = ROM16(entry[2]);
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} else {
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while (dp->link_bw < (entry[0] * 27000))
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entry += 3;
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script = ROM16(entry[1]);
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}
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nouveau_bios_run_init_table(dev, script, dp->dcb, dp->crtc);
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}
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/* configure lane count on the source */
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dp_ctrl = ((1 << dp->link_nr) - 1) << 16;
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sink[1] = dp->link_nr;
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if (dp->dpcd[2] & DP_ENHANCED_FRAME_CAP) {
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dp_ctrl |= 0x00004000;
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sink[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
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}
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nv_mask(dev, NV50_SOR_DP_CTRL(or, link), 0x001f4000, dp_ctrl);
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/* inform the sink of the new configuration */
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auxch_tx(dev, dp->auxch, 8, DP_LINK_BW_SET, sink, 2);
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}
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static void
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dp_set_training_pattern(struct drm_device *dev, struct dp_state *dp, u8 tp)
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{
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u8 sink_tp;
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NV_DEBUG_KMS(dev, "training pattern %d\n", tp);
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nv_mask(dev, NV50_SOR_DP_CTRL(dp->or, dp->link), 0x0f000000, tp << 24);
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auxch_tx(dev, dp->auxch, 9, DP_TRAINING_PATTERN_SET, &sink_tp, 1);
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sink_tp &= ~DP_TRAINING_PATTERN_MASK;
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sink_tp |= tp;
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auxch_tx(dev, dp->auxch, 8, DP_TRAINING_PATTERN_SET, &sink_tp, 1);
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}
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static const u8 nv50_lane_map[] = { 16, 8, 0, 24 };
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static const u8 nvaf_lane_map[] = { 24, 16, 8, 0 };
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static int
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dp_link_train_commit(struct drm_device *dev, struct dp_state *dp)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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u32 mask = 0, drv = 0, pre = 0, unk = 0;
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const u8 *shifts;
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int link = dp->link;
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int or = dp->or;
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int i;
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if (dev_priv->chipset != 0xaf)
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shifts = nv50_lane_map;
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else
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shifts = nvaf_lane_map;
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for (i = 0; i < dp->link_nr; i++) {
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u8 *conf = dp->entry + dp->table[4];
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u8 lane = (dp->stat[4 + (i >> 1)] >> ((i & 1) * 4)) & 0xf;
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u8 lpre = (lane & 0x0c) >> 2;
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u8 lvsw = (lane & 0x03) >> 0;
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mask |= 0xff << shifts[i];
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unk |= 1 << (shifts[i] >> 3);
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dp->conf[i] = (lpre << 3) | lvsw;
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if (lvsw == DP_TRAIN_VOLTAGE_SWING_1200)
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dp->conf[i] |= DP_TRAIN_MAX_SWING_REACHED;
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if (lpre == DP_TRAIN_PRE_EMPHASIS_9_5)
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dp->conf[i] |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
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NV_DEBUG_KMS(dev, "config lane %d %02x\n", i, dp->conf[i]);
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if (dp->table[0] < 0x30) {
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u8 *last = conf + (dp->entry[4] * dp->table[5]);
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while (lvsw != conf[0] || lpre != conf[1]) {
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conf += dp->table[5];
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if (conf >= last)
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return -EINVAL;
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}
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conf += 2;
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} else {
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/* no lookup table anymore, set entries for each
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* combination of voltage swing and pre-emphasis
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* level allowed by the DP spec.
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*/
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switch (lvsw) {
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case 0: lpre += 0; break;
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case 1: lpre += 4; break;
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case 2: lpre += 7; break;
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case 3: lpre += 9; break;
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}
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conf = conf + (lpre * dp->table[5]);
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conf++;
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}
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drv |= conf[0] << shifts[i];
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pre |= conf[1] << shifts[i];
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unk = (unk & ~0x0000ff00) | (conf[2] << 8);
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}
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nv_mask(dev, NV50_SOR_DP_UNK118(or, link), mask, drv);
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nv_mask(dev, NV50_SOR_DP_UNK120(or, link), mask, pre);
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nv_mask(dev, NV50_SOR_DP_UNK130(or, link), 0x0000ff0f, unk);
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return auxch_tx(dev, dp->auxch, 8, DP_TRAINING_LANE0_SET, dp->conf, 4);
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}
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static int
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dp_link_train_update(struct drm_device *dev, struct dp_state *dp, u32 delay)
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{
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int ret;
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udelay(delay);
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|
|
ret = auxch_tx(dev, dp->auxch, 9, DP_LANE0_1_STATUS, dp->stat, 6);
|
|
if (ret)
|
|
return ret;
|
|
|
|
NV_DEBUG_KMS(dev, "status %02x %02x %02x %02x %02x %02x\n",
|
|
dp->stat[0], dp->stat[1], dp->stat[2], dp->stat[3],
|
|
dp->stat[4], dp->stat[5]);
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
dp_link_train_cr(struct drm_device *dev, struct dp_state *dp)
|
|
{
|
|
bool cr_done = false, abort = false;
|
|
int voltage = dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
|
|
int tries = 0, i;
|
|
|
|
dp_set_training_pattern(dev, dp, DP_TRAINING_PATTERN_1);
|
|
|
|
do {
|
|
if (dp_link_train_commit(dev, dp) ||
|
|
dp_link_train_update(dev, dp, 100))
|
|
break;
|
|
|
|
cr_done = true;
|
|
for (i = 0; i < dp->link_nr; i++) {
|
|
u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
|
|
if (!(lane & DP_LANE_CR_DONE)) {
|
|
cr_done = false;
|
|
if (dp->conf[i] & DP_TRAIN_MAX_SWING_REACHED)
|
|
abort = true;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if ((dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK) != voltage) {
|
|
voltage = dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
|
|
tries = 0;
|
|
}
|
|
} while (!cr_done && !abort && ++tries < 5);
|
|
|
|
return cr_done ? 0 : -1;
|
|
}
|
|
|
|
static int
|
|
dp_link_train_eq(struct drm_device *dev, struct dp_state *dp)
|
|
{
|
|
bool eq_done, cr_done = true;
|
|
int tries = 0, i;
|
|
|
|
dp_set_training_pattern(dev, dp, DP_TRAINING_PATTERN_2);
|
|
|
|
do {
|
|
if (dp_link_train_update(dev, dp, 400))
|
|
break;
|
|
|
|
eq_done = !!(dp->stat[2] & DP_INTERLANE_ALIGN_DONE);
|
|
for (i = 0; i < dp->link_nr && eq_done; i++) {
|
|
u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
|
|
if (!(lane & DP_LANE_CR_DONE))
|
|
cr_done = false;
|
|
if (!(lane & DP_LANE_CHANNEL_EQ_DONE) ||
|
|
!(lane & DP_LANE_SYMBOL_LOCKED))
|
|
eq_done = false;
|
|
}
|
|
|
|
if (dp_link_train_commit(dev, dp))
|
|
break;
|
|
} while (!eq_done && cr_done && ++tries <= 5);
|
|
|
|
return eq_done ? 0 : -1;
|
|
}
|
|
|
|
bool
|
|
nouveau_dp_link_train(struct drm_encoder *encoder, u32 datarate)
|
|
{
|
|
struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
|
|
struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
|
|
struct nouveau_connector *nv_connector =
|
|
nouveau_encoder_connector_get(nv_encoder);
|
|
struct drm_device *dev = encoder->dev;
|
|
struct nouveau_i2c_chan *auxch;
|
|
const u32 bw_list[] = { 270000, 162000, 0 };
|
|
const u32 *link_bw = bw_list;
|
|
struct dp_state dp;
|
|
|
|
auxch = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index);
|
|
if (!auxch)
|
|
return false;
|
|
|
|
dp.table = nouveau_dp_bios_data(dev, nv_encoder->dcb, &dp.entry);
|
|
if (!dp.table)
|
|
return -EINVAL;
|
|
|
|
dp.dcb = nv_encoder->dcb;
|
|
dp.crtc = nv_crtc->index;
|
|
dp.auxch = auxch->drive;
|
|
dp.or = nv_encoder->or;
|
|
dp.link = !(nv_encoder->dcb->sorconf.link & 1);
|
|
dp.dpcd = nv_encoder->dp.dpcd;
|
|
|
|
/* some sinks toggle hotplug in response to some of the actions
|
|
* we take during link training (DP_SET_POWER is one), we need
|
|
* to ignore them for the moment to avoid races.
|
|
*/
|
|
nouveau_gpio_irq(dev, 0, nv_connector->hpd, 0xff, false);
|
|
|
|
/* enable down-spreading, if possible */
|
|
if (dp.table[1] >= 16) {
|
|
u16 script = ROM16(dp.entry[14]);
|
|
if (nv_encoder->dp.dpcd[3] & 1)
|
|
script = ROM16(dp.entry[12]);
|
|
|
|
nouveau_bios_run_init_table(dev, script, dp.dcb, dp.crtc);
|
|
}
|
|
|
|
/* execute pre-train script from vbios */
|
|
nouveau_bios_run_init_table(dev, ROM16(dp.entry[6]), dp.dcb, dp.crtc);
|
|
|
|
/* start off at highest link rate supported by encoder and display */
|
|
while (*link_bw > nv_encoder->dp.link_bw)
|
|
link_bw++;
|
|
|
|
while (link_bw[0]) {
|
|
/* find minimum required lane count at this link rate */
|
|
dp.link_nr = nv_encoder->dp.link_nr;
|
|
while ((dp.link_nr >> 1) * link_bw[0] > datarate)
|
|
dp.link_nr >>= 1;
|
|
|
|
/* drop link rate to minimum with this lane count */
|
|
while ((link_bw[1] * dp.link_nr) > datarate)
|
|
link_bw++;
|
|
dp.link_bw = link_bw[0];
|
|
|
|
/* program selected link configuration */
|
|
dp_set_link_config(dev, &dp);
|
|
|
|
/* attempt to train the link at this configuration */
|
|
memset(dp.stat, 0x00, sizeof(dp.stat));
|
|
if (!dp_link_train_cr(dev, &dp) &&
|
|
!dp_link_train_eq(dev, &dp))
|
|
break;
|
|
|
|
/* retry at lower rate */
|
|
link_bw++;
|
|
}
|
|
|
|
/* finish link training */
|
|
dp_set_training_pattern(dev, &dp, DP_TRAINING_PATTERN_DISABLE);
|
|
|
|
/* execute post-train script from vbios */
|
|
nouveau_bios_run_init_table(dev, ROM16(dp.entry[8]), dp.dcb, dp.crtc);
|
|
|
|
/* re-enable hotplug detect */
|
|
nouveau_gpio_irq(dev, 0, nv_connector->hpd, 0xff, true);
|
|
return true;
|
|
}
|
|
|
|
bool
|
|
nouveau_dp_detect(struct drm_encoder *encoder)
|
|
{
|
|
struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
|
|
struct drm_device *dev = encoder->dev;
|
|
struct nouveau_i2c_chan *auxch;
|
|
u8 *dpcd = nv_encoder->dp.dpcd;
|
|
int ret;
|
|
|
|
auxch = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index);
|
|
if (!auxch)
|
|
return false;
|
|
|
|
ret = auxch_tx(dev, auxch->drive, 9, DP_DPCD_REV, dpcd, 8);
|
|
if (ret)
|
|
return false;
|
|
|
|
nv_encoder->dp.link_bw = 27000 * dpcd[1];
|
|
nv_encoder->dp.link_nr = dpcd[2] & DP_MAX_LANE_COUNT_MASK;
|
|
|
|
NV_DEBUG_KMS(dev, "display: %dx%d dpcd 0x%02x\n",
|
|
nv_encoder->dp.link_nr, nv_encoder->dp.link_bw, dpcd[0]);
|
|
NV_DEBUG_KMS(dev, "encoder: %dx%d\n",
|
|
nv_encoder->dcb->dpconf.link_nr,
|
|
nv_encoder->dcb->dpconf.link_bw);
|
|
|
|
if (nv_encoder->dcb->dpconf.link_nr < nv_encoder->dp.link_nr)
|
|
nv_encoder->dp.link_nr = nv_encoder->dcb->dpconf.link_nr;
|
|
if (nv_encoder->dcb->dpconf.link_bw < nv_encoder->dp.link_bw)
|
|
nv_encoder->dp.link_bw = nv_encoder->dcb->dpconf.link_bw;
|
|
|
|
NV_DEBUG_KMS(dev, "maximum: %dx%d\n",
|
|
nv_encoder->dp.link_nr, nv_encoder->dp.link_bw);
|
|
|
|
return true;
|
|
}
|
|
|
|
int
|
|
nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
|
|
uint8_t *data, int data_nr)
|
|
{
|
|
return auxch_tx(auxch->dev, auxch->drive, cmd, addr, data, data_nr);
|
|
}
|
|
|
|
static int
|
|
nouveau_dp_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
|
|
{
|
|
struct nouveau_i2c_chan *auxch = (struct nouveau_i2c_chan *)adap;
|
|
struct i2c_msg *msg = msgs;
|
|
int ret, mcnt = num;
|
|
|
|
while (mcnt--) {
|
|
u8 remaining = msg->len;
|
|
u8 *ptr = msg->buf;
|
|
|
|
while (remaining) {
|
|
u8 cnt = (remaining > 16) ? 16 : remaining;
|
|
u8 cmd;
|
|
|
|
if (msg->flags & I2C_M_RD)
|
|
cmd = AUX_I2C_READ;
|
|
else
|
|
cmd = AUX_I2C_WRITE;
|
|
|
|
if (mcnt || remaining > 16)
|
|
cmd |= AUX_I2C_MOT;
|
|
|
|
ret = nouveau_dp_auxch(auxch, cmd, msg->addr, ptr, cnt);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
ptr += cnt;
|
|
remaining -= cnt;
|
|
}
|
|
|
|
msg++;
|
|
}
|
|
|
|
return num;
|
|
}
|
|
|
|
static u32
|
|
nouveau_dp_i2c_func(struct i2c_adapter *adap)
|
|
{
|
|
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
|
|
}
|
|
|
|
const struct i2c_algorithm nouveau_dp_i2c_algo = {
|
|
.master_xfer = nouveau_dp_i2c_xfer,
|
|
.functionality = nouveau_dp_i2c_func
|
|
};
|