![Alan Cox](/assets/img/avatar_default.png)
Now that we pull the right BIOS data out of the hat we need to use it when doing our panel setup. Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
513 lines
15 KiB
C
513 lines
15 KiB
C
/**************************************************************************
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* Copyright (c) 2011, Intel Corporation.
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* All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*
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**************************************************************************/
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#include <linux/backlight.h>
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#include <linux/module.h>
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#include <linux/dmi.h>
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#include <drm/drmP.h>
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#include <drm/drm.h>
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#include "gma_drm.h"
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#include "psb_drv.h"
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#include "psb_reg.h"
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#include "psb_intel_reg.h"
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#include <asm/mrst.h>
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#include <asm/intel_scu_ipc.h>
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#include "mid_bios.h"
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#include "intel_bios.h"
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static int oaktrail_output_init(struct drm_device *dev)
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{
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struct drm_psb_private *dev_priv = dev->dev_private;
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if (dev_priv->iLVDS_enable)
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oaktrail_lvds_init(dev, &dev_priv->mode_dev);
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else
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dev_err(dev->dev, "DSI is not supported\n");
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if (dev_priv->hdmi_priv)
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oaktrail_hdmi_init(dev, &dev_priv->mode_dev);
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return 0;
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}
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/*
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* Provide the low level interfaces for the Moorestown backlight
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*/
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#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
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#define MRST_BLC_MAX_PWM_REG_FREQ 0xFFFF
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#define BLC_PWM_PRECISION_FACTOR 100 /* 10000000 */
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#define BLC_PWM_FREQ_CALC_CONSTANT 32
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#define MHz 1000000
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#define BLC_ADJUSTMENT_MAX 100
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static struct backlight_device *oaktrail_backlight_device;
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static int oaktrail_brightness;
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static int oaktrail_set_brightness(struct backlight_device *bd)
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{
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struct drm_device *dev = bl_get_data(oaktrail_backlight_device);
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struct drm_psb_private *dev_priv = dev->dev_private;
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int level = bd->props.brightness;
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u32 blc_pwm_ctl;
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u32 max_pwm_blc;
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/* Percentage 1-100% being valid */
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if (level < 1)
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level = 1;
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if (gma_power_begin(dev, 0)) {
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/* Calculate and set the brightness value */
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max_pwm_blc = REG_READ(BLC_PWM_CTL) >> 16;
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blc_pwm_ctl = level * max_pwm_blc / 100;
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/* Adjust the backlight level with the percent in
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* dev_priv->blc_adj1;
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*/
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blc_pwm_ctl = blc_pwm_ctl * dev_priv->blc_adj1;
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blc_pwm_ctl = blc_pwm_ctl / 100;
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/* Adjust the backlight level with the percent in
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* dev_priv->blc_adj2;
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*/
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blc_pwm_ctl = blc_pwm_ctl * dev_priv->blc_adj2;
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blc_pwm_ctl = blc_pwm_ctl / 100;
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/* force PWM bit on */
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REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2)));
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REG_WRITE(BLC_PWM_CTL, (max_pwm_blc << 16) | blc_pwm_ctl);
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gma_power_end(dev);
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}
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oaktrail_brightness = level;
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return 0;
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}
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static int oaktrail_get_brightness(struct backlight_device *bd)
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{
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/* return locally cached var instead of HW read (due to DPST etc.) */
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/* FIXME: ideally return actual value in case firmware fiddled with
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it */
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return oaktrail_brightness;
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}
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static int device_backlight_init(struct drm_device *dev)
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{
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struct drm_psb_private *dev_priv = dev->dev_private;
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unsigned long core_clock;
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u16 bl_max_freq;
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uint32_t value;
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uint32_t blc_pwm_precision_factor;
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dev_priv->blc_adj1 = BLC_ADJUSTMENT_MAX;
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dev_priv->blc_adj2 = BLC_ADJUSTMENT_MAX;
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bl_max_freq = 256;
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/* this needs to be set elsewhere */
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blc_pwm_precision_factor = BLC_PWM_PRECISION_FACTOR;
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core_clock = dev_priv->core_freq;
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value = (core_clock * MHz) / BLC_PWM_FREQ_CALC_CONSTANT;
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value *= blc_pwm_precision_factor;
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value /= bl_max_freq;
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value /= blc_pwm_precision_factor;
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if (value > (unsigned long long)MRST_BLC_MAX_PWM_REG_FREQ)
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return -ERANGE;
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if (gma_power_begin(dev, false)) {
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REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2)));
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REG_WRITE(BLC_PWM_CTL, value | (value << 16));
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gma_power_end(dev);
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}
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return 0;
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}
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static const struct backlight_ops oaktrail_ops = {
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.get_brightness = oaktrail_get_brightness,
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.update_status = oaktrail_set_brightness,
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};
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int oaktrail_backlight_init(struct drm_device *dev)
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{
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struct drm_psb_private *dev_priv = dev->dev_private;
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int ret;
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struct backlight_properties props;
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memset(&props, 0, sizeof(struct backlight_properties));
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props.max_brightness = 100;
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props.type = BACKLIGHT_PLATFORM;
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oaktrail_backlight_device = backlight_device_register("oaktrail-bl",
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NULL, (void *)dev, &oaktrail_ops, &props);
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if (IS_ERR(oaktrail_backlight_device))
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return PTR_ERR(oaktrail_backlight_device);
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ret = device_backlight_init(dev);
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if (ret < 0) {
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backlight_device_unregister(oaktrail_backlight_device);
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return ret;
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}
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oaktrail_backlight_device->props.brightness = 100;
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oaktrail_backlight_device->props.max_brightness = 100;
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backlight_update_status(oaktrail_backlight_device);
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dev_priv->backlight_device = oaktrail_backlight_device;
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return 0;
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}
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#endif
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/*
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* Provide the Moorestown specific chip logic and low level methods
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* for power management
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*/
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static void oaktrail_init_pm(struct drm_device *dev)
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{
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}
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/**
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* oaktrail_save_display_registers - save registers lost on suspend
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* @dev: our DRM device
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*
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* Save the state we need in order to be able to restore the interface
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* upon resume from suspend
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*/
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static int oaktrail_save_display_registers(struct drm_device *dev)
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{
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struct drm_psb_private *dev_priv = dev->dev_private;
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int i;
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u32 pp_stat;
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/* Display arbitration control + watermarks */
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dev_priv->saveDSPARB = PSB_RVDC32(DSPARB);
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dev_priv->saveDSPFW1 = PSB_RVDC32(DSPFW1);
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dev_priv->saveDSPFW2 = PSB_RVDC32(DSPFW2);
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dev_priv->saveDSPFW3 = PSB_RVDC32(DSPFW3);
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dev_priv->saveDSPFW4 = PSB_RVDC32(DSPFW4);
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dev_priv->saveDSPFW5 = PSB_RVDC32(DSPFW5);
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dev_priv->saveDSPFW6 = PSB_RVDC32(DSPFW6);
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dev_priv->saveCHICKENBIT = PSB_RVDC32(DSPCHICKENBIT);
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/* Pipe & plane A info */
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dev_priv->savePIPEACONF = PSB_RVDC32(PIPEACONF);
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dev_priv->savePIPEASRC = PSB_RVDC32(PIPEASRC);
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dev_priv->saveFPA0 = PSB_RVDC32(MRST_FPA0);
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dev_priv->saveFPA1 = PSB_RVDC32(MRST_FPA1);
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dev_priv->saveDPLL_A = PSB_RVDC32(MRST_DPLL_A);
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dev_priv->saveHTOTAL_A = PSB_RVDC32(HTOTAL_A);
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dev_priv->saveHBLANK_A = PSB_RVDC32(HBLANK_A);
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dev_priv->saveHSYNC_A = PSB_RVDC32(HSYNC_A);
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dev_priv->saveVTOTAL_A = PSB_RVDC32(VTOTAL_A);
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dev_priv->saveVBLANK_A = PSB_RVDC32(VBLANK_A);
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dev_priv->saveVSYNC_A = PSB_RVDC32(VSYNC_A);
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dev_priv->saveBCLRPAT_A = PSB_RVDC32(BCLRPAT_A);
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dev_priv->saveDSPACNTR = PSB_RVDC32(DSPACNTR);
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dev_priv->saveDSPASTRIDE = PSB_RVDC32(DSPASTRIDE);
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dev_priv->saveDSPAADDR = PSB_RVDC32(DSPABASE);
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dev_priv->saveDSPASURF = PSB_RVDC32(DSPASURF);
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dev_priv->saveDSPALINOFF = PSB_RVDC32(DSPALINOFF);
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dev_priv->saveDSPATILEOFF = PSB_RVDC32(DSPATILEOFF);
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/* Save cursor regs */
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dev_priv->saveDSPACURSOR_CTRL = PSB_RVDC32(CURACNTR);
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dev_priv->saveDSPACURSOR_BASE = PSB_RVDC32(CURABASE);
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dev_priv->saveDSPACURSOR_POS = PSB_RVDC32(CURAPOS);
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/* Save palette (gamma) */
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for (i = 0; i < 256; i++)
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dev_priv->save_palette_a[i] = PSB_RVDC32(PALETTE_A + (i << 2));
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if (dev_priv->hdmi_priv)
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oaktrail_hdmi_save(dev);
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/* Save performance state */
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dev_priv->savePERF_MODE = PSB_RVDC32(MRST_PERF_MODE);
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/* LVDS state */
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dev_priv->savePP_CONTROL = PSB_RVDC32(PP_CONTROL);
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dev_priv->savePFIT_PGM_RATIOS = PSB_RVDC32(PFIT_PGM_RATIOS);
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dev_priv->savePFIT_AUTO_RATIOS = PSB_RVDC32(PFIT_AUTO_RATIOS);
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dev_priv->saveBLC_PWM_CTL = PSB_RVDC32(BLC_PWM_CTL);
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dev_priv->saveBLC_PWM_CTL2 = PSB_RVDC32(BLC_PWM_CTL2);
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dev_priv->saveLVDS = PSB_RVDC32(LVDS);
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dev_priv->savePFIT_CONTROL = PSB_RVDC32(PFIT_CONTROL);
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dev_priv->savePP_ON_DELAYS = PSB_RVDC32(LVDSPP_ON);
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dev_priv->savePP_OFF_DELAYS = PSB_RVDC32(LVDSPP_OFF);
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dev_priv->savePP_DIVISOR = PSB_RVDC32(PP_CYCLE);
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/* HW overlay */
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dev_priv->saveOV_OVADD = PSB_RVDC32(OV_OVADD);
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dev_priv->saveOV_OGAMC0 = PSB_RVDC32(OV_OGAMC0);
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dev_priv->saveOV_OGAMC1 = PSB_RVDC32(OV_OGAMC1);
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dev_priv->saveOV_OGAMC2 = PSB_RVDC32(OV_OGAMC2);
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dev_priv->saveOV_OGAMC3 = PSB_RVDC32(OV_OGAMC3);
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dev_priv->saveOV_OGAMC4 = PSB_RVDC32(OV_OGAMC4);
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dev_priv->saveOV_OGAMC5 = PSB_RVDC32(OV_OGAMC5);
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/* DPST registers */
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dev_priv->saveHISTOGRAM_INT_CONTROL_REG =
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PSB_RVDC32(HISTOGRAM_INT_CONTROL);
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dev_priv->saveHISTOGRAM_LOGIC_CONTROL_REG =
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PSB_RVDC32(HISTOGRAM_LOGIC_CONTROL);
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dev_priv->savePWM_CONTROL_LOGIC = PSB_RVDC32(PWM_CONTROL_LOGIC);
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if (dev_priv->iLVDS_enable) {
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/* Shut down the panel */
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PSB_WVDC32(0, PP_CONTROL);
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do {
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pp_stat = PSB_RVDC32(PP_STATUS);
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} while (pp_stat & 0x80000000);
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/* Turn off the plane */
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PSB_WVDC32(0x58000000, DSPACNTR);
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/* Trigger the plane disable */
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PSB_WVDC32(0, DSPASURF);
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/* Wait ~4 ticks */
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msleep(4);
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/* Turn off pipe */
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PSB_WVDC32(0x0, PIPEACONF);
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/* Wait ~8 ticks */
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msleep(8);
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/* Turn off PLLs */
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PSB_WVDC32(0, MRST_DPLL_A);
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}
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return 0;
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}
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/**
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* oaktrail_restore_display_registers - restore lost register state
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* @dev: our DRM device
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*
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* Restore register state that was lost during suspend and resume.
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*/
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static int oaktrail_restore_display_registers(struct drm_device *dev)
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{
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struct drm_psb_private *dev_priv = dev->dev_private;
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u32 pp_stat;
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int i;
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/* Display arbitration + watermarks */
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PSB_WVDC32(dev_priv->saveDSPARB, DSPARB);
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PSB_WVDC32(dev_priv->saveDSPFW1, DSPFW1);
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PSB_WVDC32(dev_priv->saveDSPFW2, DSPFW2);
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PSB_WVDC32(dev_priv->saveDSPFW3, DSPFW3);
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PSB_WVDC32(dev_priv->saveDSPFW4, DSPFW4);
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PSB_WVDC32(dev_priv->saveDSPFW5, DSPFW5);
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PSB_WVDC32(dev_priv->saveDSPFW6, DSPFW6);
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PSB_WVDC32(dev_priv->saveCHICKENBIT, DSPCHICKENBIT);
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/* Make sure VGA plane is off. it initializes to on after reset!*/
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PSB_WVDC32(0x80000000, VGACNTRL);
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/* set the plls */
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PSB_WVDC32(dev_priv->saveFPA0, MRST_FPA0);
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PSB_WVDC32(dev_priv->saveFPA1, MRST_FPA1);
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/* Actually enable it */
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PSB_WVDC32(dev_priv->saveDPLL_A, MRST_DPLL_A);
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DRM_UDELAY(150);
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/* Restore mode */
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PSB_WVDC32(dev_priv->saveHTOTAL_A, HTOTAL_A);
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PSB_WVDC32(dev_priv->saveHBLANK_A, HBLANK_A);
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PSB_WVDC32(dev_priv->saveHSYNC_A, HSYNC_A);
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PSB_WVDC32(dev_priv->saveVTOTAL_A, VTOTAL_A);
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PSB_WVDC32(dev_priv->saveVBLANK_A, VBLANK_A);
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PSB_WVDC32(dev_priv->saveVSYNC_A, VSYNC_A);
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PSB_WVDC32(dev_priv->savePIPEASRC, PIPEASRC);
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PSB_WVDC32(dev_priv->saveBCLRPAT_A, BCLRPAT_A);
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/* Restore performance mode*/
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PSB_WVDC32(dev_priv->savePERF_MODE, MRST_PERF_MODE);
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/* Enable the pipe*/
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if (dev_priv->iLVDS_enable)
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PSB_WVDC32(dev_priv->savePIPEACONF, PIPEACONF);
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/* Set up the plane*/
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PSB_WVDC32(dev_priv->saveDSPALINOFF, DSPALINOFF);
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PSB_WVDC32(dev_priv->saveDSPASTRIDE, DSPASTRIDE);
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PSB_WVDC32(dev_priv->saveDSPATILEOFF, DSPATILEOFF);
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/* Enable the plane */
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PSB_WVDC32(dev_priv->saveDSPACNTR, DSPACNTR);
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PSB_WVDC32(dev_priv->saveDSPASURF, DSPASURF);
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/* Enable Cursor A */
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PSB_WVDC32(dev_priv->saveDSPACURSOR_CTRL, CURACNTR);
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PSB_WVDC32(dev_priv->saveDSPACURSOR_POS, CURAPOS);
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PSB_WVDC32(dev_priv->saveDSPACURSOR_BASE, CURABASE);
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/* Restore palette (gamma) */
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for (i = 0; i < 256; i++)
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PSB_WVDC32(dev_priv->save_palette_a[i], PALETTE_A + (i << 2));
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if (dev_priv->hdmi_priv)
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oaktrail_hdmi_restore(dev);
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if (dev_priv->iLVDS_enable) {
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PSB_WVDC32(dev_priv->saveBLC_PWM_CTL2, BLC_PWM_CTL2);
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PSB_WVDC32(dev_priv->saveLVDS, LVDS); /*port 61180h*/
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PSB_WVDC32(dev_priv->savePFIT_CONTROL, PFIT_CONTROL);
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PSB_WVDC32(dev_priv->savePFIT_PGM_RATIOS, PFIT_PGM_RATIOS);
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PSB_WVDC32(dev_priv->savePFIT_AUTO_RATIOS, PFIT_AUTO_RATIOS);
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PSB_WVDC32(dev_priv->saveBLC_PWM_CTL, BLC_PWM_CTL);
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PSB_WVDC32(dev_priv->savePP_ON_DELAYS, LVDSPP_ON);
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PSB_WVDC32(dev_priv->savePP_OFF_DELAYS, LVDSPP_OFF);
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PSB_WVDC32(dev_priv->savePP_DIVISOR, PP_CYCLE);
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PSB_WVDC32(dev_priv->savePP_CONTROL, PP_CONTROL);
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}
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/* Wait for cycle delay */
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do {
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pp_stat = PSB_RVDC32(PP_STATUS);
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} while (pp_stat & 0x08000000);
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/* Wait for panel power up */
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do {
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pp_stat = PSB_RVDC32(PP_STATUS);
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} while (pp_stat & 0x10000000);
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/* Restore HW overlay */
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PSB_WVDC32(dev_priv->saveOV_OVADD, OV_OVADD);
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PSB_WVDC32(dev_priv->saveOV_OGAMC0, OV_OGAMC0);
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PSB_WVDC32(dev_priv->saveOV_OGAMC1, OV_OGAMC1);
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PSB_WVDC32(dev_priv->saveOV_OGAMC2, OV_OGAMC2);
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PSB_WVDC32(dev_priv->saveOV_OGAMC3, OV_OGAMC3);
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PSB_WVDC32(dev_priv->saveOV_OGAMC4, OV_OGAMC4);
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PSB_WVDC32(dev_priv->saveOV_OGAMC5, OV_OGAMC5);
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/* DPST registers */
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PSB_WVDC32(dev_priv->saveHISTOGRAM_INT_CONTROL_REG,
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HISTOGRAM_INT_CONTROL);
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PSB_WVDC32(dev_priv->saveHISTOGRAM_LOGIC_CONTROL_REG,
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HISTOGRAM_LOGIC_CONTROL);
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PSB_WVDC32(dev_priv->savePWM_CONTROL_LOGIC, PWM_CONTROL_LOGIC);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* oaktrail_power_down - power down the display island
|
|
* @dev: our DRM device
|
|
*
|
|
* Power down the display interface of our device
|
|
*/
|
|
static int oaktrail_power_down(struct drm_device *dev)
|
|
{
|
|
struct drm_psb_private *dev_priv = dev->dev_private;
|
|
u32 pwr_mask ;
|
|
u32 pwr_sts;
|
|
|
|
pwr_mask = PSB_PWRGT_DISPLAY_MASK;
|
|
outl(pwr_mask, dev_priv->ospm_base + PSB_PM_SSC);
|
|
|
|
while (true) {
|
|
pwr_sts = inl(dev_priv->ospm_base + PSB_PM_SSS);
|
|
if ((pwr_sts & pwr_mask) == pwr_mask)
|
|
break;
|
|
else
|
|
udelay(10);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* oaktrail_power_up
|
|
*
|
|
* Restore power to the specified island(s) (powergating)
|
|
*/
|
|
static int oaktrail_power_up(struct drm_device *dev)
|
|
{
|
|
struct drm_psb_private *dev_priv = dev->dev_private;
|
|
u32 pwr_mask = PSB_PWRGT_DISPLAY_MASK;
|
|
u32 pwr_sts, pwr_cnt;
|
|
|
|
pwr_cnt = inl(dev_priv->ospm_base + PSB_PM_SSC);
|
|
pwr_cnt &= ~pwr_mask;
|
|
outl(pwr_cnt, (dev_priv->ospm_base + PSB_PM_SSC));
|
|
|
|
while (true) {
|
|
pwr_sts = inl(dev_priv->ospm_base + PSB_PM_SSS);
|
|
if ((pwr_sts & pwr_mask) == 0)
|
|
break;
|
|
else
|
|
udelay(10);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
|
|
static int oaktrail_chip_setup(struct drm_device *dev)
|
|
{
|
|
struct drm_psb_private *dev_priv = dev->dev_private;
|
|
struct oaktrail_vbt *vbt = &dev_priv->vbt_data;
|
|
int ret;
|
|
|
|
ret = mid_chip_setup(dev);
|
|
if (ret < 0)
|
|
return ret;
|
|
if (vbt->size == 0) {
|
|
/* Now pull the BIOS data */
|
|
gma_intel_opregion_init(dev);
|
|
psb_intel_init_bios(dev);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static void oaktrail_teardown(struct drm_device *dev)
|
|
{
|
|
struct drm_psb_private *dev_priv = dev->dev_private;
|
|
struct oaktrail_vbt *vbt = &dev_priv->vbt_data;
|
|
|
|
oaktrail_hdmi_teardown(dev);
|
|
if (vbt->size == 0)
|
|
psb_intel_destroy_bios(dev);
|
|
}
|
|
|
|
const struct psb_ops oaktrail_chip_ops = {
|
|
.name = "Oaktrail",
|
|
.accel_2d = 1,
|
|
.pipes = 2,
|
|
.crtcs = 2,
|
|
.sgx_offset = MRST_SGX_OFFSET,
|
|
|
|
.chip_setup = oaktrail_chip_setup,
|
|
.chip_teardown = oaktrail_teardown,
|
|
.crtc_helper = &oaktrail_helper_funcs,
|
|
.crtc_funcs = &psb_intel_crtc_funcs,
|
|
|
|
.output_init = oaktrail_output_init,
|
|
|
|
#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
|
|
.backlight_init = oaktrail_backlight_init,
|
|
#endif
|
|
|
|
.init_pm = oaktrail_init_pm,
|
|
.save_regs = oaktrail_save_display_registers,
|
|
.restore_regs = oaktrail_restore_display_registers,
|
|
.power_down = oaktrail_power_down,
|
|
.power_up = oaktrail_power_up,
|
|
|
|
.i2c_bus = 1,
|
|
};
|