839 lines
21 KiB
C
839 lines
21 KiB
C
/*
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* lis3l02dq.c support STMicroelectronics LISD02DQ
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* 3d 2g Linear Accelerometers via SPI
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*
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* Copyright (c) 2007 Jonathan Cameron <jic23@cam.ac.uk>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Settings:
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* 16 bit left justified mode used.
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*/
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/gpio.h>
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#include <linux/workqueue.h>
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#include <linux/mutex.h>
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#include <linux/device.h>
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#include <linux/kernel.h>
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#include <linux/spi/spi.h>
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#include <linux/slab.h>
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#include <linux/sysfs.h>
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#include <linux/list.h>
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#include "../iio.h"
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#include "../sysfs.h"
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#include "../ring_generic.h"
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#include "../ring_sw.h"
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#include "accel.h"
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#include "lis3l02dq.h"
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/* At the moment the spi framework doesn't allow global setting of cs_change.
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* It's in the likely to be added comment at the top of spi.h.
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* This means that use cannot be made of spi_write etc.
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*/
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static int __lis3l02dq_spi_read_reg_8(struct lis3l02dq_state *st,
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u8 reg_address, u8 *val)
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{
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struct spi_message msg;
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int ret;
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struct spi_transfer xfer = {
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.tx_buf = st->tx,
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.rx_buf = st->rx,
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.bits_per_word = 8,
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.len = 2,
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.cs_change = 1,
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};
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mutex_lock(&st->buf_lock);
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st->tx[0] = LIS3L02DQ_READ_REG(reg_address);
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st->tx[1] = 0;
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spi_message_init(&msg);
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spi_message_add_tail(&xfer, &msg);
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ret = spi_sync(st->us, &msg);
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*val = st->rx[1];
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mutex_unlock(&st->buf_lock);
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return ret;
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}
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/**
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* lis3l02dq_spi_read_reg_8() - read single byte from a single register
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* @dev: device asosciated with child of actual device (iio_dev or iio_trig)
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* @reg_address: the address of the register to be read
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* @val: pass back the resulting value
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**/
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int lis3l02dq_spi_read_reg_8(struct device *dev, u8 reg_address, u8 *val)
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{
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struct iio_dev *indio_dev = dev_get_drvdata(dev);
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struct iio_sw_ring_helper_state *h = iio_dev_get_devdata(indio_dev);
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struct lis3l02dq_state *st = lis3l02dq_h_to_s(h);
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return __lis3l02dq_spi_read_reg_8(st, reg_address, val);
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}
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/**
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* lis3l02dq_spi_write_reg_8() - write single byte to a register
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* @dev: device associated with child of actual device (iio_dev or iio_trig)
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* @reg_address: the address of the register to be written
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* @val: the value to write
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**/
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int lis3l02dq_spi_write_reg_8(struct device *dev,
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u8 reg_address,
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u8 *val)
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{
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int ret;
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struct spi_message msg;
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struct iio_dev *indio_dev = dev_get_drvdata(dev);
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struct iio_sw_ring_helper_state *h
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= iio_dev_get_devdata(indio_dev);
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struct lis3l02dq_state *st = lis3l02dq_h_to_s(h);
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struct spi_transfer xfer = {
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.tx_buf = st->tx,
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.bits_per_word = 8,
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.len = 2,
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.cs_change = 1,
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};
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mutex_lock(&st->buf_lock);
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st->tx[0] = LIS3L02DQ_WRITE_REG(reg_address);
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st->tx[1] = *val;
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spi_message_init(&msg);
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spi_message_add_tail(&xfer, &msg);
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ret = spi_sync(st->us, &msg);
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mutex_unlock(&st->buf_lock);
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return ret;
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}
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/**
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* lisl302dq_spi_write_reg_s16() - write 2 bytes to a pair of registers
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* @dev: device associated with child of actual device (iio_dev or iio_trig)
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* @reg_address: the address of the lower of the two registers. Second register
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* is assumed to have address one greater.
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* @val: value to be written
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**/
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static int lis3l02dq_spi_write_reg_s16(struct device *dev,
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u8 lower_reg_address,
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s16 value)
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{
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int ret;
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struct spi_message msg;
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struct iio_dev *indio_dev = dev_get_drvdata(dev);
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struct iio_sw_ring_helper_state *h
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= iio_dev_get_devdata(indio_dev);
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struct lis3l02dq_state *st = lis3l02dq_h_to_s(h);
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struct spi_transfer xfers[] = { {
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.tx_buf = st->tx,
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.bits_per_word = 8,
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.len = 2,
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.cs_change = 1,
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}, {
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.tx_buf = st->tx + 2,
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.bits_per_word = 8,
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.len = 2,
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.cs_change = 1,
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},
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};
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mutex_lock(&st->buf_lock);
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st->tx[0] = LIS3L02DQ_WRITE_REG(lower_reg_address);
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st->tx[1] = value & 0xFF;
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st->tx[2] = LIS3L02DQ_WRITE_REG(lower_reg_address + 1);
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st->tx[3] = (value >> 8) & 0xFF;
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spi_message_init(&msg);
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spi_message_add_tail(&xfers[0], &msg);
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spi_message_add_tail(&xfers[1], &msg);
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ret = spi_sync(st->us, &msg);
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mutex_unlock(&st->buf_lock);
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return ret;
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}
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static int lis3l02dq_read_16bit_s(struct lis3l02dq_state *st,
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u8 lower_reg_address,
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int *val)
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{
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struct spi_message msg;
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int ret;
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s16 tempval;
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struct spi_transfer xfers[] = { {
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.tx_buf = st->tx,
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.rx_buf = st->rx,
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.bits_per_word = 8,
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.len = 2,
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.cs_change = 1,
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}, {
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.tx_buf = st->tx + 2,
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.rx_buf = st->rx + 2,
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.bits_per_word = 8,
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.len = 2,
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.cs_change = 0,
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},
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};
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mutex_lock(&st->buf_lock);
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st->tx[0] = LIS3L02DQ_READ_REG(lower_reg_address);
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st->tx[1] = 0;
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st->tx[2] = LIS3L02DQ_READ_REG(lower_reg_address + 1);
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st->tx[3] = 0;
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spi_message_init(&msg);
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spi_message_add_tail(&xfers[0], &msg);
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spi_message_add_tail(&xfers[1], &msg);
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ret = spi_sync(st->us, &msg);
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if (ret) {
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dev_err(&st->us->dev, "problem when reading 16 bit register");
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goto error_ret;
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}
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tempval = (s16)(st->rx[1]) | ((s16)(st->rx[3]) << 8);
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*val = tempval;
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error_ret:
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mutex_unlock(&st->buf_lock);
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return ret;
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}
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enum lis3l02dq_rm_ind {
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LIS3L02DQ_ACCEL,
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LIS3L02DQ_GAIN,
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LIS3L02DQ_BIAS,
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};
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static u8 lis3l02dq_axis_map[3][3] = {
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[LIS3L02DQ_ACCEL] = { LIS3L02DQ_REG_OUT_X_L_ADDR,
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LIS3L02DQ_REG_OUT_Y_L_ADDR,
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LIS3L02DQ_REG_OUT_Z_L_ADDR },
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[LIS3L02DQ_GAIN] = { LIS3L02DQ_REG_GAIN_X_ADDR,
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LIS3L02DQ_REG_GAIN_Y_ADDR,
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LIS3L02DQ_REG_GAIN_Z_ADDR },
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[LIS3L02DQ_BIAS] = { LIS3L02DQ_REG_OFFSET_X_ADDR,
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LIS3L02DQ_REG_OFFSET_Y_ADDR,
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LIS3L02DQ_REG_OFFSET_Z_ADDR }
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};
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static int lis3l02dq_read_thresh(struct iio_dev *indio_dev,
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int e,
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int *val)
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{
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struct iio_sw_ring_helper_state *h
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= iio_dev_get_devdata(indio_dev);
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struct lis3l02dq_state *st = lis3l02dq_h_to_s(h);
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return lis3l02dq_read_16bit_s(st, LIS3L02DQ_REG_THS_L_ADDR, val);
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}
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static int lis3l02dq_write_thresh(struct iio_dev *indio_dev,
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int event_code,
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int val)
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{
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u16 value = val;
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return lis3l02dq_spi_write_reg_s16(&indio_dev->dev,
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LIS3L02DQ_REG_THS_L_ADDR,
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value);
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}
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static int lis3l02dq_read_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int *val,
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int *val2,
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long mask)
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{
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u8 utemp;
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s8 stemp;
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ssize_t ret = 0;
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struct iio_sw_ring_helper_state *h
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= iio_dev_get_devdata(indio_dev);
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struct lis3l02dq_state *st = lis3l02dq_h_to_s(h);
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u8 reg;
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switch (mask) {
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case 0:
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/* Take the iio_dev status lock */
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mutex_lock(&indio_dev->mlock);
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if (indio_dev->currentmode == INDIO_RING_TRIGGERED)
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ret = lis3l02dq_read_accel_from_ring(indio_dev->ring,
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chan->scan_index,
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val);
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else {
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reg = lis3l02dq_axis_map
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[LIS3L02DQ_ACCEL][chan->address];
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ret = lis3l02dq_read_16bit_s(st, reg, val);
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}
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mutex_unlock(&indio_dev->mlock);
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return IIO_VAL_INT;
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case (1 << IIO_CHAN_INFO_SCALE_SHARED):
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*val = 0;
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*val2 = 9580;
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return IIO_VAL_INT_PLUS_MICRO;
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case (1 << IIO_CHAN_INFO_CALIBSCALE_SEPARATE):
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reg = lis3l02dq_axis_map[LIS3L02DQ_GAIN][chan->address];
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ret = __lis3l02dq_spi_read_reg_8(st, reg, &utemp);
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if (ret)
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goto error_ret;
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/* to match with what previous code does */
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*val = utemp;
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return IIO_VAL_INT;
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case (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE):
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reg = lis3l02dq_axis_map[LIS3L02DQ_BIAS][chan->address];
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ret = __lis3l02dq_spi_read_reg_8(st, reg, (u8 *)&stemp);
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/* to match with what previous code does */
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*val = stemp;
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return IIO_VAL_INT;
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}
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error_ret:
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return ret;
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}
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static ssize_t lis3l02dq_read_frequency(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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int ret, len = 0;
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s8 t;
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ret = lis3l02dq_spi_read_reg_8(dev,
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LIS3L02DQ_REG_CTRL_1_ADDR,
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(u8 *)&t);
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if (ret)
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return ret;
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t &= LIS3L02DQ_DEC_MASK;
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switch (t) {
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case LIS3L02DQ_REG_CTRL_1_DF_128:
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len = sprintf(buf, "280\n");
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break;
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case LIS3L02DQ_REG_CTRL_1_DF_64:
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len = sprintf(buf, "560\n");
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break;
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case LIS3L02DQ_REG_CTRL_1_DF_32:
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len = sprintf(buf, "1120\n");
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break;
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case LIS3L02DQ_REG_CTRL_1_DF_8:
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len = sprintf(buf, "4480\n");
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break;
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}
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return len;
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}
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static ssize_t lis3l02dq_write_frequency(struct device *dev,
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struct device_attribute *attr,
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const char *buf,
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size_t len)
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{
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struct iio_dev *indio_dev = dev_get_drvdata(dev);
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long val;
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int ret;
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u8 t;
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ret = strict_strtol(buf, 10, &val);
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if (ret)
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return ret;
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mutex_lock(&indio_dev->mlock);
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ret = lis3l02dq_spi_read_reg_8(dev,
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LIS3L02DQ_REG_CTRL_1_ADDR,
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&t);
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if (ret)
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goto error_ret_mutex;
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/* Wipe the bits clean */
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t &= ~LIS3L02DQ_DEC_MASK;
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switch (val) {
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case 280:
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t |= LIS3L02DQ_REG_CTRL_1_DF_128;
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break;
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case 560:
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t |= LIS3L02DQ_REG_CTRL_1_DF_64;
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break;
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case 1120:
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t |= LIS3L02DQ_REG_CTRL_1_DF_32;
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break;
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case 4480:
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t |= LIS3L02DQ_REG_CTRL_1_DF_8;
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break;
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default:
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ret = -EINVAL;
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goto error_ret_mutex;
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}
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ret = lis3l02dq_spi_write_reg_8(dev,
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LIS3L02DQ_REG_CTRL_1_ADDR,
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&t);
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error_ret_mutex:
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mutex_unlock(&indio_dev->mlock);
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return ret ? ret : len;
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}
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static int lis3l02dq_initial_setup(struct lis3l02dq_state *st)
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{
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int ret;
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u8 val, valtest;
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st->us->mode = SPI_MODE_3;
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spi_setup(st->us);
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val = LIS3L02DQ_DEFAULT_CTRL1;
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/* Write suitable defaults to ctrl1 */
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ret = lis3l02dq_spi_write_reg_8(&st->help.indio_dev->dev,
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LIS3L02DQ_REG_CTRL_1_ADDR,
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&val);
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if (ret) {
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dev_err(&st->us->dev, "problem with setup control register 1");
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goto err_ret;
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}
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/* Repeat as sometimes doesn't work first time?*/
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ret = lis3l02dq_spi_write_reg_8(&st->help.indio_dev->dev,
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LIS3L02DQ_REG_CTRL_1_ADDR,
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&val);
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if (ret) {
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dev_err(&st->us->dev, "problem with setup control register 1");
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goto err_ret;
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}
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/* Read back to check this has worked acts as loose test of correct
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* chip */
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ret = lis3l02dq_spi_read_reg_8(&st->help.indio_dev->dev,
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LIS3L02DQ_REG_CTRL_1_ADDR,
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&valtest);
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if (ret || (valtest != val)) {
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dev_err(&st->help.indio_dev->dev, "device not playing ball");
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ret = -EINVAL;
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goto err_ret;
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}
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val = LIS3L02DQ_DEFAULT_CTRL2;
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ret = lis3l02dq_spi_write_reg_8(&st->help.indio_dev->dev,
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LIS3L02DQ_REG_CTRL_2_ADDR,
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&val);
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if (ret) {
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dev_err(&st->us->dev, "problem with setup control register 2");
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goto err_ret;
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}
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val = LIS3L02DQ_REG_WAKE_UP_CFG_LATCH_SRC;
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ret = lis3l02dq_spi_write_reg_8(&st->help.indio_dev->dev,
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LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
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&val);
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if (ret)
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dev_err(&st->us->dev, "problem with interrupt cfg register");
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err_ret:
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return ret;
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}
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|
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static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO,
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lis3l02dq_read_frequency,
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lis3l02dq_write_frequency);
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|
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static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("280 560 1120 4480");
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|
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static int lis3l02dq_thresh_handler_th(struct iio_dev *indio_dev,
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int index,
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s64 timestamp,
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int no_test)
|
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{
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struct iio_sw_ring_helper_state *h
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= iio_dev_get_devdata(indio_dev);
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struct lis3l02dq_state *st = lis3l02dq_h_to_s(h);
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/* Stash the timestamp somewhere convenient for the bh */
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st->thresh_timestamp = timestamp;
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schedule_work(&st->work_thresh);
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return 0;
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}
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|
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/* A shared handler for a number of threshold types */
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IIO_EVENT_SH(threshold, &lis3l02dq_thresh_handler_th);
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|
|
|
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#define LIS3L02DQ_INFO_MASK \
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((1 << IIO_CHAN_INFO_SCALE_SHARED) | \
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(1 << IIO_CHAN_INFO_CALIBSCALE_SEPARATE) | \
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(1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE))
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|
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#define LIS3L02DQ_EVENT_MASK \
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(IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING) | \
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IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING))
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|
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static struct iio_chan_spec lis3l02dq_channels[] = {
|
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IIO_CHAN(IIO_ACCEL, 1, 0, 0, NULL, 0, IIO_MOD_X, LIS3L02DQ_INFO_MASK,
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0, 0, IIO_ST('s', 12, 16, 0),
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LIS3L02DQ_EVENT_MASK, &iio_event_threshold),
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IIO_CHAN(IIO_ACCEL, 1, 0, 0, NULL, 0, IIO_MOD_Y, LIS3L02DQ_INFO_MASK,
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1, 1, IIO_ST('s', 12, 16, 0),
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LIS3L02DQ_EVENT_MASK, &iio_event_threshold),
|
|
IIO_CHAN(IIO_ACCEL, 1, 0, 0, NULL, 0, IIO_MOD_Z, LIS3L02DQ_INFO_MASK,
|
|
2, 2, IIO_ST('s', 12, 16, 0),
|
|
LIS3L02DQ_EVENT_MASK, &iio_event_threshold),
|
|
IIO_CHAN_SOFT_TIMESTAMP(3)
|
|
};
|
|
|
|
|
|
static ssize_t lis3l02dq_read_event_config(struct iio_dev *indio_dev,
|
|
int event_code)
|
|
{
|
|
|
|
u8 val;
|
|
int ret;
|
|
u8 mask = (1 << (IIO_EVENT_CODE_EXTRACT_MODIFIER(event_code)*2 +
|
|
(IIO_EVENT_CODE_EXTRACT_DIR(event_code) ==
|
|
IIO_EV_DIR_RISING)));
|
|
ret = lis3l02dq_spi_read_reg_8(&indio_dev->dev,
|
|
LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
|
|
&val);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
return !!(val & mask);
|
|
}
|
|
|
|
static int lis3l02dq_write_event_config(struct iio_dev *indio_dev,
|
|
int event_code,
|
|
struct iio_event_handler_list *list_el,
|
|
int state)
|
|
{
|
|
int ret = 0;
|
|
u8 val, control;
|
|
u8 currentlyset;
|
|
bool changed = false;
|
|
u8 mask = (1 << (IIO_EVENT_CODE_EXTRACT_MODIFIER(event_code)*2 +
|
|
(IIO_EVENT_CODE_EXTRACT_DIR(event_code) ==
|
|
IIO_EV_DIR_RISING)));
|
|
|
|
mutex_lock(&indio_dev->mlock);
|
|
/* read current control */
|
|
ret = lis3l02dq_spi_read_reg_8(&indio_dev->dev,
|
|
LIS3L02DQ_REG_CTRL_2_ADDR,
|
|
&control);
|
|
if (ret)
|
|
goto error_ret;
|
|
ret = lis3l02dq_spi_read_reg_8(&indio_dev->dev,
|
|
LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
|
|
&val);
|
|
if (ret < 0)
|
|
goto error_ret;
|
|
currentlyset = val & mask;
|
|
|
|
if (!currentlyset && state) {
|
|
changed = true;
|
|
val |= mask;
|
|
iio_add_event_to_list(list_el,
|
|
&indio_dev->interrupts[0]->ev_list);
|
|
|
|
} else if (currentlyset && !state) {
|
|
changed = true;
|
|
val &= ~mask;
|
|
iio_remove_event_from_list(list_el,
|
|
&indio_dev->interrupts[0]->ev_list);
|
|
}
|
|
if (changed) {
|
|
ret = lis3l02dq_spi_write_reg_8(&indio_dev->dev,
|
|
LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
|
|
&val);
|
|
if (ret)
|
|
goto error_ret;
|
|
control = list_el->refcount ?
|
|
(control | LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT) :
|
|
(control & ~LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT);
|
|
ret = lis3l02dq_spi_write_reg_8(&indio_dev->dev,
|
|
LIS3L02DQ_REG_CTRL_2_ADDR,
|
|
&control);
|
|
}
|
|
|
|
error_ret:
|
|
mutex_unlock(&indio_dev->mlock);
|
|
return ret;
|
|
}
|
|
|
|
/* Unforunately it appears the interrupt won't clear unless you read from the
|
|
* src register.
|
|
*/
|
|
static void lis3l02dq_thresh_handler_bh_no_check(struct work_struct *work_s)
|
|
{
|
|
struct lis3l02dq_state *st
|
|
= container_of(work_s,
|
|
struct lis3l02dq_state, work_thresh);
|
|
u8 t;
|
|
|
|
lis3l02dq_spi_read_reg_8(&st->help.indio_dev->dev,
|
|
LIS3L02DQ_REG_WAKE_UP_SRC_ADDR,
|
|
&t);
|
|
|
|
if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Z_HIGH)
|
|
iio_push_event(st->help.indio_dev, 0,
|
|
IIO_MOD_EVENT_CODE(IIO_EV_CLASS_ACCEL,
|
|
0,
|
|
IIO_EV_MOD_Z,
|
|
IIO_EV_TYPE_THRESH,
|
|
IIO_EV_DIR_RISING),
|
|
st->thresh_timestamp);
|
|
|
|
if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Z_LOW)
|
|
iio_push_event(st->help.indio_dev, 0,
|
|
IIO_MOD_EVENT_CODE(IIO_EV_CLASS_ACCEL,
|
|
0,
|
|
IIO_EV_MOD_Z,
|
|
IIO_EV_TYPE_THRESH,
|
|
IIO_EV_DIR_FALLING),
|
|
st->thresh_timestamp);
|
|
|
|
if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Y_HIGH)
|
|
iio_push_event(st->help.indio_dev, 0,
|
|
IIO_MOD_EVENT_CODE(IIO_EV_CLASS_ACCEL,
|
|
0,
|
|
IIO_EV_MOD_Y,
|
|
IIO_EV_TYPE_THRESH,
|
|
IIO_EV_DIR_RISING),
|
|
st->thresh_timestamp);
|
|
|
|
if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Y_LOW)
|
|
iio_push_event(st->help.indio_dev, 0,
|
|
IIO_MOD_EVENT_CODE(IIO_EV_CLASS_ACCEL,
|
|
0,
|
|
IIO_EV_MOD_Y,
|
|
IIO_EV_TYPE_THRESH,
|
|
IIO_EV_DIR_FALLING),
|
|
st->thresh_timestamp);
|
|
|
|
if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_X_HIGH)
|
|
iio_push_event(st->help.indio_dev, 0,
|
|
IIO_MOD_EVENT_CODE(IIO_EV_CLASS_ACCEL,
|
|
0,
|
|
IIO_EV_MOD_X,
|
|
IIO_EV_TYPE_THRESH,
|
|
IIO_EV_DIR_RISING),
|
|
st->thresh_timestamp);
|
|
|
|
if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_X_LOW)
|
|
iio_push_event(st->help.indio_dev, 0,
|
|
IIO_MOD_EVENT_CODE(IIO_EV_CLASS_ACCEL,
|
|
0,
|
|
IIO_EV_MOD_X,
|
|
IIO_EV_TYPE_THRESH,
|
|
IIO_EV_DIR_FALLING),
|
|
st->thresh_timestamp);
|
|
/* reenable the irq */
|
|
enable_irq(st->us->irq);
|
|
/* Ack and allow for new interrupts */
|
|
lis3l02dq_spi_read_reg_8(&st->help.indio_dev->dev,
|
|
LIS3L02DQ_REG_WAKE_UP_ACK_ADDR,
|
|
&t);
|
|
|
|
return;
|
|
}
|
|
|
|
static IIO_CONST_ATTR_NAME("lis3l02dq");
|
|
|
|
static struct attribute *lis3l02dq_attributes[] = {
|
|
&iio_dev_attr_sampling_frequency.dev_attr.attr,
|
|
&iio_const_attr_sampling_frequency_available.dev_attr.attr,
|
|
&iio_const_attr_name.dev_attr.attr,
|
|
NULL
|
|
};
|
|
|
|
static const struct attribute_group lis3l02dq_attribute_group = {
|
|
.attrs = lis3l02dq_attributes,
|
|
};
|
|
|
|
static int __devinit lis3l02dq_probe(struct spi_device *spi)
|
|
{
|
|
int ret, regdone = 0;
|
|
struct lis3l02dq_state *st = kzalloc(sizeof *st, GFP_KERNEL);
|
|
if (!st) {
|
|
ret = -ENOMEM;
|
|
goto error_ret;
|
|
}
|
|
INIT_WORK(&st->work_thresh, lis3l02dq_thresh_handler_bh_no_check);
|
|
/* this is only used tor removal purposes */
|
|
spi_set_drvdata(spi, st);
|
|
|
|
/* Allocate the comms buffers */
|
|
st->rx = kzalloc(sizeof(*st->rx)*LIS3L02DQ_MAX_RX, GFP_KERNEL);
|
|
if (st->rx == NULL) {
|
|
ret = -ENOMEM;
|
|
goto error_free_st;
|
|
}
|
|
st->tx = kzalloc(sizeof(*st->tx)*LIS3L02DQ_MAX_TX, GFP_KERNEL);
|
|
if (st->tx == NULL) {
|
|
ret = -ENOMEM;
|
|
goto error_free_rx;
|
|
}
|
|
st->us = spi;
|
|
mutex_init(&st->buf_lock);
|
|
/* setup the industrialio driver allocated elements */
|
|
st->help.indio_dev = iio_allocate_device(0);
|
|
if (st->help.indio_dev == NULL) {
|
|
ret = -ENOMEM;
|
|
goto error_free_tx;
|
|
}
|
|
|
|
st->help.indio_dev->dev.parent = &spi->dev;
|
|
st->help.indio_dev->num_interrupt_lines = 1;
|
|
st->help.indio_dev->channels = lis3l02dq_channels;
|
|
st->help.indio_dev->num_channels = ARRAY_SIZE(lis3l02dq_channels);
|
|
st->help.indio_dev->read_raw = &lis3l02dq_read_raw;
|
|
st->help.indio_dev->read_event_value = &lis3l02dq_read_thresh;
|
|
st->help.indio_dev->write_event_value = &lis3l02dq_write_thresh;
|
|
st->help.indio_dev->write_event_config = &lis3l02dq_write_event_config;
|
|
st->help.indio_dev->read_event_config = &lis3l02dq_read_event_config;
|
|
st->help.indio_dev->attrs = &lis3l02dq_attribute_group;
|
|
st->help.indio_dev->dev_data = (void *)(&st->help);
|
|
st->help.indio_dev->driver_module = THIS_MODULE;
|
|
st->help.indio_dev->modes = INDIO_DIRECT_MODE;
|
|
|
|
ret = lis3l02dq_configure_ring(st->help.indio_dev);
|
|
if (ret)
|
|
goto error_free_dev;
|
|
|
|
ret = iio_device_register(st->help.indio_dev);
|
|
if (ret)
|
|
goto error_unreg_ring_funcs;
|
|
regdone = 1;
|
|
|
|
ret = iio_ring_buffer_register_ex(st->help.indio_dev->ring, 0,
|
|
lis3l02dq_channels,
|
|
ARRAY_SIZE(lis3l02dq_channels));
|
|
if (ret) {
|
|
printk(KERN_ERR "failed to initialize the ring\n");
|
|
goto error_unreg_ring_funcs;
|
|
}
|
|
|
|
if (spi->irq && gpio_is_valid(irq_to_gpio(spi->irq)) > 0) {
|
|
st->inter = 0;
|
|
ret = iio_register_interrupt_line(spi->irq,
|
|
st->help.indio_dev,
|
|
0,
|
|
IRQF_TRIGGER_RISING,
|
|
"lis3l02dq");
|
|
if (ret)
|
|
goto error_uninitialize_ring;
|
|
|
|
ret = lis3l02dq_probe_trigger(st->help.indio_dev);
|
|
if (ret)
|
|
goto error_unregister_line;
|
|
}
|
|
|
|
/* Get the device into a sane initial state */
|
|
ret = lis3l02dq_initial_setup(st);
|
|
if (ret)
|
|
goto error_remove_trigger;
|
|
return 0;
|
|
|
|
error_remove_trigger:
|
|
if (st->help.indio_dev->modes & INDIO_RING_TRIGGERED)
|
|
lis3l02dq_remove_trigger(st->help.indio_dev);
|
|
error_unregister_line:
|
|
if (st->help.indio_dev->modes & INDIO_RING_TRIGGERED)
|
|
iio_unregister_interrupt_line(st->help.indio_dev, 0);
|
|
error_uninitialize_ring:
|
|
iio_ring_buffer_unregister(st->help.indio_dev->ring);
|
|
error_unreg_ring_funcs:
|
|
lis3l02dq_unconfigure_ring(st->help.indio_dev);
|
|
error_free_dev:
|
|
if (regdone)
|
|
iio_device_unregister(st->help.indio_dev);
|
|
else
|
|
iio_free_device(st->help.indio_dev);
|
|
error_free_tx:
|
|
kfree(st->tx);
|
|
error_free_rx:
|
|
kfree(st->rx);
|
|
error_free_st:
|
|
kfree(st);
|
|
error_ret:
|
|
return ret;
|
|
}
|
|
|
|
/* Power down the device */
|
|
static int lis3l02dq_stop_device(struct iio_dev *indio_dev)
|
|
{
|
|
int ret;
|
|
struct iio_sw_ring_helper_state *h
|
|
= iio_dev_get_devdata(indio_dev);
|
|
struct lis3l02dq_state *st = lis3l02dq_h_to_s(h);
|
|
u8 val = 0;
|
|
|
|
mutex_lock(&indio_dev->mlock);
|
|
ret = lis3l02dq_spi_write_reg_8(&indio_dev->dev,
|
|
LIS3L02DQ_REG_CTRL_1_ADDR,
|
|
&val);
|
|
if (ret) {
|
|
dev_err(&st->us->dev, "problem with turning device off: ctrl1");
|
|
goto err_ret;
|
|
}
|
|
|
|
ret = lis3l02dq_spi_write_reg_8(&indio_dev->dev,
|
|
LIS3L02DQ_REG_CTRL_2_ADDR,
|
|
&val);
|
|
if (ret)
|
|
dev_err(&st->us->dev, "problem with turning device off: ctrl2");
|
|
err_ret:
|
|
mutex_unlock(&indio_dev->mlock);
|
|
return ret;
|
|
}
|
|
|
|
/* fixme, confirm ordering in this function */
|
|
static int lis3l02dq_remove(struct spi_device *spi)
|
|
{
|
|
int ret;
|
|
struct lis3l02dq_state *st = spi_get_drvdata(spi);
|
|
struct iio_dev *indio_dev = st->help.indio_dev;
|
|
|
|
ret = lis3l02dq_stop_device(indio_dev);
|
|
if (ret)
|
|
goto err_ret;
|
|
|
|
flush_scheduled_work();
|
|
|
|
lis3l02dq_remove_trigger(indio_dev);
|
|
if (spi->irq && gpio_is_valid(irq_to_gpio(spi->irq)) > 0)
|
|
iio_unregister_interrupt_line(indio_dev, 0);
|
|
|
|
iio_ring_buffer_unregister(indio_dev->ring);
|
|
lis3l02dq_unconfigure_ring(indio_dev);
|
|
iio_device_unregister(indio_dev);
|
|
kfree(st->tx);
|
|
kfree(st->rx);
|
|
kfree(st);
|
|
|
|
return 0;
|
|
|
|
err_ret:
|
|
return ret;
|
|
}
|
|
|
|
static struct spi_driver lis3l02dq_driver = {
|
|
.driver = {
|
|
.name = "lis3l02dq",
|
|
.owner = THIS_MODULE,
|
|
},
|
|
.probe = lis3l02dq_probe,
|
|
.remove = __devexit_p(lis3l02dq_remove),
|
|
};
|
|
|
|
static __init int lis3l02dq_init(void)
|
|
{
|
|
return spi_register_driver(&lis3l02dq_driver);
|
|
}
|
|
module_init(lis3l02dq_init);
|
|
|
|
static __exit void lis3l02dq_exit(void)
|
|
{
|
|
spi_unregister_driver(&lis3l02dq_driver);
|
|
}
|
|
module_exit(lis3l02dq_exit);
|
|
|
|
MODULE_AUTHOR("Jonathan Cameron <jic23@cam.ac.uk>");
|
|
MODULE_DESCRIPTION("ST LIS3L02DQ Accelerometer SPI driver");
|
|
MODULE_LICENSE("GPL v2");
|