![Atsushi Nemoto](/assets/img/avatar_default.png)
This is a big irq cleanup patch. * Use set_irq_chip() to register irq_chip. * Initialize .mask, .unmask, .mask_ack field. Functions for these method are already exist in most case. * Do not initialize .startup, .shutdown, .enable, .disable fields if default routines provided by irq_chip_set_defaults() were suitable. * Remove redundant irq_desc initializations. * Remove unnecessary local_irq_save/local_irq_restore, spin_lock. With this cleanup, it would be easy to switch to slightly lightwait irq flow handlers (handle_level_irq(), etc.) instead of __do_IRQ(). Though whole this patch is quite large, changes in each irq_chip are not quite simple. Please review and test on your platform. Thanks. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
459 lines
12 KiB
C
459 lines
12 KiB
C
/*
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* Copyright 2001 MontaVista Software Inc.
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* Author: MontaVista Software, Inc.
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* ahennessy@mvista.com
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2000-2001 Toshiba Corporation
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/irq.h>
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#include <linux/kernel_stat.h>
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/timex.h>
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#include <linux/slab.h>
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#include <linux/random.h>
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#include <linux/smp.h>
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#include <linux/smp_lock.h>
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#include <linux/bitops.h>
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#include <asm/irq_regs.h>
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#include <asm/io.h>
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#include <asm/mipsregs.h>
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#include <asm/system.h>
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#include <asm/ptrace.h>
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#include <asm/processor.h>
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#include <asm/jmr3927/irq.h>
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#include <asm/debug.h>
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#include <asm/jmr3927/jmr3927.h>
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#if JMR3927_IRQ_END > NR_IRQS
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#error JMR3927_IRQ_END > NR_IRQS
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#endif
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struct tb_irq_space* tb_irq_spaces;
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static int jmr3927_irq_base = -1;
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#ifdef CONFIG_PCI
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static int jmr3927_gen_iack(void)
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{
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/* generate ACK cycle */
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#ifdef __BIG_ENDIAN
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return (tx3927_pcicptr->iiadp >> 24) & 0xff;
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#else
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return tx3927_pcicptr->iiadp & 0xff;
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#endif
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}
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#endif
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#define irc_dlevel 0
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#define irc_elevel 1
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static unsigned char irc_level[TX3927_NUM_IR] = {
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5, 5, 5, 5, 5, 5, /* INT[5:0] */
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7, 7, /* SIO */
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5, 5, 5, 0, 0, /* DMA, PIO, PCI */
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6, 6, 6 /* TMR */
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};
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static void jmr3927_irq_disable(unsigned int irq_nr);
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static void jmr3927_irq_enable(unsigned int irq_nr);
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static void jmr3927_irq_ack(unsigned int irq)
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{
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if (irq == JMR3927_IRQ_IRC_TMR0)
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jmr3927_tmrptr->tisr = 0; /* ack interrupt */
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jmr3927_irq_disable(irq);
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}
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static void jmr3927_irq_end(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
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jmr3927_irq_enable(irq);
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}
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static void jmr3927_irq_disable(unsigned int irq_nr)
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{
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struct tb_irq_space* sp;
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for (sp = tb_irq_spaces; sp; sp = sp->next) {
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if (sp->start_irqno <= irq_nr &&
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irq_nr < sp->start_irqno + sp->nr_irqs) {
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if (sp->mask_func)
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sp->mask_func(irq_nr - sp->start_irqno,
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sp->space_id);
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break;
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}
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}
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}
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static void jmr3927_irq_enable(unsigned int irq_nr)
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{
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struct tb_irq_space* sp;
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for (sp = tb_irq_spaces; sp; sp = sp->next) {
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if (sp->start_irqno <= irq_nr &&
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irq_nr < sp->start_irqno + sp->nr_irqs) {
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if (sp->unmask_func)
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sp->unmask_func(irq_nr - sp->start_irqno,
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sp->space_id);
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break;
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}
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}
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}
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/*
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* CP0_STATUS is a thread's resource (saved/restored on context switch).
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* So disable_irq/enable_irq MUST handle IOC/ISAC/IRC registers.
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*/
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static void mask_irq_isac(int irq_nr, int space_id)
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{
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/* 0: mask */
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unsigned char imask =
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jmr3927_isac_reg_in(JMR3927_ISAC_INTM_ADDR);
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unsigned int bit = 1 << irq_nr;
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jmr3927_isac_reg_out(imask & ~bit, JMR3927_ISAC_INTM_ADDR);
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/* flush write buffer */
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(void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
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}
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static void unmask_irq_isac(int irq_nr, int space_id)
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{
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/* 0: mask */
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unsigned char imask = jmr3927_isac_reg_in(JMR3927_ISAC_INTM_ADDR);
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unsigned int bit = 1 << irq_nr;
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jmr3927_isac_reg_out(imask | bit, JMR3927_ISAC_INTM_ADDR);
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/* flush write buffer */
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(void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
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}
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static void mask_irq_ioc(int irq_nr, int space_id)
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{
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/* 0: mask */
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unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR);
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unsigned int bit = 1 << irq_nr;
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jmr3927_ioc_reg_out(imask & ~bit, JMR3927_IOC_INTM_ADDR);
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/* flush write buffer */
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(void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
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}
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static void unmask_irq_ioc(int irq_nr, int space_id)
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{
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/* 0: mask */
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unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR);
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unsigned int bit = 1 << irq_nr;
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jmr3927_ioc_reg_out(imask | bit, JMR3927_IOC_INTM_ADDR);
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/* flush write buffer */
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(void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
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}
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static void mask_irq_irc(int irq_nr, int space_id)
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{
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volatile unsigned long *ilrp = &tx3927_ircptr->ilr[irq_nr / 2];
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if (irq_nr & 1)
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*ilrp = (*ilrp & 0x00ff) | (irc_dlevel << 8);
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else
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*ilrp = (*ilrp & 0xff00) | irc_dlevel;
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/* update IRCSR */
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tx3927_ircptr->imr = 0;
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tx3927_ircptr->imr = irc_elevel;
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/* flush write buffer */
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(void)tx3927_ircptr->ssr;
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}
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static void unmask_irq_irc(int irq_nr, int space_id)
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{
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volatile unsigned long *ilrp = &tx3927_ircptr->ilr[irq_nr / 2];
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if (irq_nr & 1)
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*ilrp = (*ilrp & 0x00ff) | (irc_level[irq_nr] << 8);
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else
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*ilrp = (*ilrp & 0xff00) | irc_level[irq_nr];
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/* update IRCSR */
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tx3927_ircptr->imr = 0;
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tx3927_ircptr->imr = irc_elevel;
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}
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struct tb_irq_space jmr3927_isac_irqspace = {
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.next = NULL,
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.start_irqno = JMR3927_IRQ_ISAC,
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nr_irqs : JMR3927_NR_IRQ_ISAC,
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.mask_func = mask_irq_isac,
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.unmask_func = unmask_irq_isac,
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.name = "ISAC",
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.space_id = 0,
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can_share : 0
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};
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struct tb_irq_space jmr3927_ioc_irqspace = {
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.next = NULL,
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.start_irqno = JMR3927_IRQ_IOC,
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nr_irqs : JMR3927_NR_IRQ_IOC,
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.mask_func = mask_irq_ioc,
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.unmask_func = unmask_irq_ioc,
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.name = "IOC",
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.space_id = 0,
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can_share : 1
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};
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struct tb_irq_space jmr3927_irc_irqspace = {
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.next = NULL,
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.start_irqno = JMR3927_IRQ_IRC,
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.nr_irqs = JMR3927_NR_IRQ_IRC,
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.mask_func = mask_irq_irc,
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.unmask_func = unmask_irq_irc,
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.name = "on-chip",
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.space_id = 0,
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.can_share = 0
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};
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#ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND
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static int tx_branch_likely_bug_count = 0;
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static int have_tx_branch_likely_bug = 0;
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static void tx_branch_likely_bug_fixup(void)
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{
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struct pt_regs *regs = get_irq_regs();
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/* TX39/49-BUG: Under this condition, the insn in delay slot
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of the branch likely insn is executed (not nullified) even
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the branch condition is false. */
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if (!have_tx_branch_likely_bug)
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return;
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if ((regs->cp0_epc & 0xfff) == 0xffc &&
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KSEGX(regs->cp0_epc) != KSEG0 &&
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KSEGX(regs->cp0_epc) != KSEG1) {
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unsigned int insn = *(unsigned int*)(regs->cp0_epc - 4);
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/* beql,bnel,blezl,bgtzl */
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/* bltzl,bgezl,blezall,bgezall */
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/* bczfl, bcztl */
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if ((insn & 0xf0000000) == 0x50000000 ||
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(insn & 0xfc0e0000) == 0x04020000 ||
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(insn & 0xf3fe0000) == 0x41020000) {
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regs->cp0_epc -= 4;
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tx_branch_likely_bug_count++;
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printk(KERN_INFO
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"fix branch-likery bug in %s (insn %08x)\n",
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current->comm, insn);
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}
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}
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}
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#endif
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static void jmr3927_spurious(void)
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{
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struct pt_regs * regs = get_irq_regs();
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#ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND
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tx_branch_likely_bug_fixup();
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#endif
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printk(KERN_WARNING "spurious interrupt (cause 0x%lx, pc 0x%lx, ra 0x%lx).\n",
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regs->cp0_cause, regs->cp0_epc, regs->regs[31]);
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}
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asmlinkage void plat_irq_dispatch(void)
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{
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struct pt_regs * regs = get_irq_regs();
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int irq;
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#ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND
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tx_branch_likely_bug_fixup();
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#endif
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if ((regs->cp0_cause & CAUSEF_IP7) == 0) {
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#if 0
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jmr3927_spurious();
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#endif
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return;
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}
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irq = (regs->cp0_cause >> CAUSEB_IP2) & 0x0f;
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do_IRQ(irq + JMR3927_IRQ_IRC);
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}
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static irqreturn_t jmr3927_ioc_interrupt(int irq, void *dev_id)
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{
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unsigned char istat = jmr3927_ioc_reg_in(JMR3927_IOC_INTS2_ADDR);
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int i;
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for (i = 0; i < JMR3927_NR_IRQ_IOC; i++) {
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if (istat & (1 << i)) {
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irq = JMR3927_IRQ_IOC + i;
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do_IRQ(irq);
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}
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}
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return IRQ_HANDLED;
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}
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static struct irqaction ioc_action = {
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jmr3927_ioc_interrupt, 0, CPU_MASK_NONE, "IOC", NULL, NULL,
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};
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static irqreturn_t jmr3927_isac_interrupt(int irq, void *dev_id)
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{
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unsigned char istat = jmr3927_isac_reg_in(JMR3927_ISAC_INTS2_ADDR);
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int i;
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for (i = 0; i < JMR3927_NR_IRQ_ISAC; i++) {
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if (istat & (1 << i)) {
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irq = JMR3927_IRQ_ISAC + i;
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do_IRQ(irq);
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}
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}
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return IRQ_HANDLED;
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}
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static struct irqaction isac_action = {
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jmr3927_isac_interrupt, 0, CPU_MASK_NONE, "ISAC", NULL, NULL,
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};
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static irqreturn_t jmr3927_isaerr_interrupt(int irq, void *dev_id)
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{
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printk(KERN_WARNING "ISA error interrupt (irq 0x%x).\n", irq);
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return IRQ_HANDLED;
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}
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static struct irqaction isaerr_action = {
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jmr3927_isaerr_interrupt, 0, CPU_MASK_NONE, "ISA error", NULL, NULL,
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};
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static irqreturn_t jmr3927_pcierr_interrupt(int irq, void *dev_id)
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{
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printk(KERN_WARNING "PCI error interrupt (irq 0x%x).\n", irq);
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printk(KERN_WARNING "pcistat:%02x, lbstat:%04lx\n",
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tx3927_pcicptr->pcistat, tx3927_pcicptr->lbstat);
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return IRQ_HANDLED;
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}
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static struct irqaction pcierr_action = {
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jmr3927_pcierr_interrupt, 0, CPU_MASK_NONE, "PCI error", NULL, NULL,
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};
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int jmr3927_ether1_irq = 0;
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void jmr3927_irq_init(u32 irq_base);
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void __init arch_init_irq(void)
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{
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/* look for io board's presence */
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int have_isac = jmr3927_have_isac();
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/* Now, interrupt control disabled, */
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/* all IRC interrupts are masked, */
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/* all IRC interrupt mode are Low Active. */
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if (have_isac) {
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/* ETHER1 (NE2000 compatible 10M-Ether) parameter setup */
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/* temporary enable interrupt control */
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tx3927_ircptr->cer = 1;
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/* ETHER1 Int. Is High-Active. */
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if (tx3927_ircptr->ssr & (1 << 0))
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jmr3927_ether1_irq = JMR3927_IRQ_IRC_INT0;
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#if 0 /* INT3 may be asserted by ether0 (even after reboot...) */
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else if (tx3927_ircptr->ssr & (1 << 3))
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jmr3927_ether1_irq = JMR3927_IRQ_IRC_INT3;
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#endif
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/* disable interrupt control */
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tx3927_ircptr->cer = 0;
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/* Ether1: High Active */
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if (jmr3927_ether1_irq) {
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int ether1_irc = jmr3927_ether1_irq - JMR3927_IRQ_IRC;
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tx3927_ircptr->cr[ether1_irc / 8] |=
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TX3927_IRCR_HIGH << ((ether1_irc % 8) * 2);
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}
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}
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/* mask all IOC interrupts */
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jmr3927_ioc_reg_out(0, JMR3927_IOC_INTM_ADDR);
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/* setup IOC interrupt mode (SOFT:High Active, Others:Low Active) */
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jmr3927_ioc_reg_out(JMR3927_IOC_INTF_SOFT, JMR3927_IOC_INTP_ADDR);
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if (have_isac) {
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/* mask all ISAC interrupts */
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jmr3927_isac_reg_out(0, JMR3927_ISAC_INTM_ADDR);
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/* setup ISAC interrupt mode (ISAIRQ3,ISAIRQ5:Low Active ???) */
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jmr3927_isac_reg_out(JMR3927_ISAC_INTF_IRQ3|JMR3927_ISAC_INTF_IRQ5, JMR3927_ISAC_INTP_ADDR);
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}
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/* clear PCI Soft interrupts */
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jmr3927_ioc_reg_out(0, JMR3927_IOC_INTS1_ADDR);
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/* clear PCI Reset interrupts */
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jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
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/* enable interrupt control */
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tx3927_ircptr->cer = TX3927_IRCER_ICE;
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tx3927_ircptr->imr = irc_elevel;
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jmr3927_irq_init(NR_ISA_IRQS);
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/* setup irq space */
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add_tb_irq_space(&jmr3927_isac_irqspace);
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add_tb_irq_space(&jmr3927_ioc_irqspace);
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add_tb_irq_space(&jmr3927_irc_irqspace);
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/* setup IOC interrupt 1 (PCI, MODEM) */
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setup_irq(JMR3927_IRQ_IOCINT, &ioc_action);
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if (have_isac) {
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setup_irq(JMR3927_IRQ_ISACINT, &isac_action);
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setup_irq(JMR3927_IRQ_ISAC_ISAER, &isaerr_action);
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}
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#ifdef CONFIG_PCI
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setup_irq(JMR3927_IRQ_IRC_PCI, &pcierr_action);
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#endif
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/* enable all CPU interrupt bits. */
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set_c0_status(ST0_IM); /* IE bit is still 0. */
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}
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static struct irq_chip jmr3927_irq_controller = {
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.typename = "jmr3927_irq",
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.ack = jmr3927_irq_ack,
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.mask = jmr3927_irq_disable,
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.mask_ack = jmr3927_irq_ack,
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.unmask = jmr3927_irq_enable,
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.end = jmr3927_irq_end,
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};
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void jmr3927_irq_init(u32 irq_base)
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{
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u32 i;
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|
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for (i= irq_base; i< irq_base + JMR3927_NR_IRQ_IRC + JMR3927_NR_IRQ_IOC; i++)
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set_irq_chip(i, &jmr3927_irq_controller);
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jmr3927_irq_base = irq_base;
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}
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