![Linus Torvalds](/assets/img/avatar_default.png)
This reverts commit aeeddc1435
, which was
half-baked and broken. It just resulted in compile errors, since
cpufreq_register_driver() still changes the 'driver_data' by setting
bits in the flags field. So claiming it is 'const' _really_ doesn't
work.
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
335 lines
7.8 KiB
C
335 lines
7.8 KiB
C
/*
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* Based on documentation provided by Dave Jones. Thanks!
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*
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* Licensed under the terms of the GNU GPL License version 2.
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*
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* BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/cpufreq.h>
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#include <linux/ioport.h>
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#include <linux/slab.h>
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#include <asm/msr.h>
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#include <asm/tsc.h>
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#include <asm/timex.h>
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#include <asm/io.h>
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#include <asm/delay.h>
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#define EPS_BRAND_C7M 0
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#define EPS_BRAND_C7 1
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#define EPS_BRAND_EDEN 2
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#define EPS_BRAND_C3 3
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struct eps_cpu_data {
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u32 fsb;
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struct cpufreq_frequency_table freq_table[];
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};
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static struct eps_cpu_data *eps_cpu[NR_CPUS];
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static unsigned int eps_get(unsigned int cpu)
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{
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struct eps_cpu_data *centaur;
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u32 lo, hi;
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if (cpu)
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return 0;
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centaur = eps_cpu[cpu];
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if (centaur == NULL)
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return 0;
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/* Return current frequency */
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rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
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return centaur->fsb * ((lo >> 8) & 0xff);
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}
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static int eps_set_state(struct eps_cpu_data *centaur,
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unsigned int cpu,
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u32 dest_state)
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{
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struct cpufreq_freqs freqs;
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u32 lo, hi;
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int err = 0;
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int i;
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freqs.old = eps_get(cpu);
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freqs.new = centaur->fsb * ((dest_state >> 8) & 0xff);
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freqs.cpu = cpu;
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cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
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/* Wait while CPU is busy */
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rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
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i = 0;
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while (lo & ((1 << 16) | (1 << 17))) {
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udelay(16);
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rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
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i++;
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if (unlikely(i > 64)) {
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err = -ENODEV;
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goto postchange;
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}
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}
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/* Set new multiplier and voltage */
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wrmsr(MSR_IA32_PERF_CTL, dest_state & 0xffff, 0);
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/* Wait until transition end */
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i = 0;
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do {
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udelay(16);
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rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
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i++;
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if (unlikely(i > 64)) {
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err = -ENODEV;
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goto postchange;
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}
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} while (lo & ((1 << 16) | (1 << 17)));
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/* Return current frequency */
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postchange:
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rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
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freqs.new = centaur->fsb * ((lo >> 8) & 0xff);
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cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
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return err;
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}
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static int eps_target(struct cpufreq_policy *policy,
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unsigned int target_freq,
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unsigned int relation)
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{
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struct eps_cpu_data *centaur;
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unsigned int newstate = 0;
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unsigned int cpu = policy->cpu;
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unsigned int dest_state;
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int ret;
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if (unlikely(eps_cpu[cpu] == NULL))
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return -ENODEV;
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centaur = eps_cpu[cpu];
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if (unlikely(cpufreq_frequency_table_target(policy,
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&eps_cpu[cpu]->freq_table[0],
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target_freq,
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relation,
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&newstate))) {
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return -EINVAL;
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}
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/* Make frequency transition */
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dest_state = centaur->freq_table[newstate].index & 0xffff;
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ret = eps_set_state(centaur, cpu, dest_state);
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if (ret)
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printk(KERN_ERR "eps: Timeout!\n");
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return ret;
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}
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static int eps_verify(struct cpufreq_policy *policy)
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{
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return cpufreq_frequency_table_verify(policy,
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&eps_cpu[policy->cpu]->freq_table[0]);
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}
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static int eps_cpu_init(struct cpufreq_policy *policy)
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{
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unsigned int i;
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u32 lo, hi;
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u64 val;
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u8 current_multiplier, current_voltage;
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u8 max_multiplier, max_voltage;
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u8 min_multiplier, min_voltage;
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u8 brand;
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u32 fsb;
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struct eps_cpu_data *centaur;
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struct cpufreq_frequency_table *f_table;
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int k, step, voltage;
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int ret;
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int states;
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if (policy->cpu != 0)
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return -ENODEV;
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/* Check brand */
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printk("eps: Detected VIA ");
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rdmsr(0x1153, lo, hi);
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brand = (((lo >> 2) ^ lo) >> 18) & 3;
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switch(brand) {
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case EPS_BRAND_C7M:
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printk("C7-M\n");
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break;
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case EPS_BRAND_C7:
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printk("C7\n");
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break;
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case EPS_BRAND_EDEN:
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printk("Eden\n");
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break;
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case EPS_BRAND_C3:
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printk("C3\n");
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return -ENODEV;
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break;
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}
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/* Enable Enhanced PowerSaver */
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rdmsrl(MSR_IA32_MISC_ENABLE, val);
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if (!(val & 1 << 16)) {
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val |= 1 << 16;
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wrmsrl(MSR_IA32_MISC_ENABLE, val);
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/* Can be locked at 0 */
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rdmsrl(MSR_IA32_MISC_ENABLE, val);
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if (!(val & 1 << 16)) {
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printk("eps: Can't enable Enhanced PowerSaver\n");
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return -ENODEV;
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}
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}
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/* Print voltage and multiplier */
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rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
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current_voltage = lo & 0xff;
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printk("eps: Current voltage = %dmV\n", current_voltage * 16 + 700);
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current_multiplier = (lo >> 8) & 0xff;
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printk("eps: Current multiplier = %d\n", current_multiplier);
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/* Print limits */
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max_voltage = hi & 0xff;
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printk("eps: Highest voltage = %dmV\n", max_voltage * 16 + 700);
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max_multiplier = (hi >> 8) & 0xff;
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printk("eps: Highest multiplier = %d\n", max_multiplier);
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min_voltage = (hi >> 16) & 0xff;
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printk("eps: Lowest voltage = %dmV\n", min_voltage * 16 + 700);
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min_multiplier = (hi >> 24) & 0xff;
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printk("eps: Lowest multiplier = %d\n", min_multiplier);
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/* Sanity checks */
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if (current_multiplier == 0 || max_multiplier == 0
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|| min_multiplier == 0)
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return -EINVAL;
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if (current_multiplier > max_multiplier
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|| max_multiplier <= min_multiplier)
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return -EINVAL;
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if (current_voltage > 0x1c || max_voltage > 0x1c)
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return -EINVAL;
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if (max_voltage < min_voltage)
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return -EINVAL;
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/* Calc FSB speed */
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fsb = cpu_khz / current_multiplier;
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/* Calc number of p-states supported */
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if (brand == EPS_BRAND_C7M)
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states = max_multiplier - min_multiplier + 1;
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else
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states = 2;
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/* Allocate private data and frequency table for current cpu */
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centaur = kzalloc(sizeof(struct eps_cpu_data)
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+ (states + 1) * sizeof(struct cpufreq_frequency_table),
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GFP_KERNEL);
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if (!centaur)
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return -ENOMEM;
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eps_cpu[0] = centaur;
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/* Copy basic values */
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centaur->fsb = fsb;
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/* Fill frequency and MSR value table */
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f_table = ¢aur->freq_table[0];
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if (brand != EPS_BRAND_C7M) {
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f_table[0].frequency = fsb * min_multiplier;
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f_table[0].index = (min_multiplier << 8) | min_voltage;
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f_table[1].frequency = fsb * max_multiplier;
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f_table[1].index = (max_multiplier << 8) | max_voltage;
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f_table[2].frequency = CPUFREQ_TABLE_END;
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} else {
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k = 0;
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step = ((max_voltage - min_voltage) * 256)
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/ (max_multiplier - min_multiplier);
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for (i = min_multiplier; i <= max_multiplier; i++) {
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voltage = (k * step) / 256 + min_voltage;
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f_table[k].frequency = fsb * i;
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f_table[k].index = (i << 8) | voltage;
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k++;
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}
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f_table[k].frequency = CPUFREQ_TABLE_END;
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}
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policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
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policy->cpuinfo.transition_latency = 140000; /* 844mV -> 700mV in ns */
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policy->cur = fsb * current_multiplier;
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ret = cpufreq_frequency_table_cpuinfo(policy, ¢aur->freq_table[0]);
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if (ret) {
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kfree(centaur);
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return ret;
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}
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cpufreq_frequency_table_get_attr(¢aur->freq_table[0], policy->cpu);
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return 0;
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}
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static int eps_cpu_exit(struct cpufreq_policy *policy)
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{
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unsigned int cpu = policy->cpu;
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struct eps_cpu_data *centaur;
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u32 lo, hi;
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if (eps_cpu[cpu] == NULL)
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return -ENODEV;
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centaur = eps_cpu[cpu];
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/* Get max frequency */
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rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
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/* Set max frequency */
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eps_set_state(centaur, cpu, hi & 0xffff);
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/* Bye */
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cpufreq_frequency_table_put_attr(policy->cpu);
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kfree(eps_cpu[cpu]);
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eps_cpu[cpu] = NULL;
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return 0;
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}
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static struct freq_attr* eps_attr[] = {
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&cpufreq_freq_attr_scaling_available_freqs,
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NULL,
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};
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static struct cpufreq_driver eps_driver = {
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.verify = eps_verify,
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.target = eps_target,
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.init = eps_cpu_init,
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.exit = eps_cpu_exit,
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.get = eps_get,
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.name = "e_powersaver",
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.owner = THIS_MODULE,
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.attr = eps_attr,
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};
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static int __init eps_init(void)
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{
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struct cpuinfo_x86 *c = cpu_data;
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/* This driver will work only on Centaur C7 processors with
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* Enhanced SpeedStep/PowerSaver registers */
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if (c->x86_vendor != X86_VENDOR_CENTAUR
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|| c->x86 != 6 || c->x86_model != 10)
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return -ENODEV;
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if (!cpu_has(c, X86_FEATURE_EST))
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return -ENODEV;
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if (cpufreq_register_driver(&eps_driver))
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return -EINVAL;
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return 0;
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}
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static void __exit eps_exit(void)
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{
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cpufreq_unregister_driver(&eps_driver);
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}
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MODULE_AUTHOR("Rafa<EFBFBD> Bilski <rafalbilski@interia.pl>");
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MODULE_DESCRIPTION("Enhanced PowerSaver driver for VIA C7 CPU's.");
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MODULE_LICENSE("GPL");
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module_init(eps_init);
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module_exit(eps_exit);
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