![David Woodhouse](/assets/img/avatar_default.png)
Conflicts: drivers/mtd/mtdcore.c Pull in the bdi fixes and ARM platform changes that other outstanding patches depend on.
914 lines
21 KiB
C
914 lines
21 KiB
C
/*
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* SuperH FLCTL nand controller
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*
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* Copyright (c) 2008 Renesas Solutions Corp.
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* Copyright (c) 2008 Atom Create Engineering Co., Ltd.
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*
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* Based on fsl_elbc_nand.c, Copyright (c) 2006-2007 Freescale Semiconductor
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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#include <linux/mtd/sh_flctl.h>
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static struct nand_ecclayout flctl_4secc_oob_16 = {
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.eccbytes = 10,
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.eccpos = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9},
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.oobfree = {
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{.offset = 12,
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. length = 4} },
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};
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static struct nand_ecclayout flctl_4secc_oob_64 = {
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.eccbytes = 10,
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.eccpos = {48, 49, 50, 51, 52, 53, 54, 55, 56, 57},
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.oobfree = {
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{.offset = 60,
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. length = 4} },
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};
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static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
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static struct nand_bbt_descr flctl_4secc_smallpage = {
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.options = NAND_BBT_SCAN2NDPAGE,
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.offs = 11,
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.len = 1,
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.pattern = scan_ff_pattern,
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};
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static struct nand_bbt_descr flctl_4secc_largepage = {
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.options = NAND_BBT_SCAN2NDPAGE,
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.offs = 58,
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.len = 2,
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.pattern = scan_ff_pattern,
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};
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static void empty_fifo(struct sh_flctl *flctl)
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{
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writel(0x000c0000, FLINTDMACR(flctl)); /* FIFO Clear */
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writel(0x00000000, FLINTDMACR(flctl)); /* Clear Error flags */
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}
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static void start_translation(struct sh_flctl *flctl)
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{
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writeb(TRSTRT, FLTRCR(flctl));
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}
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static void timeout_error(struct sh_flctl *flctl, const char *str)
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{
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dev_err(&flctl->pdev->dev, "Timeout occured in %s\n", str);
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}
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static void wait_completion(struct sh_flctl *flctl)
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{
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uint32_t timeout = LOOP_TIMEOUT_MAX;
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while (timeout--) {
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if (readb(FLTRCR(flctl)) & TREND) {
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writeb(0x0, FLTRCR(flctl));
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return;
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}
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udelay(1);
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}
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timeout_error(flctl, __func__);
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writeb(0x0, FLTRCR(flctl));
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}
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static void set_addr(struct mtd_info *mtd, int column, int page_addr)
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{
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struct sh_flctl *flctl = mtd_to_flctl(mtd);
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uint32_t addr = 0;
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if (column == -1) {
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addr = page_addr; /* ERASE1 */
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} else if (page_addr != -1) {
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/* SEQIN, READ0, etc.. */
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if (flctl->chip.options & NAND_BUSWIDTH_16)
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column >>= 1;
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if (flctl->page_size) {
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addr = column & 0x0FFF;
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addr |= (page_addr & 0xff) << 16;
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addr |= ((page_addr >> 8) & 0xff) << 24;
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/* big than 128MB */
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if (flctl->rw_ADRCNT == ADRCNT2_E) {
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uint32_t addr2;
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addr2 = (page_addr >> 16) & 0xff;
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writel(addr2, FLADR2(flctl));
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}
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} else {
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addr = column;
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addr |= (page_addr & 0xff) << 8;
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addr |= ((page_addr >> 8) & 0xff) << 16;
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addr |= ((page_addr >> 16) & 0xff) << 24;
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}
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}
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writel(addr, FLADR(flctl));
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}
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static void wait_rfifo_ready(struct sh_flctl *flctl)
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{
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uint32_t timeout = LOOP_TIMEOUT_MAX;
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while (timeout--) {
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uint32_t val;
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/* check FIFO */
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val = readl(FLDTCNTR(flctl)) >> 16;
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if (val & 0xFF)
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return;
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udelay(1);
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}
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timeout_error(flctl, __func__);
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}
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static void wait_wfifo_ready(struct sh_flctl *flctl)
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{
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uint32_t len, timeout = LOOP_TIMEOUT_MAX;
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while (timeout--) {
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/* check FIFO */
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len = (readl(FLDTCNTR(flctl)) >> 16) & 0xFF;
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if (len >= 4)
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return;
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udelay(1);
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}
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timeout_error(flctl, __func__);
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}
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static int wait_recfifo_ready(struct sh_flctl *flctl, int sector_number)
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{
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uint32_t timeout = LOOP_TIMEOUT_MAX;
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int checked[4];
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void __iomem *ecc_reg[4];
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int i;
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uint32_t data, size;
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memset(checked, 0, sizeof(checked));
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while (timeout--) {
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size = readl(FLDTCNTR(flctl)) >> 24;
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if (size & 0xFF)
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return 0; /* success */
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if (readl(FL4ECCCR(flctl)) & _4ECCFA)
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return 1; /* can't correct */
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udelay(1);
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if (!(readl(FL4ECCCR(flctl)) & _4ECCEND))
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continue;
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/* start error correction */
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ecc_reg[0] = FL4ECCRESULT0(flctl);
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ecc_reg[1] = FL4ECCRESULT1(flctl);
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ecc_reg[2] = FL4ECCRESULT2(flctl);
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ecc_reg[3] = FL4ECCRESULT3(flctl);
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for (i = 0; i < 3; i++) {
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data = readl(ecc_reg[i]);
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if (data != INIT_FL4ECCRESULT_VAL && !checked[i]) {
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uint8_t org;
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int index;
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if (flctl->page_size)
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index = (512 * sector_number) +
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(data >> 16);
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else
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index = data >> 16;
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org = flctl->done_buff[index];
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flctl->done_buff[index] = org ^ (data & 0xFF);
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checked[i] = 1;
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}
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}
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writel(0, FL4ECCCR(flctl));
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}
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timeout_error(flctl, __func__);
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return 1; /* timeout */
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}
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static void wait_wecfifo_ready(struct sh_flctl *flctl)
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{
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uint32_t timeout = LOOP_TIMEOUT_MAX;
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uint32_t len;
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while (timeout--) {
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/* check FLECFIFO */
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len = (readl(FLDTCNTR(flctl)) >> 24) & 0xFF;
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if (len >= 4)
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return;
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udelay(1);
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}
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timeout_error(flctl, __func__);
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}
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static void read_datareg(struct sh_flctl *flctl, int offset)
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{
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unsigned long data;
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unsigned long *buf = (unsigned long *)&flctl->done_buff[offset];
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wait_completion(flctl);
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data = readl(FLDATAR(flctl));
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*buf = le32_to_cpu(data);
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}
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static void read_fiforeg(struct sh_flctl *flctl, int rlen, int offset)
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{
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int i, len_4align;
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unsigned long *buf = (unsigned long *)&flctl->done_buff[offset];
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void *fifo_addr = (void *)FLDTFIFO(flctl);
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len_4align = (rlen + 3) / 4;
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for (i = 0; i < len_4align; i++) {
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wait_rfifo_ready(flctl);
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buf[i] = readl(fifo_addr);
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buf[i] = be32_to_cpu(buf[i]);
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}
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}
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static int read_ecfiforeg(struct sh_flctl *flctl, uint8_t *buff, int sector)
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{
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int i;
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unsigned long *ecc_buf = (unsigned long *)buff;
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void *fifo_addr = (void *)FLECFIFO(flctl);
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for (i = 0; i < 4; i++) {
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if (wait_recfifo_ready(flctl , sector))
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return 1;
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ecc_buf[i] = readl(fifo_addr);
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ecc_buf[i] = be32_to_cpu(ecc_buf[i]);
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}
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return 0;
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}
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static void write_fiforeg(struct sh_flctl *flctl, int rlen, int offset)
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{
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int i, len_4align;
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unsigned long *data = (unsigned long *)&flctl->done_buff[offset];
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void *fifo_addr = (void *)FLDTFIFO(flctl);
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len_4align = (rlen + 3) / 4;
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for (i = 0; i < len_4align; i++) {
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wait_wfifo_ready(flctl);
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writel(cpu_to_be32(data[i]), fifo_addr);
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}
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}
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static void set_cmd_regs(struct mtd_info *mtd, uint32_t cmd, uint32_t flcmcdr_val)
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{
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struct sh_flctl *flctl = mtd_to_flctl(mtd);
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uint32_t flcmncr_val = readl(FLCMNCR(flctl)) & ~SEL_16BIT;
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uint32_t flcmdcr_val, addr_len_bytes = 0;
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/* Set SNAND bit if page size is 2048byte */
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if (flctl->page_size)
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flcmncr_val |= SNAND_E;
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else
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flcmncr_val &= ~SNAND_E;
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/* default FLCMDCR val */
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flcmdcr_val = DOCMD1_E | DOADR_E;
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/* Set for FLCMDCR */
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switch (cmd) {
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case NAND_CMD_ERASE1:
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addr_len_bytes = flctl->erase_ADRCNT;
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flcmdcr_val |= DOCMD2_E;
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break;
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case NAND_CMD_READ0:
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case NAND_CMD_READOOB:
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addr_len_bytes = flctl->rw_ADRCNT;
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flcmdcr_val |= CDSRC_E;
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if (flctl->chip.options & NAND_BUSWIDTH_16)
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flcmncr_val |= SEL_16BIT;
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break;
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case NAND_CMD_SEQIN:
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/* This case is that cmd is READ0 or READ1 or READ00 */
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flcmdcr_val &= ~DOADR_E; /* ONLY execute 1st cmd */
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break;
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case NAND_CMD_PAGEPROG:
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addr_len_bytes = flctl->rw_ADRCNT;
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flcmdcr_val |= DOCMD2_E | CDSRC_E | SELRW;
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if (flctl->chip.options & NAND_BUSWIDTH_16)
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flcmncr_val |= SEL_16BIT;
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break;
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case NAND_CMD_READID:
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flcmncr_val &= ~SNAND_E;
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addr_len_bytes = ADRCNT_1;
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break;
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case NAND_CMD_STATUS:
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case NAND_CMD_RESET:
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flcmncr_val &= ~SNAND_E;
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flcmdcr_val &= ~(DOADR_E | DOSR_E);
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break;
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default:
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break;
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}
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/* Set address bytes parameter */
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flcmdcr_val |= addr_len_bytes;
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/* Now actually write */
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writel(flcmncr_val, FLCMNCR(flctl));
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writel(flcmdcr_val, FLCMDCR(flctl));
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writel(flcmcdr_val, FLCMCDR(flctl));
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}
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static int flctl_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
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uint8_t *buf, int page)
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{
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int i, eccsize = chip->ecc.size;
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int eccbytes = chip->ecc.bytes;
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int eccsteps = chip->ecc.steps;
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uint8_t *p = buf;
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struct sh_flctl *flctl = mtd_to_flctl(mtd);
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for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
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chip->read_buf(mtd, p, eccsize);
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for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
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if (flctl->hwecc_cant_correct[i])
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mtd->ecc_stats.failed++;
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else
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mtd->ecc_stats.corrected += 0;
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}
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return 0;
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}
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static void flctl_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
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const uint8_t *buf)
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{
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int i, eccsize = chip->ecc.size;
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int eccbytes = chip->ecc.bytes;
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int eccsteps = chip->ecc.steps;
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const uint8_t *p = buf;
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for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
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chip->write_buf(mtd, p, eccsize);
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}
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static void execmd_read_page_sector(struct mtd_info *mtd, int page_addr)
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{
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struct sh_flctl *flctl = mtd_to_flctl(mtd);
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int sector, page_sectors;
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if (flctl->page_size)
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page_sectors = 4;
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else
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page_sectors = 1;
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writel(readl(FLCMNCR(flctl)) | ACM_SACCES_MODE | _4ECCCORRECT,
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FLCMNCR(flctl));
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set_cmd_regs(mtd, NAND_CMD_READ0,
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(NAND_CMD_READSTART << 8) | NAND_CMD_READ0);
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for (sector = 0; sector < page_sectors; sector++) {
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int ret;
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empty_fifo(flctl);
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writel(readl(FLCMDCR(flctl)) | 1, FLCMDCR(flctl));
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writel(page_addr << 2 | sector, FLADR(flctl));
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start_translation(flctl);
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read_fiforeg(flctl, 512, 512 * sector);
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ret = read_ecfiforeg(flctl,
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&flctl->done_buff[mtd->writesize + 16 * sector],
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sector);
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if (ret)
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flctl->hwecc_cant_correct[sector] = 1;
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writel(0x0, FL4ECCCR(flctl));
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wait_completion(flctl);
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}
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writel(readl(FLCMNCR(flctl)) & ~(ACM_SACCES_MODE | _4ECCCORRECT),
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FLCMNCR(flctl));
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}
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static void execmd_read_oob(struct mtd_info *mtd, int page_addr)
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{
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struct sh_flctl *flctl = mtd_to_flctl(mtd);
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set_cmd_regs(mtd, NAND_CMD_READ0,
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(NAND_CMD_READSTART << 8) | NAND_CMD_READ0);
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empty_fifo(flctl);
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if (flctl->page_size) {
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int i;
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/* In case that the page size is 2k */
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for (i = 0; i < 16 * 3; i++)
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flctl->done_buff[i] = 0xFF;
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set_addr(mtd, 3 * 528 + 512, page_addr);
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writel(16, FLDTCNTR(flctl));
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start_translation(flctl);
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read_fiforeg(flctl, 16, 16 * 3);
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wait_completion(flctl);
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} else {
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/* In case that the page size is 512b */
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set_addr(mtd, 512, page_addr);
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writel(16, FLDTCNTR(flctl));
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start_translation(flctl);
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read_fiforeg(flctl, 16, 0);
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wait_completion(flctl);
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}
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}
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static void execmd_write_page_sector(struct mtd_info *mtd)
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{
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struct sh_flctl *flctl = mtd_to_flctl(mtd);
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int i, page_addr = flctl->seqin_page_addr;
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int sector, page_sectors;
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if (flctl->page_size)
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page_sectors = 4;
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else
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page_sectors = 1;
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writel(readl(FLCMNCR(flctl)) | ACM_SACCES_MODE, FLCMNCR(flctl));
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set_cmd_regs(mtd, NAND_CMD_PAGEPROG,
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(NAND_CMD_PAGEPROG << 8) | NAND_CMD_SEQIN);
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for (sector = 0; sector < page_sectors; sector++) {
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empty_fifo(flctl);
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writel(readl(FLCMDCR(flctl)) | 1, FLCMDCR(flctl));
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writel(page_addr << 2 | sector, FLADR(flctl));
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start_translation(flctl);
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write_fiforeg(flctl, 512, 512 * sector);
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for (i = 0; i < 4; i++) {
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wait_wecfifo_ready(flctl); /* wait for write ready */
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writel(0xFFFFFFFF, FLECFIFO(flctl));
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}
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wait_completion(flctl);
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}
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writel(readl(FLCMNCR(flctl)) & ~ACM_SACCES_MODE, FLCMNCR(flctl));
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}
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static void execmd_write_oob(struct mtd_info *mtd)
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{
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struct sh_flctl *flctl = mtd_to_flctl(mtd);
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int page_addr = flctl->seqin_page_addr;
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int sector, page_sectors;
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if (flctl->page_size) {
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sector = 3;
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page_sectors = 4;
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} else {
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sector = 0;
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page_sectors = 1;
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}
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|
|
set_cmd_regs(mtd, NAND_CMD_PAGEPROG,
|
|
(NAND_CMD_PAGEPROG << 8) | NAND_CMD_SEQIN);
|
|
|
|
for (; sector < page_sectors; sector++) {
|
|
empty_fifo(flctl);
|
|
set_addr(mtd, sector * 528 + 512, page_addr);
|
|
writel(16, FLDTCNTR(flctl)); /* set read size */
|
|
|
|
start_translation(flctl);
|
|
write_fiforeg(flctl, 16, 16 * sector);
|
|
wait_completion(flctl);
|
|
}
|
|
}
|
|
|
|
static void flctl_cmdfunc(struct mtd_info *mtd, unsigned int command,
|
|
int column, int page_addr)
|
|
{
|
|
struct sh_flctl *flctl = mtd_to_flctl(mtd);
|
|
uint32_t read_cmd = 0;
|
|
|
|
flctl->read_bytes = 0;
|
|
if (command != NAND_CMD_PAGEPROG)
|
|
flctl->index = 0;
|
|
|
|
switch (command) {
|
|
case NAND_CMD_READ1:
|
|
case NAND_CMD_READ0:
|
|
if (flctl->hwecc) {
|
|
/* read page with hwecc */
|
|
execmd_read_page_sector(mtd, page_addr);
|
|
break;
|
|
}
|
|
empty_fifo(flctl);
|
|
if (flctl->page_size)
|
|
set_cmd_regs(mtd, command, (NAND_CMD_READSTART << 8)
|
|
| command);
|
|
else
|
|
set_cmd_regs(mtd, command, command);
|
|
|
|
set_addr(mtd, 0, page_addr);
|
|
|
|
flctl->read_bytes = mtd->writesize + mtd->oobsize;
|
|
if (flctl->chip.options & NAND_BUSWIDTH_16)
|
|
column >>= 1;
|
|
flctl->index += column;
|
|
goto read_normal_exit;
|
|
|
|
case NAND_CMD_READOOB:
|
|
if (flctl->hwecc) {
|
|
/* read page with hwecc */
|
|
execmd_read_oob(mtd, page_addr);
|
|
break;
|
|
}
|
|
|
|
empty_fifo(flctl);
|
|
if (flctl->page_size) {
|
|
set_cmd_regs(mtd, command, (NAND_CMD_READSTART << 8)
|
|
| NAND_CMD_READ0);
|
|
set_addr(mtd, mtd->writesize, page_addr);
|
|
} else {
|
|
set_cmd_regs(mtd, command, command);
|
|
set_addr(mtd, 0, page_addr);
|
|
}
|
|
flctl->read_bytes = mtd->oobsize;
|
|
goto read_normal_exit;
|
|
|
|
case NAND_CMD_READID:
|
|
empty_fifo(flctl);
|
|
set_cmd_regs(mtd, command, command);
|
|
set_addr(mtd, 0, 0);
|
|
|
|
flctl->read_bytes = 4;
|
|
writel(flctl->read_bytes, FLDTCNTR(flctl)); /* set read size */
|
|
start_translation(flctl);
|
|
read_datareg(flctl, 0); /* read and end */
|
|
break;
|
|
|
|
case NAND_CMD_ERASE1:
|
|
flctl->erase1_page_addr = page_addr;
|
|
break;
|
|
|
|
case NAND_CMD_ERASE2:
|
|
set_cmd_regs(mtd, NAND_CMD_ERASE1,
|
|
(command << 8) | NAND_CMD_ERASE1);
|
|
set_addr(mtd, -1, flctl->erase1_page_addr);
|
|
start_translation(flctl);
|
|
wait_completion(flctl);
|
|
break;
|
|
|
|
case NAND_CMD_SEQIN:
|
|
if (!flctl->page_size) {
|
|
/* output read command */
|
|
if (column >= mtd->writesize) {
|
|
column -= mtd->writesize;
|
|
read_cmd = NAND_CMD_READOOB;
|
|
} else if (column < 256) {
|
|
read_cmd = NAND_CMD_READ0;
|
|
} else {
|
|
column -= 256;
|
|
read_cmd = NAND_CMD_READ1;
|
|
}
|
|
}
|
|
flctl->seqin_column = column;
|
|
flctl->seqin_page_addr = page_addr;
|
|
flctl->seqin_read_cmd = read_cmd;
|
|
break;
|
|
|
|
case NAND_CMD_PAGEPROG:
|
|
empty_fifo(flctl);
|
|
if (!flctl->page_size) {
|
|
set_cmd_regs(mtd, NAND_CMD_SEQIN,
|
|
flctl->seqin_read_cmd);
|
|
set_addr(mtd, -1, -1);
|
|
writel(0, FLDTCNTR(flctl)); /* set 0 size */
|
|
start_translation(flctl);
|
|
wait_completion(flctl);
|
|
}
|
|
if (flctl->hwecc) {
|
|
/* write page with hwecc */
|
|
if (flctl->seqin_column == mtd->writesize)
|
|
execmd_write_oob(mtd);
|
|
else if (!flctl->seqin_column)
|
|
execmd_write_page_sector(mtd);
|
|
else
|
|
printk(KERN_ERR "Invalid address !?\n");
|
|
break;
|
|
}
|
|
set_cmd_regs(mtd, command, (command << 8) | NAND_CMD_SEQIN);
|
|
set_addr(mtd, flctl->seqin_column, flctl->seqin_page_addr);
|
|
writel(flctl->index, FLDTCNTR(flctl)); /* set write size */
|
|
start_translation(flctl);
|
|
write_fiforeg(flctl, flctl->index, 0);
|
|
wait_completion(flctl);
|
|
break;
|
|
|
|
case NAND_CMD_STATUS:
|
|
set_cmd_regs(mtd, command, command);
|
|
set_addr(mtd, -1, -1);
|
|
|
|
flctl->read_bytes = 1;
|
|
writel(flctl->read_bytes, FLDTCNTR(flctl)); /* set read size */
|
|
start_translation(flctl);
|
|
read_datareg(flctl, 0); /* read and end */
|
|
break;
|
|
|
|
case NAND_CMD_RESET:
|
|
set_cmd_regs(mtd, command, command);
|
|
set_addr(mtd, -1, -1);
|
|
|
|
writel(0, FLDTCNTR(flctl)); /* set 0 size */
|
|
start_translation(flctl);
|
|
wait_completion(flctl);
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
return;
|
|
|
|
read_normal_exit:
|
|
writel(flctl->read_bytes, FLDTCNTR(flctl)); /* set read size */
|
|
start_translation(flctl);
|
|
read_fiforeg(flctl, flctl->read_bytes, 0);
|
|
wait_completion(flctl);
|
|
return;
|
|
}
|
|
|
|
static void flctl_select_chip(struct mtd_info *mtd, int chipnr)
|
|
{
|
|
struct sh_flctl *flctl = mtd_to_flctl(mtd);
|
|
uint32_t flcmncr_val = readl(FLCMNCR(flctl));
|
|
|
|
switch (chipnr) {
|
|
case -1:
|
|
flcmncr_val &= ~CE0_ENABLE;
|
|
writel(flcmncr_val, FLCMNCR(flctl));
|
|
break;
|
|
case 0:
|
|
flcmncr_val |= CE0_ENABLE;
|
|
writel(flcmncr_val, FLCMNCR(flctl));
|
|
break;
|
|
default:
|
|
BUG();
|
|
}
|
|
}
|
|
|
|
static void flctl_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
|
|
{
|
|
struct sh_flctl *flctl = mtd_to_flctl(mtd);
|
|
int i, index = flctl->index;
|
|
|
|
for (i = 0; i < len; i++)
|
|
flctl->done_buff[index + i] = buf[i];
|
|
flctl->index += len;
|
|
}
|
|
|
|
static uint8_t flctl_read_byte(struct mtd_info *mtd)
|
|
{
|
|
struct sh_flctl *flctl = mtd_to_flctl(mtd);
|
|
int index = flctl->index;
|
|
uint8_t data;
|
|
|
|
data = flctl->done_buff[index];
|
|
flctl->index++;
|
|
return data;
|
|
}
|
|
|
|
static uint16_t flctl_read_word(struct mtd_info *mtd)
|
|
{
|
|
struct sh_flctl *flctl = mtd_to_flctl(mtd);
|
|
int index = flctl->index;
|
|
uint16_t data;
|
|
uint16_t *buf = (uint16_t *)&flctl->done_buff[index];
|
|
|
|
data = *buf;
|
|
flctl->index += 2;
|
|
return data;
|
|
}
|
|
|
|
static void flctl_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < len; i++)
|
|
buf[i] = flctl_read_byte(mtd);
|
|
}
|
|
|
|
static int flctl_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < len; i++)
|
|
if (buf[i] != flctl_read_byte(mtd))
|
|
return -EFAULT;
|
|
return 0;
|
|
}
|
|
|
|
static void flctl_register_init(struct sh_flctl *flctl, unsigned long val)
|
|
{
|
|
writel(val, FLCMNCR(flctl));
|
|
}
|
|
|
|
static int flctl_chip_init_tail(struct mtd_info *mtd)
|
|
{
|
|
struct sh_flctl *flctl = mtd_to_flctl(mtd);
|
|
struct nand_chip *chip = &flctl->chip;
|
|
|
|
if (mtd->writesize == 512) {
|
|
flctl->page_size = 0;
|
|
if (chip->chipsize > (32 << 20)) {
|
|
/* big than 32MB */
|
|
flctl->rw_ADRCNT = ADRCNT_4;
|
|
flctl->erase_ADRCNT = ADRCNT_3;
|
|
} else if (chip->chipsize > (2 << 16)) {
|
|
/* big than 128KB */
|
|
flctl->rw_ADRCNT = ADRCNT_3;
|
|
flctl->erase_ADRCNT = ADRCNT_2;
|
|
} else {
|
|
flctl->rw_ADRCNT = ADRCNT_2;
|
|
flctl->erase_ADRCNT = ADRCNT_1;
|
|
}
|
|
} else {
|
|
flctl->page_size = 1;
|
|
if (chip->chipsize > (128 << 20)) {
|
|
/* big than 128MB */
|
|
flctl->rw_ADRCNT = ADRCNT2_E;
|
|
flctl->erase_ADRCNT = ADRCNT_3;
|
|
} else if (chip->chipsize > (8 << 16)) {
|
|
/* big than 512KB */
|
|
flctl->rw_ADRCNT = ADRCNT_4;
|
|
flctl->erase_ADRCNT = ADRCNT_2;
|
|
} else {
|
|
flctl->rw_ADRCNT = ADRCNT_3;
|
|
flctl->erase_ADRCNT = ADRCNT_1;
|
|
}
|
|
}
|
|
|
|
if (flctl->hwecc) {
|
|
if (mtd->writesize == 512) {
|
|
chip->ecc.layout = &flctl_4secc_oob_16;
|
|
chip->badblock_pattern = &flctl_4secc_smallpage;
|
|
} else {
|
|
chip->ecc.layout = &flctl_4secc_oob_64;
|
|
chip->badblock_pattern = &flctl_4secc_largepage;
|
|
}
|
|
|
|
chip->ecc.size = 512;
|
|
chip->ecc.bytes = 10;
|
|
chip->ecc.read_page = flctl_read_page_hwecc;
|
|
chip->ecc.write_page = flctl_write_page_hwecc;
|
|
chip->ecc.mode = NAND_ECC_HW;
|
|
|
|
/* 4 symbols ECC enabled */
|
|
writel(readl(FLCMNCR(flctl)) | _4ECCEN | ECCPOS2 | ECCPOS_02,
|
|
FLCMNCR(flctl));
|
|
} else {
|
|
chip->ecc.mode = NAND_ECC_SOFT;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __devinit flctl_probe(struct platform_device *pdev)
|
|
{
|
|
struct resource *res;
|
|
struct sh_flctl *flctl;
|
|
struct mtd_info *flctl_mtd;
|
|
struct nand_chip *nand;
|
|
struct sh_flctl_platform_data *pdata;
|
|
int ret = -ENXIO;
|
|
|
|
pdata = pdev->dev.platform_data;
|
|
if (pdata == NULL) {
|
|
dev_err(&pdev->dev, "no platform data defined\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
flctl = kzalloc(sizeof(struct sh_flctl), GFP_KERNEL);
|
|
if (!flctl) {
|
|
dev_err(&pdev->dev, "failed to allocate driver data\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!res) {
|
|
dev_err(&pdev->dev, "failed to get I/O memory\n");
|
|
goto err;
|
|
}
|
|
|
|
flctl->reg = ioremap(res->start, resource_size(res));
|
|
if (flctl->reg == NULL) {
|
|
dev_err(&pdev->dev, "failed to remap I/O memory\n");
|
|
goto err;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, flctl);
|
|
flctl_mtd = &flctl->mtd;
|
|
nand = &flctl->chip;
|
|
flctl_mtd->priv = nand;
|
|
flctl->pdev = pdev;
|
|
flctl->hwecc = pdata->has_hwecc;
|
|
|
|
flctl_register_init(flctl, pdata->flcmncr_val);
|
|
|
|
nand->options = NAND_NO_AUTOINCR;
|
|
|
|
/* Set address of hardware control function */
|
|
/* 20 us command delay time */
|
|
nand->chip_delay = 20;
|
|
|
|
nand->read_byte = flctl_read_byte;
|
|
nand->write_buf = flctl_write_buf;
|
|
nand->read_buf = flctl_read_buf;
|
|
nand->verify_buf = flctl_verify_buf;
|
|
nand->select_chip = flctl_select_chip;
|
|
nand->cmdfunc = flctl_cmdfunc;
|
|
|
|
if (pdata->flcmncr_val & SEL_16BIT) {
|
|
nand->options |= NAND_BUSWIDTH_16;
|
|
nand->read_word = flctl_read_word;
|
|
}
|
|
|
|
ret = nand_scan_ident(flctl_mtd, 1, NULL);
|
|
if (ret)
|
|
goto err;
|
|
|
|
ret = flctl_chip_init_tail(flctl_mtd);
|
|
if (ret)
|
|
goto err;
|
|
|
|
ret = nand_scan_tail(flctl_mtd);
|
|
if (ret)
|
|
goto err;
|
|
|
|
add_mtd_partitions(flctl_mtd, pdata->parts, pdata->nr_parts);
|
|
|
|
return 0;
|
|
|
|
err:
|
|
kfree(flctl);
|
|
return ret;
|
|
}
|
|
|
|
static int __devexit flctl_remove(struct platform_device *pdev)
|
|
{
|
|
struct sh_flctl *flctl = platform_get_drvdata(pdev);
|
|
|
|
nand_release(&flctl->mtd);
|
|
kfree(flctl);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver flctl_driver = {
|
|
.remove = flctl_remove,
|
|
.driver = {
|
|
.name = "sh_flctl",
|
|
.owner = THIS_MODULE,
|
|
},
|
|
};
|
|
|
|
static int __init flctl_nand_init(void)
|
|
{
|
|
return platform_driver_probe(&flctl_driver, flctl_probe);
|
|
}
|
|
|
|
static void __exit flctl_nand_cleanup(void)
|
|
{
|
|
platform_driver_unregister(&flctl_driver);
|
|
}
|
|
|
|
module_init(flctl_nand_init);
|
|
module_exit(flctl_nand_cleanup);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("Yoshihiro Shimoda");
|
|
MODULE_DESCRIPTION("SuperH FLCTL driver");
|
|
MODULE_ALIAS("platform:sh_flctl");
|