762 lines
19 KiB
C
762 lines
19 KiB
C
/*
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* Copyright © 2010 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* jim liu <jim.liu@intel.com>
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* Jackie Li<yaodong.li@intel.com>
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*/
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#include "mdfld_dsi_dbi.h"
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#include "mdfld_dsi_dbi_dpu.h"
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#include "mdfld_dsi_pkg_sender.h"
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#include "power.h"
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#include <linux/pm_runtime.h>
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int enable_gfx_rtpm;
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extern struct drm_device *gpDrmDevice;
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extern int gfxrtdelay;
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int enter_dsr;
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struct mdfld_dsi_dbi_output *gdbi_output;
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extern bool gbgfxsuspended;
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extern int enable_gfx_rtpm;
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extern int gfxrtdelay;
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#define MDFLD_DSR_MAX_IDLE_COUNT 2
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/*
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* set refreshing area
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*/
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int mdfld_dsi_dbi_update_area(struct mdfld_dsi_dbi_output *dbi_output,
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u16 x1, u16 y1, u16 x2, u16 y2)
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{
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struct mdfld_dsi_pkg_sender *sender =
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mdfld_dsi_encoder_get_pkg_sender(&dbi_output->base);
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u8 param[4];
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u8 cmd;
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int err;
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if (!sender) {
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WARN_ON(1);
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return -EINVAL;
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}
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/* Set column */
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cmd = DCS_SET_COLUMN_ADDRESS;
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param[0] = x1 >> 8;
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param[1] = x1;
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param[2] = x2 >> 8;
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param[3] = x2;
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err = mdfld_dsi_send_dcs(sender,
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cmd,
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param,
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4,
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CMD_DATA_SRC_SYSTEM_MEM,
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MDFLD_DSI_QUEUE_PACKAGE);
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if (err) {
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dev_err(sender->dev->dev, "DCS 0x%x sent failed\n", cmd);
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goto err_out;
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}
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/* Set page */
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cmd = DCS_SET_PAGE_ADDRESS;
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param[0] = y1 >> 8;
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param[1] = y1;
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param[2] = y2 >> 8;
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param[3] = y2;
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err = mdfld_dsi_send_dcs(sender,
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cmd,
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param,
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4,
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CMD_DATA_SRC_SYSTEM_MEM,
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MDFLD_DSI_QUEUE_PACKAGE);
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if (err) {
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dev_err(sender->dev->dev, "DCS 0x%x sent failed\n", cmd);
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goto err_out;
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}
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/*update screen*/
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err = mdfld_dsi_send_dcs(sender,
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write_mem_start,
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NULL,
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0,
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CMD_DATA_SRC_PIPE,
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MDFLD_DSI_QUEUE_PACKAGE);
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if (err) {
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dev_err(sender->dev->dev, "DCS 0x%x sent failed\n", cmd);
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goto err_out;
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}
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mdfld_dsi_cmds_kick_out(sender);
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err_out:
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return err;
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}
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/*
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* set panel's power state
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*/
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int mdfld_dsi_dbi_update_power(struct mdfld_dsi_dbi_output *dbi_output,
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int mode)
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{
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struct drm_device *dev = dbi_output->dev;
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struct mdfld_dsi_pkg_sender *sender =
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mdfld_dsi_encoder_get_pkg_sender(&dbi_output->base);
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u8 param = 0;
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u32 err = 0;
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if (!sender) {
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WARN_ON(1);
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return -EINVAL;
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}
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if (mode == DRM_MODE_DPMS_ON) {
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/* Exit sleep mode */
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err = mdfld_dsi_send_dcs(sender,
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DCS_EXIT_SLEEP_MODE,
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NULL,
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0,
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CMD_DATA_SRC_SYSTEM_MEM,
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MDFLD_DSI_QUEUE_PACKAGE);
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if (err) {
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dev_err(dev->dev, "DCS 0x%x sent failed\n",
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DCS_EXIT_SLEEP_MODE);
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goto power_err;
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}
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/* Set display on */
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err = mdfld_dsi_send_dcs(sender,
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DCS_SET_DISPLAY_ON,
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NULL,
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0,
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CMD_DATA_SRC_SYSTEM_MEM,
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MDFLD_DSI_QUEUE_PACKAGE);
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if (err) {
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dev_err(dev->dev, "DCS 0x%x sent failed\n",
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DCS_SET_DISPLAY_ON);
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goto power_err;
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}
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/* set tear effect on */
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err = mdfld_dsi_send_dcs(sender,
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DCS_SET_TEAR_ON,
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¶m,
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1,
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CMD_DATA_SRC_SYSTEM_MEM,
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MDFLD_DSI_QUEUE_PACKAGE);
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if (err) {
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dev_err(dev->dev, "DCS 0x%x sent failed\n",
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set_tear_on);
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goto power_err;
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}
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/**
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* FIXME: remove this later
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*/
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err = mdfld_dsi_send_dcs(sender,
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DCS_WRITE_MEM_START,
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NULL,
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0,
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CMD_DATA_SRC_PIPE,
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MDFLD_DSI_QUEUE_PACKAGE);
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if (err) {
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dev_err(dev->dev, "DCS 0x%x sent failed\n",
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DCS_WRITE_MEM_START);
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goto power_err;
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}
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} else {
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/* Set tear effect off */
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err = mdfld_dsi_send_dcs(sender,
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DCS_SET_TEAR_OFF,
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NULL,
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0,
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CMD_DATA_SRC_SYSTEM_MEM,
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MDFLD_DSI_QUEUE_PACKAGE);
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if (err) {
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dev_err(dev->dev, "DCS 0x%x sent failed\n",
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DCS_SET_TEAR_OFF);
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goto power_err;
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}
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/* Turn display off */
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err = mdfld_dsi_send_dcs(sender,
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DCS_SET_DISPLAY_OFF,
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NULL,
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0,
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CMD_DATA_SRC_SYSTEM_MEM,
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MDFLD_DSI_QUEUE_PACKAGE);
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if (err) {
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dev_err(dev->dev, "DCS 0x%x sent failed\n",
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DCS_SET_DISPLAY_OFF);
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goto power_err;
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}
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/* Now enter sleep mode */
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err = mdfld_dsi_send_dcs(sender,
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DCS_ENTER_SLEEP_MODE,
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NULL,
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0,
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CMD_DATA_SRC_SYSTEM_MEM,
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MDFLD_DSI_QUEUE_PACKAGE);
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if (err) {
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dev_err(dev->dev, "DCS 0x%x sent failed\n",
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DCS_ENTER_SLEEP_MODE);
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goto power_err;
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}
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}
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mdfld_dsi_cmds_kick_out(sender);
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power_err:
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return err;
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}
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/*
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* send a generic DCS command with a parameter list
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*/
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int mdfld_dsi_dbi_send_dcs(struct mdfld_dsi_dbi_output *dbi_output,
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u8 dcs, u8 *param, u32 num, u8 data_src)
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{
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struct mdfld_dsi_pkg_sender *sender =
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mdfld_dsi_encoder_get_pkg_sender(&dbi_output->base);
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int ret;
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if (!sender) {
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WARN_ON(1);
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return -EINVAL;
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}
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ret = mdfld_dsi_send_dcs(sender,
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dcs,
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param,
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num,
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data_src,
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MDFLD_DSI_SEND_PACKAGE);
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return ret;
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}
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/*
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* Enter DSR
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*/
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void mdfld_dsi_dbi_enter_dsr(struct mdfld_dsi_dbi_output *dbi_output, int pipe)
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{
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u32 reg_val;
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struct drm_device *dev = dbi_output->dev;
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struct drm_psb_private *dev_priv = dev->dev_private;
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struct drm_crtc *crtc = dbi_output->base.base.crtc;
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struct psb_intel_crtc *psb_crtc = (crtc) ?
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to_psb_intel_crtc(crtc) : NULL;
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u32 dpll_reg = MRST_DPLL_A;
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u32 pipeconf_reg = PIPEACONF;
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u32 dspcntr_reg = DSPACNTR;
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if (!dbi_output)
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return;
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/* FIXME check if can go */
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dev_priv->is_in_idle = true;
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gdbi_output = dbi_output;
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if ((dbi_output->mode_flags & MODE_SETTING_ON_GOING) ||
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(psb_crtc && psb_crtc->mode_flags & MODE_SETTING_ON_GOING))
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return;
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if (pipe == 2) {
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dpll_reg = MRST_DPLL_A;
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pipeconf_reg = PIPECCONF;
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dspcntr_reg = DSPCCNTR;
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}
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if (!gma_power_begin(dev, true)) {
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dev_err(dev->dev, "hw begin failed\n");
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return;
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}
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/* Disable te interrupts */
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mdfld_disable_te(dev, pipe);
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/* Disable plane */
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reg_val = REG_READ(dspcntr_reg);
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if (!(reg_val & DISPLAY_PLANE_ENABLE)) {
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REG_WRITE(dspcntr_reg, reg_val & ~DISPLAY_PLANE_ENABLE);
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REG_READ(dspcntr_reg);
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}
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/* Disable pipe */
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reg_val = REG_READ(pipeconf_reg);
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if (!(reg_val & DISPLAY_PLANE_ENABLE)) {
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reg_val &= ~DISPLAY_PLANE_ENABLE;
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reg_val |= (PIPECONF_PLANE_OFF | PIPECONF_CURSOR_OFF);
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REG_WRITE(pipeconf_reg, reg_val);
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REG_READ(pipeconf_reg);
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mdfldWaitForPipeDisable(dev, pipe);
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}
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/* Disable DPLL */
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reg_val = REG_READ(dpll_reg);
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if (!(reg_val & DPLL_VCO_ENABLE)) {
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reg_val &= ~DPLL_VCO_ENABLE;
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REG_WRITE(dpll_reg, reg_val);
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REG_READ(dpll_reg);
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udelay(500);
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}
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gma_power_end(dev);
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dbi_output->mode_flags |= MODE_SETTING_IN_DSR;
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if (pipe == 2) {
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enter_dsr = 1;
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/* pm_schedule_suspend(&dev->pdev->dev, gfxrtdelay); */
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}
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}
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static void mdfld_dbi_output_exit_dsr(struct mdfld_dsi_dbi_output *dbi_output,
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int pipe)
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{
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struct drm_device *dev = dbi_output->dev;
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struct drm_crtc *crtc = dbi_output->base.base.crtc;
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struct psb_intel_crtc *psb_crtc = (crtc) ?
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to_psb_intel_crtc(crtc) : NULL;
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u32 reg_val;
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u32 dpll_reg = MRST_DPLL_A;
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u32 pipeconf_reg = PIPEACONF;
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u32 dspcntr_reg = DSPACNTR;
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u32 reg_offset = 0;
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/*if mode setting on-going, back off*/
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if ((dbi_output->mode_flags & MODE_SETTING_ON_GOING) ||
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(psb_crtc && psb_crtc->mode_flags & MODE_SETTING_ON_GOING))
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return;
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if (pipe == 2) {
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dpll_reg = MRST_DPLL_A;
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pipeconf_reg = PIPECCONF;
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dspcntr_reg = DSPCCNTR;
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reg_offset = MIPIC_REG_OFFSET;
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}
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if (!gma_power_begin(dev, true)) {
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dev_err(dev->dev, "hw begin failed\n");
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return;
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}
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/* Enable DPLL */
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reg_val = REG_READ(dpll_reg);
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if (!(reg_val & DPLL_VCO_ENABLE)) {
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if (reg_val & MDFLD_PWR_GATE_EN) {
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reg_val &= ~MDFLD_PWR_GATE_EN;
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REG_WRITE(dpll_reg, reg_val);
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REG_READ(dpll_reg);
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udelay(500);
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}
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reg_val |= DPLL_VCO_ENABLE;
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REG_WRITE(dpll_reg, reg_val);
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REG_READ(dpll_reg);
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udelay(500);
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/* Add timeout */
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while (!(REG_READ(pipeconf_reg) & PIPECONF_DSIPLL_LOCK))
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cpu_relax();
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}
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/* Enable pipe */
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reg_val = REG_READ(pipeconf_reg);
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if (!(reg_val & PIPEACONF_ENABLE)) {
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reg_val |= PIPEACONF_ENABLE;
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REG_WRITE(pipeconf_reg, reg_val);
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REG_READ(pipeconf_reg);
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udelay(500);
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mdfldWaitForPipeEnable(dev, pipe);
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}
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/* Enable plane */
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reg_val = REG_READ(dspcntr_reg);
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if (!(reg_val & DISPLAY_PLANE_ENABLE)) {
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reg_val |= DISPLAY_PLANE_ENABLE;
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REG_WRITE(dspcntr_reg, reg_val);
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REG_READ(dspcntr_reg);
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udelay(500);
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}
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/* Enable TE interrupt on this pipe */
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mdfld_enable_te(dev, pipe);
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gma_power_end(dev);
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/*clean IN_DSR flag*/
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dbi_output->mode_flags &= ~MODE_SETTING_IN_DSR;
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}
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/*
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* Exit from DSR
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*/
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void mdfld_dsi_dbi_exit_dsr(struct drm_device *dev, u32 update_src)
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{
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struct drm_psb_private *dev_priv = dev->dev_private;
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struct mdfld_dbi_dsr_info *dsr_info = dev_priv->dbi_dsr_info;
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struct mdfld_dsi_dbi_output **dbi_output;
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int i;
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int pipe;
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/* FIXME can go ? */
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dev_priv->is_in_idle = false;
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dbi_output = dsr_info->dbi_outputs;
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#ifdef CONFIG_PM_RUNTIME
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if (!enable_gfx_rtpm) {
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/* pm_runtime_allow(&gpDrmDevice->pdev->dev); */
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/* schedule_delayed_work(&rtpm_work, 30 * 1000);*/ /* FIXME: HZ ? */
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}
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#endif
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/* For each output, exit dsr */
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for (i = 0; i < dsr_info->dbi_output_num; i++) {
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/* If panel has been turned off, skip */
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if (!dbi_output[i] || !dbi_output[i]->dbi_panel_on)
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continue;
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pipe = dbi_output[i]->channel_num ? 2 : 0;
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enter_dsr = 0;
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mdfld_dbi_output_exit_dsr(dbi_output[i], pipe);
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}
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dev_priv->dsr_fb_update |= update_src;
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}
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static bool mdfld_dbi_is_in_dsr(struct drm_device *dev)
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{
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if (REG_READ(MRST_DPLL_A) & DPLL_VCO_ENABLE)
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return false;
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if ((REG_READ(PIPEACONF) & PIPEACONF_ENABLE) ||
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(REG_READ(PIPECCONF) & PIPEACONF_ENABLE))
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return false;
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if ((REG_READ(DSPACNTR) & DISPLAY_PLANE_ENABLE) ||
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(REG_READ(DSPCCNTR) & DISPLAY_PLANE_ENABLE))
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return false;
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return true;
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}
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/* Periodically update dbi panel */
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void mdfld_dbi_update_panel(struct drm_device *dev, int pipe)
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{
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struct drm_psb_private *dev_priv = dev->dev_private;
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struct mdfld_dbi_dsr_info *dsr_info = dev_priv->dbi_dsr_info;
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struct mdfld_dsi_dbi_output **dbi_outputs;
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struct mdfld_dsi_dbi_output *dbi_output;
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int i;
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int can_enter_dsr = 0;
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u32 damage_mask;
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dbi_outputs = dsr_info->dbi_outputs;
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dbi_output = pipe ? dbi_outputs[1] : dbi_outputs[0];
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if (!dbi_output)
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return;
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if (pipe == 0)
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damage_mask = dev_priv->dsr_fb_update & MDFLD_DSR_DAMAGE_MASK_0;
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else if (pipe == 2)
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damage_mask = dev_priv->dsr_fb_update & MDFLD_DSR_DAMAGE_MASK_2;
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else
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return;
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/* If FB is damaged and panel is on update on-panel FB */
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if (damage_mask && dbi_output->dbi_panel_on) {
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dbi_output->dsr_fb_update_done = false;
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if (dbi_output->p_funcs->update_fb)
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dbi_output->p_funcs->update_fb(dbi_output, pipe);
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if (dev_priv->dsr_enable && dbi_output->dsr_fb_update_done)
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dev_priv->dsr_fb_update &= ~damage_mask;
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/*clean IN_DSR flag*/
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dbi_output->mode_flags &= ~MODE_SETTING_IN_DSR;
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dbi_output->dsr_idle_count = 0;
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} else {
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dbi_output->dsr_idle_count++;
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}
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switch (dsr_info->dbi_output_num) {
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case 1:
|
|
if (dbi_output->dsr_idle_count > MDFLD_DSR_MAX_IDLE_COUNT)
|
|
can_enter_dsr = 1;
|
|
break;
|
|
case 2:
|
|
if (dbi_outputs[0]->dsr_idle_count > MDFLD_DSR_MAX_IDLE_COUNT
|
|
&& dbi_outputs[1]->dsr_idle_count > MDFLD_DSR_MAX_IDLE_COUNT)
|
|
can_enter_dsr = 1;
|
|
break;
|
|
default:
|
|
DRM_ERROR("Wrong DBI output number\n");
|
|
}
|
|
|
|
/* Try to enter DSR */
|
|
if (can_enter_dsr) {
|
|
for (i = 0; i < dsr_info->dbi_output_num; i++) {
|
|
if (!mdfld_dbi_is_in_dsr(dev) && dbi_outputs[i] &&
|
|
!(dbi_outputs[i]->mode_flags & MODE_SETTING_ON_GOING)) {
|
|
mdfld_dsi_dbi_enter_dsr(dbi_outputs[i],
|
|
dbi_outputs[i]->channel_num ? 2 : 0);
|
|
#if 0
|
|
enter_dsr = 1;
|
|
pr_err("%s: enter_dsr = 1\n", __func__);
|
|
#endif
|
|
}
|
|
}
|
|
/*schedule rpm suspend after gfxrtdelay*/
|
|
#ifdef CONFIG_GFX_RTPM
|
|
if (!dev_priv->rpm_enabled
|
|
|| !enter_dsr
|
|
/* || (REG_READ(HDMIB_CONTROL) & HDMIB_PORT_EN) */
|
|
|| pm_schedule_suspend(&dev->pdev->dev, gfxrtdelay))
|
|
dev_warn(dev->dev,
|
|
"Runtime PM schedule suspend failed, rpm %d\n",
|
|
dev_priv->rpm_enabled);
|
|
#endif
|
|
}
|
|
}
|
|
|
|
int mdfld_dbi_dsr_init(struct drm_device *dev)
|
|
{
|
|
struct drm_psb_private *dev_priv = dev->dev_private;
|
|
struct mdfld_dbi_dsr_info *dsr_info = dev_priv->dbi_dsr_info;
|
|
|
|
if (!dsr_info || IS_ERR(dsr_info)) {
|
|
dsr_info = kzalloc(sizeof(struct mdfld_dbi_dsr_info),
|
|
GFP_KERNEL);
|
|
if (!dsr_info) {
|
|
dev_err(dev->dev, "No memory\n");
|
|
return -ENOMEM;
|
|
}
|
|
dev_priv->dbi_dsr_info = dsr_info;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
void mdfld_dbi_dsr_exit(struct drm_device *dev)
|
|
{
|
|
struct drm_psb_private *dev_priv = dev->dev_private;
|
|
struct mdfld_dbi_dsr_info *dsr_info = dev_priv->dbi_dsr_info;
|
|
|
|
if (dsr_info) {
|
|
kfree(dsr_info);
|
|
dev_priv->dbi_dsr_info = NULL;
|
|
}
|
|
}
|
|
|
|
void mdfld_dsi_controller_dbi_init(struct mdfld_dsi_config *dsi_config,
|
|
int pipe)
|
|
{
|
|
struct drm_device *dev = dsi_config->dev;
|
|
u32 reg_offset = pipe ? MIPIC_REG_OFFSET : 0;
|
|
int lane_count = dsi_config->lane_count;
|
|
u32 val = 0;
|
|
|
|
dev_dbg(dev->dev, "Init DBI interface on pipe %d...\n", pipe);
|
|
|
|
/* Un-ready device */
|
|
REG_WRITE((MIPIA_DEVICE_READY_REG + reg_offset), 0x00000000);
|
|
|
|
/* Init dsi adapter before kicking off */
|
|
REG_WRITE((MIPIA_CONTROL_REG + reg_offset), 0x00000018);
|
|
|
|
/* TODO: figure out how to setup these registers */
|
|
REG_WRITE((MIPIA_DPHY_PARAM_REG + reg_offset), 0x150c3408);
|
|
REG_WRITE((MIPIA_CLK_LANE_SWITCH_TIME_CNT_REG + reg_offset),
|
|
0x000a0014);
|
|
REG_WRITE((MIPIA_DBI_BW_CTRL_REG + reg_offset), 0x00000400);
|
|
REG_WRITE((MIPIA_DBI_FIFO_THROTTLE_REG + reg_offset), 0x00000001);
|
|
REG_WRITE((MIPIA_HS_LS_DBI_ENABLE_REG + reg_offset), 0x00000000);
|
|
|
|
/* Enable all interrupts */
|
|
REG_WRITE((MIPIA_INTR_EN_REG + reg_offset), 0xffffffff);
|
|
/* Max value: 20 clock cycles of txclkesc */
|
|
REG_WRITE((MIPIA_TURN_AROUND_TIMEOUT_REG + reg_offset), 0x0000001f);
|
|
/* Min 21 txclkesc, max: ffffh */
|
|
REG_WRITE((MIPIA_DEVICE_RESET_TIMER_REG + reg_offset), 0x0000ffff);
|
|
/* Min: 7d0 max: 4e20 */
|
|
REG_WRITE((MIPIA_INIT_COUNT_REG + reg_offset), 0x00000fa0);
|
|
|
|
/* Set up func_prg */
|
|
val |= lane_count;
|
|
val |= (dsi_config->channel_num << DSI_DBI_VIRT_CHANNEL_OFFSET);
|
|
val |= DSI_DBI_COLOR_FORMAT_OPTION2;
|
|
REG_WRITE((MIPIA_DSI_FUNC_PRG_REG + reg_offset), val);
|
|
|
|
REG_WRITE((MIPIA_HS_TX_TIMEOUT_REG + reg_offset), 0x3fffff);
|
|
REG_WRITE((MIPIA_LP_RX_TIMEOUT_REG + reg_offset), 0xffff);
|
|
|
|
/* De-assert dbi_stall when half of DBI FIFO is empty */
|
|
/* REG_WRITE((MIPIA_DBI_FIFO_THROTTLE_REG + reg_offset), 0x00000000); */
|
|
|
|
REG_WRITE((MIPIA_HIGH_LOW_SWITCH_COUNT_REG + reg_offset), 0x46);
|
|
REG_WRITE((MIPIA_EOT_DISABLE_REG + reg_offset), 0x00000000);
|
|
REG_WRITE((MIPIA_LP_BYTECLK_REG + reg_offset), 0x00000004);
|
|
REG_WRITE((MIPIA_DEVICE_READY_REG + reg_offset), 0x00000001);
|
|
}
|
|
|
|
#if 0
|
|
/*DBI encoder helper funcs*/
|
|
static const struct drm_encoder_helper_funcs mdfld_dsi_dbi_helper_funcs = {
|
|
.dpms = mdfld_dsi_dbi_dpms,
|
|
.mode_fixup = mdfld_dsi_dbi_mode_fixup,
|
|
.prepare = mdfld_dsi_dbi_prepare,
|
|
.mode_set = mdfld_dsi_dbi_mode_set,
|
|
.commit = mdfld_dsi_dbi_commit,
|
|
};
|
|
|
|
/*DBI encoder funcs*/
|
|
static const struct drm_encoder_funcs mdfld_dsi_dbi_encoder_funcs = {
|
|
.destroy = drm_encoder_cleanup,
|
|
};
|
|
|
|
#endif
|
|
|
|
/*
|
|
* Init DSI DBI encoder.
|
|
* Allocate an mdfld_dsi_encoder and attach it to given @dsi_connector
|
|
* return pointer of newly allocated DBI encoder, NULL on error
|
|
*/
|
|
struct mdfld_dsi_encoder *mdfld_dsi_dbi_init(struct drm_device *dev,
|
|
struct mdfld_dsi_connector *dsi_connector,
|
|
struct panel_funcs *p_funcs)
|
|
{
|
|
struct drm_psb_private *dev_priv = dev->dev_private;
|
|
struct mdfld_dsi_dbi_output *dbi_output = NULL;
|
|
struct mdfld_dsi_config *dsi_config;
|
|
struct drm_connector *connector = NULL;
|
|
struct drm_encoder *encoder = NULL;
|
|
struct drm_display_mode *fixed_mode = NULL;
|
|
struct psb_gtt *pg = dev_priv ? (&dev_priv->gtt) : NULL;
|
|
struct mdfld_dbi_dpu_info *dpu_info = dev_priv ? (dev_priv->dbi_dpu_info) : NULL;
|
|
struct mdfld_dbi_dsr_info *dsr_info = dev_priv ? (dev_priv->dbi_dsr_info) : NULL;
|
|
u32 data = 0;
|
|
int pipe;
|
|
int ret;
|
|
|
|
if (!pg || !dsi_connector || !p_funcs) {
|
|
WARN_ON(1);
|
|
return NULL;
|
|
}
|
|
|
|
dsi_config = mdfld_dsi_get_config(dsi_connector);
|
|
pipe = dsi_connector->pipe;
|
|
|
|
/*panel hard-reset*/
|
|
if (p_funcs->reset) {
|
|
ret = p_funcs->reset(pipe);
|
|
if (ret) {
|
|
DRM_ERROR("Panel %d hard-reset failed\n", pipe);
|
|
return NULL;
|
|
}
|
|
}
|
|
/* Panel drvIC init */
|
|
if (p_funcs->drv_ic_init)
|
|
p_funcs->drv_ic_init(dsi_config, pipe);
|
|
|
|
/* Panel power mode detect */
|
|
ret = mdfld_dsi_get_power_mode(dsi_config,
|
|
&data,
|
|
MDFLD_DSI_HS_TRANSMISSION);
|
|
if (ret) {
|
|
DRM_ERROR("Panel %d get power mode failed\n", pipe);
|
|
dsi_connector->status = connector_status_disconnected;
|
|
} else {
|
|
DRM_INFO("pipe %d power mode 0x%x\n", pipe, data);
|
|
dsi_connector->status = connector_status_connected;
|
|
}
|
|
|
|
/*TODO: get panel info from DDB*/
|
|
|
|
dbi_output = kzalloc(sizeof(struct mdfld_dsi_dbi_output), GFP_KERNEL);
|
|
if (!dbi_output) {
|
|
dev_err(dev->dev, "No memory\n");
|
|
return NULL;
|
|
}
|
|
|
|
if (dsi_connector->pipe == 0) {
|
|
dbi_output->channel_num = 0;
|
|
dev_priv->dbi_output = dbi_output;
|
|
} else if (dsi_connector->pipe == 2) {
|
|
dbi_output->channel_num = 1;
|
|
dev_priv->dbi_output2 = dbi_output;
|
|
} else {
|
|
dev_err(dev->dev, "only support 2 DSI outputs\n");
|
|
goto out_err1;
|
|
}
|
|
|
|
dbi_output->dev = dev;
|
|
dbi_output->p_funcs = p_funcs;
|
|
fixed_mode = dsi_config->fixed_mode;
|
|
dbi_output->panel_fixed_mode = fixed_mode;
|
|
|
|
/* Create drm encoder object */
|
|
connector = &dsi_connector->base.base;
|
|
encoder = &dbi_output->base.base;
|
|
/* Review this if we ever get MIPI-HDMI bridges or similar */
|
|
drm_encoder_init(dev,
|
|
encoder,
|
|
p_funcs->encoder_funcs,
|
|
DRM_MODE_ENCODER_LVDS);
|
|
drm_encoder_helper_add(encoder, p_funcs->encoder_helper_funcs);
|
|
|
|
/* Attach to given connector */
|
|
drm_mode_connector_attach_encoder(connector, encoder);
|
|
|
|
/* Set possible CRTCs and clones */
|
|
if (dsi_connector->pipe) {
|
|
encoder->possible_crtcs = (1 << 2);
|
|
encoder->possible_clones = (1 << 1);
|
|
} else {
|
|
encoder->possible_crtcs = (1 << 0);
|
|
encoder->possible_clones = (1 << 0);
|
|
}
|
|
|
|
dev_priv->dsr_fb_update = 0;
|
|
dev_priv->dsr_enable = false;
|
|
dev_priv->exit_idle = mdfld_dsi_dbi_exit_dsr;
|
|
|
|
dbi_output->first_boot = true;
|
|
dbi_output->mode_flags = MODE_SETTING_IN_ENCODER;
|
|
|
|
/* Add this output to dpu_info if in DPU mode */
|
|
if (dpu_info && dsi_connector->status == connector_status_connected) {
|
|
if (dsi_connector->pipe == 0)
|
|
dpu_info->dbi_outputs[0] = dbi_output;
|
|
else
|
|
dpu_info->dbi_outputs[1] = dbi_output;
|
|
|
|
dpu_info->dbi_output_num++;
|
|
} else if (dsi_connector->status == connector_status_connected) {
|
|
/* Add this output to dsr_info if not */
|
|
if (dsi_connector->pipe == 0)
|
|
dsr_info->dbi_outputs[0] = dbi_output;
|
|
else
|
|
dsr_info->dbi_outputs[1] = dbi_output;
|
|
|
|
dsr_info->dbi_output_num++;
|
|
}
|
|
return &dbi_output->base;
|
|
out_err1:
|
|
kfree(dbi_output);
|
|
return NULL;
|
|
}
|