![Matthew Wilcox](/assets/img/avatar_default.png)
We had assumed that SAL firmware would return an error if it didn't understand extended config space. Unfortunately, the SAL on the SGI 750 doesn't do that, it panics the machine. So, condition the extended PCI config space accesses on SAL revision 3.2. Signed-off-by: Matthew Wilcox <willy@linux.intel.com> Tested-by: Brad Spengler <spender@grsecurity.net> Signed-off-by: Tony Luck <tony.luck@intel.com>
790 lines
19 KiB
C
790 lines
19 KiB
C
/*
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* pci.c - Low-Level PCI Access in IA-64
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*
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* Derived from bios32.c of i386 tree.
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*
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* (c) Copyright 2002, 2005 Hewlett-Packard Development Company, L.P.
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* David Mosberger-Tang <davidm@hpl.hp.com>
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* Bjorn Helgaas <bjorn.helgaas@hp.com>
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* Copyright (C) 2004 Silicon Graphics, Inc.
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*
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* Note: Above list of copyright holders is incomplete...
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*/
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#include <linux/acpi.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/bootmem.h>
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#include <asm/machvec.h>
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#include <asm/page.h>
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#include <asm/system.h>
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#include <asm/io.h>
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#include <asm/sal.h>
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#include <asm/smp.h>
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#include <asm/irq.h>
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#include <asm/hw_irq.h>
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/*
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* Low-level SAL-based PCI configuration access functions. Note that SAL
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* calls are already serialized (via sal_lock), so we don't need another
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* synchronization mechanism here.
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*/
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#define PCI_SAL_ADDRESS(seg, bus, devfn, reg) \
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(((u64) seg << 24) | (bus << 16) | (devfn << 8) | (reg))
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/* SAL 3.2 adds support for extended config space. */
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#define PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg) \
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(((u64) seg << 28) | (bus << 20) | (devfn << 12) | (reg))
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int raw_pci_read(unsigned int seg, unsigned int bus, unsigned int devfn,
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int reg, int len, u32 *value)
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{
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u64 addr, data = 0;
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int mode, result;
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if (!value || (seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095))
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return -EINVAL;
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if ((seg | reg) <= 255) {
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addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg);
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mode = 0;
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} else if (sal_revision >= SAL_VERSION_CODE(3,2)) {
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addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg);
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mode = 1;
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} else {
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return -EINVAL;
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}
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result = ia64_sal_pci_config_read(addr, mode, len, &data);
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if (result != 0)
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return -EINVAL;
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*value = (u32) data;
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return 0;
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}
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int raw_pci_write(unsigned int seg, unsigned int bus, unsigned int devfn,
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int reg, int len, u32 value)
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{
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u64 addr;
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int mode, result;
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if ((seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095))
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return -EINVAL;
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if ((seg | reg) <= 255) {
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addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg);
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mode = 0;
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} else if (sal_revision >= SAL_VERSION_CODE(3,2)) {
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addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg);
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mode = 1;
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} else {
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return -EINVAL;
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}
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result = ia64_sal_pci_config_write(addr, mode, len, value);
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if (result != 0)
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return -EINVAL;
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return 0;
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}
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static int pci_read(struct pci_bus *bus, unsigned int devfn, int where,
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int size, u32 *value)
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{
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return raw_pci_read(pci_domain_nr(bus), bus->number,
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devfn, where, size, value);
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}
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static int pci_write(struct pci_bus *bus, unsigned int devfn, int where,
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int size, u32 value)
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{
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return raw_pci_write(pci_domain_nr(bus), bus->number,
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devfn, where, size, value);
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}
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struct pci_ops pci_root_ops = {
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.read = pci_read,
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.write = pci_write,
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};
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/* Called by ACPI when it finds a new root bus. */
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static struct pci_controller * __devinit
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alloc_pci_controller (int seg)
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{
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struct pci_controller *controller;
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controller = kzalloc(sizeof(*controller), GFP_KERNEL);
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if (!controller)
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return NULL;
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controller->segment = seg;
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controller->node = -1;
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return controller;
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}
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struct pci_root_info {
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struct pci_controller *controller;
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char *name;
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};
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static unsigned int
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new_space (u64 phys_base, int sparse)
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{
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u64 mmio_base;
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int i;
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if (phys_base == 0)
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return 0; /* legacy I/O port space */
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mmio_base = (u64) ioremap(phys_base, 0);
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for (i = 0; i < num_io_spaces; i++)
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if (io_space[i].mmio_base == mmio_base &&
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io_space[i].sparse == sparse)
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return i;
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if (num_io_spaces == MAX_IO_SPACES) {
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printk(KERN_ERR "PCI: Too many IO port spaces "
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"(MAX_IO_SPACES=%lu)\n", MAX_IO_SPACES);
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return ~0;
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}
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i = num_io_spaces++;
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io_space[i].mmio_base = mmio_base;
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io_space[i].sparse = sparse;
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return i;
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}
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static u64 __devinit
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add_io_space (struct pci_root_info *info, struct acpi_resource_address64 *addr)
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{
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struct resource *resource;
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char *name;
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unsigned long base, min, max, base_port;
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unsigned int sparse = 0, space_nr, len;
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resource = kzalloc(sizeof(*resource), GFP_KERNEL);
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if (!resource) {
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printk(KERN_ERR "PCI: No memory for %s I/O port space\n",
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info->name);
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goto out;
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}
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len = strlen(info->name) + 32;
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name = kzalloc(len, GFP_KERNEL);
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if (!name) {
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printk(KERN_ERR "PCI: No memory for %s I/O port space name\n",
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info->name);
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goto free_resource;
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}
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min = addr->minimum;
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max = min + addr->address_length - 1;
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if (addr->info.io.translation_type == ACPI_SPARSE_TRANSLATION)
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sparse = 1;
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space_nr = new_space(addr->translation_offset, sparse);
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if (space_nr == ~0)
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goto free_name;
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base = __pa(io_space[space_nr].mmio_base);
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base_port = IO_SPACE_BASE(space_nr);
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snprintf(name, len, "%s I/O Ports %08lx-%08lx", info->name,
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base_port + min, base_port + max);
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/*
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* The SDM guarantees the legacy 0-64K space is sparse, but if the
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* mapping is done by the processor (not the bridge), ACPI may not
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* mark it as sparse.
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*/
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if (space_nr == 0)
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sparse = 1;
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resource->name = name;
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resource->flags = IORESOURCE_MEM;
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resource->start = base + (sparse ? IO_SPACE_SPARSE_ENCODING(min) : min);
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resource->end = base + (sparse ? IO_SPACE_SPARSE_ENCODING(max) : max);
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insert_resource(&iomem_resource, resource);
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return base_port;
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free_name:
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kfree(name);
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free_resource:
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kfree(resource);
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out:
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return ~0;
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}
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static acpi_status __devinit resource_to_window(struct acpi_resource *resource,
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struct acpi_resource_address64 *addr)
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{
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acpi_status status;
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/*
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* We're only interested in _CRS descriptors that are
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* - address space descriptors for memory or I/O space
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* - non-zero size
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* - producers, i.e., the address space is routed downstream,
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* not consumed by the bridge itself
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*/
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status = acpi_resource_to_address64(resource, addr);
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if (ACPI_SUCCESS(status) &&
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(addr->resource_type == ACPI_MEMORY_RANGE ||
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addr->resource_type == ACPI_IO_RANGE) &&
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addr->address_length &&
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addr->producer_consumer == ACPI_PRODUCER)
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return AE_OK;
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return AE_ERROR;
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}
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static acpi_status __devinit
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count_window (struct acpi_resource *resource, void *data)
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{
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unsigned int *windows = (unsigned int *) data;
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struct acpi_resource_address64 addr;
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acpi_status status;
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status = resource_to_window(resource, &addr);
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if (ACPI_SUCCESS(status))
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(*windows)++;
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return AE_OK;
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}
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static __devinit acpi_status add_window(struct acpi_resource *res, void *data)
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{
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struct pci_root_info *info = data;
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struct pci_window *window;
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struct acpi_resource_address64 addr;
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acpi_status status;
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unsigned long flags, offset = 0;
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struct resource *root;
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/* Return AE_OK for non-window resources to keep scanning for more */
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status = resource_to_window(res, &addr);
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if (!ACPI_SUCCESS(status))
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return AE_OK;
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if (addr.resource_type == ACPI_MEMORY_RANGE) {
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flags = IORESOURCE_MEM;
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root = &iomem_resource;
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offset = addr.translation_offset;
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} else if (addr.resource_type == ACPI_IO_RANGE) {
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flags = IORESOURCE_IO;
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root = &ioport_resource;
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offset = add_io_space(info, &addr);
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if (offset == ~0)
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return AE_OK;
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} else
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return AE_OK;
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window = &info->controller->window[info->controller->windows++];
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window->resource.name = info->name;
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window->resource.flags = flags;
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window->resource.start = addr.minimum + offset;
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window->resource.end = window->resource.start + addr.address_length - 1;
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window->resource.child = NULL;
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window->offset = offset;
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if (insert_resource(root, &window->resource)) {
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printk(KERN_ERR "alloc 0x%llx-0x%llx from %s for %s failed\n",
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window->resource.start, window->resource.end,
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root->name, info->name);
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}
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return AE_OK;
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}
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static void __devinit
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pcibios_setup_root_windows(struct pci_bus *bus, struct pci_controller *ctrl)
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{
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int i, j;
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j = 0;
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for (i = 0; i < ctrl->windows; i++) {
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struct resource *res = &ctrl->window[i].resource;
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/* HP's firmware has a hack to work around a Windows bug.
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* Ignore these tiny memory ranges */
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if ((res->flags & IORESOURCE_MEM) &&
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(res->end - res->start < 16))
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continue;
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if (j >= PCI_BUS_NUM_RESOURCES) {
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printk("Ignoring range [%#llx-%#llx] (%lx)\n",
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res->start, res->end, res->flags);
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continue;
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}
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bus->resource[j++] = res;
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}
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}
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struct pci_bus * __devinit
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pci_acpi_scan_root(struct acpi_device *device, int domain, int bus)
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{
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struct pci_controller *controller;
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unsigned int windows = 0;
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struct pci_bus *pbus;
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char *name;
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int pxm;
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controller = alloc_pci_controller(domain);
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if (!controller)
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goto out1;
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controller->acpi_handle = device->handle;
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pxm = acpi_get_pxm(controller->acpi_handle);
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#ifdef CONFIG_NUMA
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if (pxm >= 0)
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controller->node = pxm_to_node(pxm);
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#endif
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acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_window,
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&windows);
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if (windows) {
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struct pci_root_info info;
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controller->window =
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kmalloc_node(sizeof(*controller->window) * windows,
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GFP_KERNEL, controller->node);
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if (!controller->window)
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goto out2;
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name = kmalloc(16, GFP_KERNEL);
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if (!name)
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goto out3;
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sprintf(name, "PCI Bus %04x:%02x", domain, bus);
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info.controller = controller;
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info.name = name;
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acpi_walk_resources(device->handle, METHOD_NAME__CRS,
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add_window, &info);
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}
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/*
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* See arch/x86/pci/acpi.c.
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* The desired pci bus might already be scanned in a quirk. We
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* should handle the case here, but it appears that IA64 hasn't
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* such quirk. So we just ignore the case now.
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*/
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pbus = pci_scan_bus_parented(NULL, bus, &pci_root_ops, controller);
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return pbus;
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out3:
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kfree(controller->window);
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out2:
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kfree(controller);
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out1:
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return NULL;
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}
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void pcibios_resource_to_bus(struct pci_dev *dev,
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struct pci_bus_region *region, struct resource *res)
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{
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struct pci_controller *controller = PCI_CONTROLLER(dev);
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unsigned long offset = 0;
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int i;
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for (i = 0; i < controller->windows; i++) {
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struct pci_window *window = &controller->window[i];
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if (!(window->resource.flags & res->flags))
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continue;
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if (window->resource.start > res->start)
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continue;
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if (window->resource.end < res->end)
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continue;
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offset = window->offset;
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break;
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}
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region->start = res->start - offset;
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region->end = res->end - offset;
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}
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EXPORT_SYMBOL(pcibios_resource_to_bus);
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void pcibios_bus_to_resource(struct pci_dev *dev,
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struct resource *res, struct pci_bus_region *region)
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{
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struct pci_controller *controller = PCI_CONTROLLER(dev);
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unsigned long offset = 0;
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int i;
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for (i = 0; i < controller->windows; i++) {
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struct pci_window *window = &controller->window[i];
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if (!(window->resource.flags & res->flags))
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continue;
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if (window->resource.start - window->offset > region->start)
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continue;
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if (window->resource.end - window->offset < region->end)
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continue;
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offset = window->offset;
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break;
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}
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res->start = region->start + offset;
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res->end = region->end + offset;
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}
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EXPORT_SYMBOL(pcibios_bus_to_resource);
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static int __devinit is_valid_resource(struct pci_dev *dev, int idx)
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{
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unsigned int i, type_mask = IORESOURCE_IO | IORESOURCE_MEM;
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struct resource *devr = &dev->resource[idx];
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if (!dev->bus)
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return 0;
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for (i=0; i<PCI_BUS_NUM_RESOURCES; i++) {
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struct resource *busr = dev->bus->resource[i];
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if (!busr || ((busr->flags ^ devr->flags) & type_mask))
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continue;
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if ((devr->start) && (devr->start >= busr->start) &&
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(devr->end <= busr->end))
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return 1;
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}
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return 0;
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}
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static void __devinit
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pcibios_fixup_resources(struct pci_dev *dev, int start, int limit)
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{
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struct pci_bus_region region;
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int i;
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for (i = start; i < limit; i++) {
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if (!dev->resource[i].flags)
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continue;
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region.start = dev->resource[i].start;
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region.end = dev->resource[i].end;
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pcibios_bus_to_resource(dev, &dev->resource[i], ®ion);
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if ((is_valid_resource(dev, i)))
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pci_claim_resource(dev, i);
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}
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}
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void __devinit pcibios_fixup_device_resources(struct pci_dev *dev)
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{
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pcibios_fixup_resources(dev, 0, PCI_BRIDGE_RESOURCES);
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}
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EXPORT_SYMBOL_GPL(pcibios_fixup_device_resources);
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static void __devinit pcibios_fixup_bridge_resources(struct pci_dev *dev)
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{
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pcibios_fixup_resources(dev, PCI_BRIDGE_RESOURCES, PCI_NUM_RESOURCES);
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}
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/*
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* Called after each bus is probed, but before its children are examined.
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*/
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void __devinit
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pcibios_fixup_bus (struct pci_bus *b)
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{
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struct pci_dev *dev;
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if (b->self) {
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pci_read_bridge_bases(b);
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pcibios_fixup_bridge_resources(b->self);
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} else {
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pcibios_setup_root_windows(b, b->sysdata);
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}
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list_for_each_entry(dev, &b->devices, bus_list)
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pcibios_fixup_device_resources(dev);
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platform_pci_fixup_bus(b);
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return;
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}
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void __devinit
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pcibios_update_irq (struct pci_dev *dev, int irq)
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{
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pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
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/* ??? FIXME -- record old value for shutdown. */
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}
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int
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pcibios_enable_device (struct pci_dev *dev, int mask)
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{
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int ret;
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ret = pci_enable_resources(dev, mask);
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if (ret < 0)
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return ret;
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|
|
|
if (!dev->msi_enabled)
|
|
return acpi_pci_irq_enable(dev);
|
|
return 0;
|
|
}
|
|
|
|
void
|
|
pcibios_disable_device (struct pci_dev *dev)
|
|
{
|
|
BUG_ON(atomic_read(&dev->enable_cnt));
|
|
if (!dev->msi_enabled)
|
|
acpi_pci_irq_disable(dev);
|
|
}
|
|
|
|
void
|
|
pcibios_align_resource (void *data, struct resource *res,
|
|
resource_size_t size, resource_size_t align)
|
|
{
|
|
}
|
|
|
|
/*
|
|
* PCI BIOS setup, always defaults to SAL interface
|
|
*/
|
|
char * __init
|
|
pcibios_setup (char *str)
|
|
{
|
|
return str;
|
|
}
|
|
|
|
int
|
|
pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma,
|
|
enum pci_mmap_state mmap_state, int write_combine)
|
|
{
|
|
unsigned long size = vma->vm_end - vma->vm_start;
|
|
pgprot_t prot;
|
|
|
|
/*
|
|
* I/O space cannot be accessed via normal processor loads and
|
|
* stores on this platform.
|
|
*/
|
|
if (mmap_state == pci_mmap_io)
|
|
/*
|
|
* XXX we could relax this for I/O spaces for which ACPI
|
|
* indicates that the space is 1-to-1 mapped. But at the
|
|
* moment, we don't support multiple PCI address spaces and
|
|
* the legacy I/O space is not 1-to-1 mapped, so this is moot.
|
|
*/
|
|
return -EINVAL;
|
|
|
|
if (!valid_mmap_phys_addr_range(vma->vm_pgoff, size))
|
|
return -EINVAL;
|
|
|
|
prot = phys_mem_access_prot(NULL, vma->vm_pgoff, size,
|
|
vma->vm_page_prot);
|
|
|
|
/*
|
|
* If the user requested WC, the kernel uses UC or WC for this region,
|
|
* and the chipset supports WC, we can use WC. Otherwise, we have to
|
|
* use the same attribute the kernel uses.
|
|
*/
|
|
if (write_combine &&
|
|
((pgprot_val(prot) & _PAGE_MA_MASK) == _PAGE_MA_UC ||
|
|
(pgprot_val(prot) & _PAGE_MA_MASK) == _PAGE_MA_WC) &&
|
|
efi_range_is_wc(vma->vm_start, vma->vm_end - vma->vm_start))
|
|
vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
|
|
else
|
|
vma->vm_page_prot = prot;
|
|
|
|
if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
|
|
vma->vm_end - vma->vm_start, vma->vm_page_prot))
|
|
return -EAGAIN;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* ia64_pci_get_legacy_mem - generic legacy mem routine
|
|
* @bus: bus to get legacy memory base address for
|
|
*
|
|
* Find the base of legacy memory for @bus. This is typically the first
|
|
* megabyte of bus address space for @bus or is simply 0 on platforms whose
|
|
* chipsets support legacy I/O and memory routing. Returns the base address
|
|
* or an error pointer if an error occurred.
|
|
*
|
|
* This is the ia64 generic version of this routine. Other platforms
|
|
* are free to override it with a machine vector.
|
|
*/
|
|
char *ia64_pci_get_legacy_mem(struct pci_bus *bus)
|
|
{
|
|
return (char *)__IA64_UNCACHED_OFFSET;
|
|
}
|
|
|
|
/**
|
|
* pci_mmap_legacy_page_range - map legacy memory space to userland
|
|
* @bus: bus whose legacy space we're mapping
|
|
* @vma: vma passed in by mmap
|
|
*
|
|
* Map legacy memory space for this device back to userspace using a machine
|
|
* vector to get the base address.
|
|
*/
|
|
int
|
|
pci_mmap_legacy_page_range(struct pci_bus *bus, struct vm_area_struct *vma,
|
|
enum pci_mmap_state mmap_state)
|
|
{
|
|
unsigned long size = vma->vm_end - vma->vm_start;
|
|
pgprot_t prot;
|
|
char *addr;
|
|
|
|
/* We only support mmap'ing of legacy memory space */
|
|
if (mmap_state != pci_mmap_mem)
|
|
return -ENOSYS;
|
|
|
|
/*
|
|
* Avoid attribute aliasing. See Documentation/ia64/aliasing.txt
|
|
* for more details.
|
|
*/
|
|
if (!valid_mmap_phys_addr_range(vma->vm_pgoff, size))
|
|
return -EINVAL;
|
|
prot = phys_mem_access_prot(NULL, vma->vm_pgoff, size,
|
|
vma->vm_page_prot);
|
|
|
|
addr = pci_get_legacy_mem(bus);
|
|
if (IS_ERR(addr))
|
|
return PTR_ERR(addr);
|
|
|
|
vma->vm_pgoff += (unsigned long)addr >> PAGE_SHIFT;
|
|
vma->vm_page_prot = prot;
|
|
|
|
if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
|
|
size, vma->vm_page_prot))
|
|
return -EAGAIN;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* ia64_pci_legacy_read - read from legacy I/O space
|
|
* @bus: bus to read
|
|
* @port: legacy port value
|
|
* @val: caller allocated storage for returned value
|
|
* @size: number of bytes to read
|
|
*
|
|
* Simply reads @size bytes from @port and puts the result in @val.
|
|
*
|
|
* Again, this (and the write routine) are generic versions that can be
|
|
* overridden by the platform. This is necessary on platforms that don't
|
|
* support legacy I/O routing or that hard fail on legacy I/O timeouts.
|
|
*/
|
|
int ia64_pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size)
|
|
{
|
|
int ret = size;
|
|
|
|
switch (size) {
|
|
case 1:
|
|
*val = inb(port);
|
|
break;
|
|
case 2:
|
|
*val = inw(port);
|
|
break;
|
|
case 4:
|
|
*val = inl(port);
|
|
break;
|
|
default:
|
|
ret = -EINVAL;
|
|
break;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* ia64_pci_legacy_write - perform a legacy I/O write
|
|
* @bus: bus pointer
|
|
* @port: port to write
|
|
* @val: value to write
|
|
* @size: number of bytes to write from @val
|
|
*
|
|
* Simply writes @size bytes of @val to @port.
|
|
*/
|
|
int ia64_pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size)
|
|
{
|
|
int ret = size;
|
|
|
|
switch (size) {
|
|
case 1:
|
|
outb(val, port);
|
|
break;
|
|
case 2:
|
|
outw(val, port);
|
|
break;
|
|
case 4:
|
|
outl(val, port);
|
|
break;
|
|
default:
|
|
ret = -EINVAL;
|
|
break;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
/* It's defined in drivers/pci/pci.c */
|
|
extern u8 pci_cache_line_size;
|
|
|
|
/**
|
|
* set_pci_cacheline_size - determine cacheline size for PCI devices
|
|
*
|
|
* We want to use the line-size of the outer-most cache. We assume
|
|
* that this line-size is the same for all CPUs.
|
|
*
|
|
* Code mostly taken from arch/ia64/kernel/palinfo.c:cache_info().
|
|
*/
|
|
static void __init set_pci_cacheline_size(void)
|
|
{
|
|
unsigned long levels, unique_caches;
|
|
long status;
|
|
pal_cache_config_info_t cci;
|
|
|
|
status = ia64_pal_cache_summary(&levels, &unique_caches);
|
|
if (status != 0) {
|
|
printk(KERN_ERR "%s: ia64_pal_cache_summary() failed "
|
|
"(status=%ld)\n", __func__, status);
|
|
return;
|
|
}
|
|
|
|
status = ia64_pal_cache_config_info(levels - 1,
|
|
/* cache_type (data_or_unified)= */ 2, &cci);
|
|
if (status != 0) {
|
|
printk(KERN_ERR "%s: ia64_pal_cache_config_info() failed "
|
|
"(status=%ld)\n", __func__, status);
|
|
return;
|
|
}
|
|
pci_cache_line_size = (1 << cci.pcci_line_size) / 4;
|
|
}
|
|
|
|
u64 ia64_dma_get_required_mask(struct device *dev)
|
|
{
|
|
u32 low_totalram = ((max_pfn - 1) << PAGE_SHIFT);
|
|
u32 high_totalram = ((max_pfn - 1) >> (32 - PAGE_SHIFT));
|
|
u64 mask;
|
|
|
|
if (!high_totalram) {
|
|
/* convert to mask just covering totalram */
|
|
low_totalram = (1 << (fls(low_totalram) - 1));
|
|
low_totalram += low_totalram - 1;
|
|
mask = low_totalram;
|
|
} else {
|
|
high_totalram = (1 << (fls(high_totalram) - 1));
|
|
high_totalram += high_totalram - 1;
|
|
mask = (((u64)high_totalram) << 32) + 0xffffffff;
|
|
}
|
|
return mask;
|
|
}
|
|
EXPORT_SYMBOL_GPL(ia64_dma_get_required_mask);
|
|
|
|
u64 dma_get_required_mask(struct device *dev)
|
|
{
|
|
return platform_dma_get_required_mask(dev);
|
|
}
|
|
EXPORT_SYMBOL_GPL(dma_get_required_mask);
|
|
|
|
static int __init pcibios_init(void)
|
|
{
|
|
set_pci_cacheline_size();
|
|
return 0;
|
|
}
|
|
|
|
subsys_initcall(pcibios_init);
|