![Santosh Shilimkar](/assets/img/avatar_default.png)
This patch removes the unnecessary UART4 platform which is under data is wrong because of this There is a separate platform structure for UART4 Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Reviewed-By: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
651 lines
15 KiB
C
651 lines
15 KiB
C
/*
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* arch/arm/mach-omap2/serial.c
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*
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* OMAP2 serial support.
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*
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* Copyright (C) 2005-2008 Nokia Corporation
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* Author: Paul Mundt <paul.mundt@nokia.com>
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*
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* Major rework for PM support by Kevin Hilman
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*
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* Based off of arch/arm/mach-omap/omap1/serial.c
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*
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* Copyright (C) 2009 Texas Instruments
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* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/serial_8250.h>
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#include <linux/serial_reg.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <mach/common.h>
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#include <mach/board.h>
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#include <mach/clock.h>
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#include <mach/control.h>
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#include "prm.h"
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#include "pm.h"
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#include "prm-regbits-34xx.h"
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#define UART_OMAP_WER 0x17 /* Wake-up enable register */
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#define DEFAULT_TIMEOUT (5 * HZ)
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struct omap_uart_state {
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int num;
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int can_sleep;
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struct timer_list timer;
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u32 timeout;
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void __iomem *wk_st;
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void __iomem *wk_en;
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u32 wk_mask;
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u32 padconf;
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struct clk *ick;
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struct clk *fck;
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int clocked;
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struct plat_serial8250_port *p;
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struct list_head node;
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struct platform_device pdev;
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#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
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int context_valid;
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/* Registers to be saved/restored for OFF-mode */
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u16 dll;
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u16 dlh;
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u16 ier;
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u16 sysc;
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u16 scr;
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u16 wer;
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#endif
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};
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static LIST_HEAD(uart_list);
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static struct plat_serial8250_port serial_platform_data0[] = {
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{
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.membase = OMAP2_IO_ADDRESS(OMAP_UART1_BASE),
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.mapbase = OMAP_UART1_BASE,
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.irq = 72,
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.flags = UPF_BOOT_AUTOCONF,
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.iotype = UPIO_MEM,
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.regshift = 2,
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.uartclk = OMAP24XX_BASE_BAUD * 16,
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}, {
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.flags = 0
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}
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};
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static struct plat_serial8250_port serial_platform_data1[] = {
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{
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.membase = OMAP2_IO_ADDRESS(OMAP_UART2_BASE),
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.mapbase = OMAP_UART2_BASE,
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.irq = 73,
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.flags = UPF_BOOT_AUTOCONF,
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.iotype = UPIO_MEM,
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.regshift = 2,
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.uartclk = OMAP24XX_BASE_BAUD * 16,
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}, {
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.flags = 0
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}
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};
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static struct plat_serial8250_port serial_platform_data2[] = {
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{
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.membase = OMAP2_IO_ADDRESS(OMAP_UART3_BASE),
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.mapbase = OMAP_UART3_BASE,
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.irq = 74,
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.flags = UPF_BOOT_AUTOCONF,
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.iotype = UPIO_MEM,
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.regshift = 2,
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.uartclk = OMAP24XX_BASE_BAUD * 16,
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}, {
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.flags = 0
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}
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};
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#ifdef CONFIG_ARCH_OMAP4
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static struct plat_serial8250_port serial_platform_data3[] = {
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{
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.membase = OMAP2_IO_ADDRESS(OMAP_UART4_BASE),
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.mapbase = OMAP_UART4_BASE,
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.irq = 70,
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.flags = UPF_BOOT_AUTOCONF,
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.iotype = UPIO_MEM,
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.regshift = 2,
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.uartclk = OMAP24XX_BASE_BAUD * 16,
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}, {
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.flags = 0
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}
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};
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#endif
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static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
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int offset)
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{
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offset <<= up->regshift;
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return (unsigned int)__raw_readb(up->membase + offset);
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}
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static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
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int value)
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{
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offset <<= p->regshift;
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__raw_writeb(value, p->membase + offset);
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}
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/*
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* Internal UARTs need to be initialized for the 8250 autoconfig to work
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* properly. Note that the TX watermark initialization may not be needed
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* once the 8250.c watermark handling code is merged.
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*/
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static inline void __init omap_uart_reset(struct omap_uart_state *uart)
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{
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struct plat_serial8250_port *p = uart->p;
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serial_write_reg(p, UART_OMAP_MDR1, 0x07);
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serial_write_reg(p, UART_OMAP_SCR, 0x08);
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serial_write_reg(p, UART_OMAP_MDR1, 0x00);
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serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0));
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}
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#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
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static int enable_off_mode; /* to be removed by full off-mode patches */
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static void omap_uart_save_context(struct omap_uart_state *uart)
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{
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u16 lcr = 0;
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struct plat_serial8250_port *p = uart->p;
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if (!enable_off_mode)
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return;
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lcr = serial_read_reg(p, UART_LCR);
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serial_write_reg(p, UART_LCR, 0xBF);
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uart->dll = serial_read_reg(p, UART_DLL);
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uart->dlh = serial_read_reg(p, UART_DLM);
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serial_write_reg(p, UART_LCR, lcr);
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uart->ier = serial_read_reg(p, UART_IER);
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uart->sysc = serial_read_reg(p, UART_OMAP_SYSC);
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uart->scr = serial_read_reg(p, UART_OMAP_SCR);
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uart->wer = serial_read_reg(p, UART_OMAP_WER);
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uart->context_valid = 1;
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}
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static void omap_uart_restore_context(struct omap_uart_state *uart)
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{
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u16 efr = 0;
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struct plat_serial8250_port *p = uart->p;
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if (!enable_off_mode)
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return;
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if (!uart->context_valid)
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return;
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uart->context_valid = 0;
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serial_write_reg(p, UART_OMAP_MDR1, 0x7);
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serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
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efr = serial_read_reg(p, UART_EFR);
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serial_write_reg(p, UART_EFR, UART_EFR_ECB);
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serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
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serial_write_reg(p, UART_IER, 0x0);
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serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
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serial_write_reg(p, UART_DLL, uart->dll);
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serial_write_reg(p, UART_DLM, uart->dlh);
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serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
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serial_write_reg(p, UART_IER, uart->ier);
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serial_write_reg(p, UART_FCR, 0xA1);
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serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
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serial_write_reg(p, UART_EFR, efr);
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serial_write_reg(p, UART_LCR, UART_LCR_WLEN8);
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serial_write_reg(p, UART_OMAP_SCR, uart->scr);
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serial_write_reg(p, UART_OMAP_WER, uart->wer);
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serial_write_reg(p, UART_OMAP_SYSC, uart->sysc);
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serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */
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}
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#else
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static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
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static inline void omap_uart_restore_context(struct omap_uart_state *uart) {}
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#endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */
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static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
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{
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if (uart->clocked)
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return;
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clk_enable(uart->ick);
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clk_enable(uart->fck);
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uart->clocked = 1;
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omap_uart_restore_context(uart);
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}
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#ifdef CONFIG_PM
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static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
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{
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if (!uart->clocked)
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return;
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omap_uart_save_context(uart);
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uart->clocked = 0;
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clk_disable(uart->ick);
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clk_disable(uart->fck);
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}
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static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
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{
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/* Set wake-enable bit */
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if (uart->wk_en && uart->wk_mask) {
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u32 v = __raw_readl(uart->wk_en);
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v |= uart->wk_mask;
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__raw_writel(v, uart->wk_en);
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}
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/* Ensure IOPAD wake-enables are set */
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if (cpu_is_omap34xx() && uart->padconf) {
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u16 v = omap_ctrl_readw(uart->padconf);
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v |= OMAP3_PADCONF_WAKEUPENABLE0;
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omap_ctrl_writew(v, uart->padconf);
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}
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}
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static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
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{
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/* Clear wake-enable bit */
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if (uart->wk_en && uart->wk_mask) {
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u32 v = __raw_readl(uart->wk_en);
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v &= ~uart->wk_mask;
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__raw_writel(v, uart->wk_en);
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}
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/* Ensure IOPAD wake-enables are cleared */
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if (cpu_is_omap34xx() && uart->padconf) {
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u16 v = omap_ctrl_readw(uart->padconf);
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v &= ~OMAP3_PADCONF_WAKEUPENABLE0;
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omap_ctrl_writew(v, uart->padconf);
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}
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}
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static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
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int enable)
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{
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struct plat_serial8250_port *p = uart->p;
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u16 sysc;
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sysc = serial_read_reg(p, UART_OMAP_SYSC) & 0x7;
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if (enable)
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sysc |= 0x2 << 3;
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else
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sysc |= 0x1 << 3;
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serial_write_reg(p, UART_OMAP_SYSC, sysc);
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}
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static void omap_uart_block_sleep(struct omap_uart_state *uart)
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{
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omap_uart_enable_clocks(uart);
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omap_uart_smart_idle_enable(uart, 0);
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uart->can_sleep = 0;
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if (uart->timeout)
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mod_timer(&uart->timer, jiffies + uart->timeout);
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else
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del_timer(&uart->timer);
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}
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static void omap_uart_allow_sleep(struct omap_uart_state *uart)
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{
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if (device_may_wakeup(&uart->pdev.dev))
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omap_uart_enable_wakeup(uart);
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else
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omap_uart_disable_wakeup(uart);
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if (!uart->clocked)
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return;
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omap_uart_smart_idle_enable(uart, 1);
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uart->can_sleep = 1;
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del_timer(&uart->timer);
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}
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static void omap_uart_idle_timer(unsigned long data)
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{
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struct omap_uart_state *uart = (struct omap_uart_state *)data;
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omap_uart_allow_sleep(uart);
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}
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void omap_uart_prepare_idle(int num)
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{
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struct omap_uart_state *uart;
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list_for_each_entry(uart, &uart_list, node) {
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if (num == uart->num && uart->can_sleep) {
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omap_uart_disable_clocks(uart);
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return;
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}
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}
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}
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void omap_uart_resume_idle(int num)
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{
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struct omap_uart_state *uart;
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list_for_each_entry(uart, &uart_list, node) {
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if (num == uart->num) {
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omap_uart_enable_clocks(uart);
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/* Check for IO pad wakeup */
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if (cpu_is_omap34xx() && uart->padconf) {
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u16 p = omap_ctrl_readw(uart->padconf);
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if (p & OMAP3_PADCONF_WAKEUPEVENT0)
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omap_uart_block_sleep(uart);
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}
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/* Check for normal UART wakeup */
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if (__raw_readl(uart->wk_st) & uart->wk_mask)
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omap_uart_block_sleep(uart);
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return;
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}
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}
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}
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void omap_uart_prepare_suspend(void)
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{
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struct omap_uart_state *uart;
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list_for_each_entry(uart, &uart_list, node) {
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omap_uart_allow_sleep(uart);
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}
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}
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int omap_uart_can_sleep(void)
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{
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struct omap_uart_state *uart;
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int can_sleep = 1;
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list_for_each_entry(uart, &uart_list, node) {
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if (!uart->clocked)
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continue;
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if (!uart->can_sleep) {
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can_sleep = 0;
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continue;
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}
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/* This UART can now safely sleep. */
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omap_uart_allow_sleep(uart);
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}
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return can_sleep;
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}
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/**
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* omap_uart_interrupt()
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*
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* This handler is used only to detect that *any* UART interrupt has
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* occurred. It does _nothing_ to handle the interrupt. Rather,
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* any UART interrupt will trigger the inactivity timer so the
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* UART will not idle or sleep for its timeout period.
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*
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**/
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static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
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{
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struct omap_uart_state *uart = dev_id;
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omap_uart_block_sleep(uart);
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return IRQ_NONE;
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}
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static void omap_uart_idle_init(struct omap_uart_state *uart)
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{
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struct plat_serial8250_port *p = uart->p;
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int ret;
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uart->can_sleep = 0;
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uart->timeout = DEFAULT_TIMEOUT;
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setup_timer(&uart->timer, omap_uart_idle_timer,
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(unsigned long) uart);
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mod_timer(&uart->timer, jiffies + uart->timeout);
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omap_uart_smart_idle_enable(uart, 0);
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if (cpu_is_omap34xx()) {
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u32 mod = (uart->num == 2) ? OMAP3430_PER_MOD : CORE_MOD;
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u32 wk_mask = 0;
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u32 padconf = 0;
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uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
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uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
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switch (uart->num) {
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case 0:
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wk_mask = OMAP3430_ST_UART1_MASK;
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padconf = 0x182;
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break;
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case 1:
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wk_mask = OMAP3430_ST_UART2_MASK;
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padconf = 0x17a;
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break;
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case 2:
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wk_mask = OMAP3430_ST_UART3_MASK;
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padconf = 0x19e;
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break;
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}
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uart->wk_mask = wk_mask;
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uart->padconf = padconf;
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} else if (cpu_is_omap24xx()) {
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u32 wk_mask = 0;
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if (cpu_is_omap2430()) {
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uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKEN1);
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uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKST1);
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} else if (cpu_is_omap2420()) {
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uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKEN1);
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uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKST1);
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}
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switch (uart->num) {
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case 0:
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wk_mask = OMAP24XX_ST_UART1_MASK;
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break;
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case 1:
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wk_mask = OMAP24XX_ST_UART2_MASK;
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break;
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case 2:
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wk_mask = OMAP24XX_ST_UART3_MASK;
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break;
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}
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uart->wk_mask = wk_mask;
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} else {
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uart->wk_en = 0;
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uart->wk_st = 0;
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uart->wk_mask = 0;
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uart->padconf = 0;
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}
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p->irqflags |= IRQF_SHARED;
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ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED,
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"serial idle", (void *)uart);
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WARN_ON(ret);
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}
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void omap_uart_enable_irqs(int enable)
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{
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int ret;
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struct omap_uart_state *uart;
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list_for_each_entry(uart, &uart_list, node) {
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if (enable)
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ret = request_irq(uart->p->irq, omap_uart_interrupt,
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IRQF_SHARED, "serial idle", (void *)uart);
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else
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free_irq(uart->p->irq, (void *)uart);
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}
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}
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static ssize_t sleep_timeout_show(struct device *dev,
|
|
struct device_attribute *attr,
|
|
char *buf)
|
|
{
|
|
struct platform_device *pdev = container_of(dev,
|
|
struct platform_device, dev);
|
|
struct omap_uart_state *uart = container_of(pdev,
|
|
struct omap_uart_state, pdev);
|
|
|
|
return sprintf(buf, "%u\n", uart->timeout / HZ);
|
|
}
|
|
|
|
static ssize_t sleep_timeout_store(struct device *dev,
|
|
struct device_attribute *attr,
|
|
const char *buf, size_t n)
|
|
{
|
|
struct platform_device *pdev = container_of(dev,
|
|
struct platform_device, dev);
|
|
struct omap_uart_state *uart = container_of(pdev,
|
|
struct omap_uart_state, pdev);
|
|
unsigned int value;
|
|
|
|
if (sscanf(buf, "%u", &value) != 1) {
|
|
printk(KERN_ERR "sleep_timeout_store: Invalid value\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
uart->timeout = value * HZ;
|
|
if (uart->timeout)
|
|
mod_timer(&uart->timer, jiffies + uart->timeout);
|
|
else
|
|
/* A zero value means disable timeout feature */
|
|
omap_uart_block_sleep(uart);
|
|
|
|
return n;
|
|
}
|
|
|
|
DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show, sleep_timeout_store);
|
|
#define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr))
|
|
#else
|
|
static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
|
|
#define DEV_CREATE_FILE(dev, attr)
|
|
#endif /* CONFIG_PM */
|
|
|
|
static struct omap_uart_state omap_uart[OMAP_MAX_NR_PORTS] = {
|
|
{
|
|
.pdev = {
|
|
.name = "serial8250",
|
|
.id = PLAT8250_DEV_PLATFORM,
|
|
.dev = {
|
|
.platform_data = serial_platform_data0,
|
|
},
|
|
},
|
|
}, {
|
|
.pdev = {
|
|
.name = "serial8250",
|
|
.id = PLAT8250_DEV_PLATFORM1,
|
|
.dev = {
|
|
.platform_data = serial_platform_data1,
|
|
},
|
|
},
|
|
}, {
|
|
.pdev = {
|
|
.name = "serial8250",
|
|
.id = PLAT8250_DEV_PLATFORM2,
|
|
.dev = {
|
|
.platform_data = serial_platform_data2,
|
|
},
|
|
},
|
|
},
|
|
#ifdef CONFIG_ARCH_OMAP4
|
|
{
|
|
.pdev = {
|
|
.name = "serial8250",
|
|
.id = 3,
|
|
.dev = {
|
|
.platform_data = serial_platform_data3,
|
|
},
|
|
},
|
|
},
|
|
#endif
|
|
};
|
|
|
|
void __init omap_serial_early_init(void)
|
|
{
|
|
int i;
|
|
char name[16];
|
|
|
|
/*
|
|
* Make sure the serial ports are muxed on at this point.
|
|
* You have to mux them off in device drivers later on
|
|
* if not needed.
|
|
*/
|
|
|
|
for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
|
|
struct omap_uart_state *uart = &omap_uart[i];
|
|
struct platform_device *pdev = &uart->pdev;
|
|
struct device *dev = &pdev->dev;
|
|
struct plat_serial8250_port *p = dev->platform_data;
|
|
|
|
sprintf(name, "uart%d_ick", i+1);
|
|
uart->ick = clk_get(NULL, name);
|
|
if (IS_ERR(uart->ick)) {
|
|
printk(KERN_ERR "Could not get uart%d_ick\n", i+1);
|
|
uart->ick = NULL;
|
|
}
|
|
|
|
sprintf(name, "uart%d_fck", i+1);
|
|
uart->fck = clk_get(NULL, name);
|
|
if (IS_ERR(uart->fck)) {
|
|
printk(KERN_ERR "Could not get uart%d_fck\n", i+1);
|
|
uart->fck = NULL;
|
|
}
|
|
|
|
/* FIXME: Remove this once the clkdev is ready */
|
|
if (!cpu_is_omap44xx()) {
|
|
if (!uart->ick || !uart->fck)
|
|
continue;
|
|
}
|
|
|
|
uart->num = i;
|
|
p->private_data = uart;
|
|
uart->p = p;
|
|
list_add_tail(&uart->node, &uart_list);
|
|
|
|
if (cpu_is_omap44xx())
|
|
p->irq += 32;
|
|
|
|
omap_uart_enable_clocks(uart);
|
|
}
|
|
}
|
|
|
|
void __init omap_serial_init(void)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
|
|
struct omap_uart_state *uart = &omap_uart[i];
|
|
struct platform_device *pdev = &uart->pdev;
|
|
struct device *dev = &pdev->dev;
|
|
|
|
omap_uart_reset(uart);
|
|
omap_uart_idle_init(uart);
|
|
|
|
if (WARN_ON(platform_device_register(pdev)))
|
|
continue;
|
|
if ((cpu_is_omap34xx() && uart->padconf) ||
|
|
(uart->wk_en && uart->wk_mask)) {
|
|
device_init_wakeup(dev, true);
|
|
DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout);
|
|
}
|
|
}
|
|
}
|