264 lines
7.1 KiB
C
264 lines
7.1 KiB
C
/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include <core/gpuobj.h>
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#include <subdev/timer.h>
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#include <subdev/bar.h>
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#include <subdev/fb.h>
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#include <subdev/vm.h>
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struct nv50_bar_priv {
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struct nouveau_bar base;
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spinlock_t lock;
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struct nouveau_gpuobj *mem;
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struct nouveau_gpuobj *pad;
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struct nouveau_gpuobj *pgd;
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struct nouveau_vm *bar1_vm;
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struct nouveau_gpuobj *bar1;
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struct nouveau_vm *bar3_vm;
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struct nouveau_gpuobj *bar3;
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};
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static int
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nv50_bar_kmap(struct nouveau_bar *bar, struct nouveau_mem *mem,
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u32 flags, struct nouveau_vma *vma)
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{
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struct nv50_bar_priv *priv = (void *)bar;
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int ret;
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ret = nouveau_vm_get(priv->bar3_vm, mem->size << 12, 12, flags, vma);
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if (ret)
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return ret;
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nouveau_vm_map(vma, mem);
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nv50_vm_flush_engine(nv_subdev(bar), 6);
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return 0;
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}
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static int
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nv50_bar_umap(struct nouveau_bar *bar, struct nouveau_mem *mem,
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u32 flags, struct nouveau_vma *vma)
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{
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struct nv50_bar_priv *priv = (void *)bar;
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int ret;
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ret = nouveau_vm_get(priv->bar1_vm, mem->size << 12, 12, flags, vma);
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if (ret)
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return ret;
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nouveau_vm_map(vma, mem);
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nv50_vm_flush_engine(nv_subdev(bar), 6);
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return 0;
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}
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static void
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nv50_bar_unmap(struct nouveau_bar *bar, struct nouveau_vma *vma)
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{
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nouveau_vm_unmap(vma);
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nv50_vm_flush_engine(nv_subdev(bar), 6);
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nouveau_vm_put(vma);
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}
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static void
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nv50_bar_flush(struct nouveau_bar *bar)
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{
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struct nv50_bar_priv *priv = (void *)bar;
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unsigned long flags;
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spin_lock_irqsave(&priv->lock, flags);
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nv_wr32(priv, 0x00330c, 0x00000001);
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if (!nv_wait(priv, 0x00330c, 0x00000002, 0x00000000))
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nv_warn(priv, "flush timeout\n");
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spin_unlock_irqrestore(&priv->lock, flags);
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}
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void
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nv84_bar_flush(struct nouveau_bar *bar)
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{
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struct nv50_bar_priv *priv = (void *)bar;
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unsigned long flags;
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spin_lock_irqsave(&priv->lock, flags);
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nv_wr32(bar, 0x070000, 0x00000001);
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if (!nv_wait(priv, 0x070000, 0x00000002, 0x00000000))
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nv_warn(priv, "flush timeout\n");
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spin_unlock_irqrestore(&priv->lock, flags);
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}
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static int
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nv50_bar_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
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struct nouveau_oclass *oclass, void *data, u32 size,
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struct nouveau_object **pobject)
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{
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struct nouveau_device *device = nv_device(parent);
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struct nouveau_object *heap;
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struct nouveau_vm *vm;
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struct nv50_bar_priv *priv;
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u64 start, limit;
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int ret;
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ret = nouveau_bar_create(parent, engine, oclass, &priv);
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*pobject = nv_object(priv);
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if (ret)
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return ret;
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ret = nouveau_gpuobj_new(parent, NULL, 0x20000, 0, NVOBJ_FLAG_HEAP,
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&priv->mem);
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heap = nv_object(priv->mem);
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if (ret)
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return ret;
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ret = nouveau_gpuobj_new(parent, heap, (device->chipset == 0x50) ?
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0x1400 : 0x0200, 0, 0, &priv->pad);
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if (ret)
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return ret;
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ret = nouveau_gpuobj_new(parent, heap, 0x4000, 0, 0, &priv->pgd);
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if (ret)
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return ret;
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/* BAR3 */
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start = 0x0100000000ULL;
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limit = start + pci_resource_len(device->pdev, 3);
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ret = nouveau_vm_new(device, start, limit, start, &vm);
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if (ret)
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return ret;
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ret = nouveau_gpuobj_new(parent, heap, ((limit-- - start) >> 12) * 8,
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0x1000, NVOBJ_FLAG_ZERO_ALLOC,
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&vm->pgt[0].obj[0]);
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vm->pgt[0].refcount[0] = 1;
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if (ret)
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return ret;
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ret = nouveau_vm_ref(vm, &priv->bar3_vm, priv->pgd);
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nouveau_vm_ref(NULL, &vm, NULL);
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if (ret)
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return ret;
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ret = nouveau_gpuobj_new(parent, heap, 24, 16, 0, &priv->bar3);
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if (ret)
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return ret;
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nv_wo32(priv->bar3, 0x00, 0x7fc00000);
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nv_wo32(priv->bar3, 0x04, lower_32_bits(limit));
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nv_wo32(priv->bar3, 0x08, lower_32_bits(start));
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nv_wo32(priv->bar3, 0x0c, upper_32_bits(limit) << 24 |
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upper_32_bits(start));
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nv_wo32(priv->bar3, 0x10, 0x00000000);
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nv_wo32(priv->bar3, 0x14, 0x00000000);
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/* BAR1 */
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start = 0x0000000000ULL;
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limit = start + pci_resource_len(device->pdev, 1);
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ret = nouveau_vm_new(device, start, limit--, start, &vm);
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if (ret)
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return ret;
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ret = nouveau_vm_ref(vm, &priv->bar1_vm, priv->pgd);
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nouveau_vm_ref(NULL, &vm, NULL);
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if (ret)
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return ret;
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ret = nouveau_gpuobj_new(parent, heap, 24, 16, 0, &priv->bar1);
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if (ret)
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return ret;
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nv_wo32(priv->bar1, 0x00, 0x7fc00000);
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nv_wo32(priv->bar1, 0x04, lower_32_bits(limit));
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nv_wo32(priv->bar1, 0x08, lower_32_bits(start));
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nv_wo32(priv->bar1, 0x0c, upper_32_bits(limit) << 24 |
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upper_32_bits(start));
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nv_wo32(priv->bar1, 0x10, 0x00000000);
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nv_wo32(priv->bar1, 0x14, 0x00000000);
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priv->base.alloc = nouveau_bar_alloc;
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priv->base.kmap = nv50_bar_kmap;
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priv->base.umap = nv50_bar_umap;
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priv->base.unmap = nv50_bar_unmap;
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if (device->chipset == 0x50)
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priv->base.flush = nv50_bar_flush;
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else
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priv->base.flush = nv84_bar_flush;
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spin_lock_init(&priv->lock);
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return 0;
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}
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static void
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nv50_bar_dtor(struct nouveau_object *object)
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{
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struct nv50_bar_priv *priv = (void *)object;
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nouveau_gpuobj_ref(NULL, &priv->bar1);
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nouveau_vm_ref(NULL, &priv->bar1_vm, priv->pgd);
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nouveau_gpuobj_ref(NULL, &priv->bar3);
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if (priv->bar3_vm) {
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nouveau_gpuobj_ref(NULL, &priv->bar3_vm->pgt[0].obj[0]);
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nouveau_vm_ref(NULL, &priv->bar3_vm, priv->pgd);
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}
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nouveau_gpuobj_ref(NULL, &priv->pgd);
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nouveau_gpuobj_ref(NULL, &priv->pad);
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nouveau_gpuobj_ref(NULL, &priv->mem);
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nouveau_bar_destroy(&priv->base);
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}
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static int
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nv50_bar_init(struct nouveau_object *object)
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{
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struct nv50_bar_priv *priv = (void *)object;
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int ret;
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ret = nouveau_bar_init(&priv->base);
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if (ret)
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return ret;
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nv_mask(priv, 0x000200, 0x00000100, 0x00000000);
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nv_mask(priv, 0x000200, 0x00000100, 0x00000100);
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nv50_vm_flush_engine(nv_subdev(priv), 6);
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nv_wr32(priv, 0x001704, 0x00000000 | priv->mem->addr >> 12);
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nv_wr32(priv, 0x001704, 0x40000000 | priv->mem->addr >> 12);
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nv_wr32(priv, 0x001708, 0x80000000 | priv->bar1->node->offset >> 4);
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nv_wr32(priv, 0x00170c, 0x80000000 | priv->bar3->node->offset >> 4);
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return 0;
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}
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static int
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nv50_bar_fini(struct nouveau_object *object, bool suspend)
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{
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struct nv50_bar_priv *priv = (void *)object;
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return nouveau_bar_fini(&priv->base, suspend);
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}
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struct nouveau_oclass
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nv50_bar_oclass = {
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.handle = NV_SUBDEV(BAR, 0x50),
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.ofuncs = &(struct nouveau_ofuncs) {
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.ctor = nv50_bar_ctor,
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.dtor = nv50_bar_dtor,
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.init = nv50_bar_init,
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.fini = nv50_bar_fini,
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},
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};
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