1261 lines
34 KiB
C
1261 lines
34 KiB
C
/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include <core/object.h>
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#include <core/parent.h>
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#include <core/handle.h>
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#include <core/class.h>
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#include <engine/software.h>
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#include <engine/disp.h>
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#include <subdev/bios.h>
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#include <subdev/bios/dcb.h>
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#include <subdev/bios/disp.h>
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#include <subdev/bios/init.h>
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#include <subdev/bios/pll.h>
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#include <subdev/timer.h>
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#include <subdev/fb.h>
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#include <subdev/bar.h>
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#include <subdev/clock.h>
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#include "nv50.h"
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/*******************************************************************************
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* EVO channel base class
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******************************************************************************/
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int
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nv50_disp_chan_create_(struct nouveau_object *parent,
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struct nouveau_object *engine,
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struct nouveau_oclass *oclass, int chid,
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int length, void **pobject)
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{
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struct nv50_disp_base *base = (void *)parent;
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struct nv50_disp_chan *chan;
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int ret;
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if (base->chan & (1 << chid))
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return -EBUSY;
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base->chan |= (1 << chid);
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ret = nouveau_namedb_create_(parent, engine, oclass, 0, NULL,
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(1ULL << NVDEV_ENGINE_DMAOBJ),
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length, pobject);
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chan = *pobject;
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if (ret)
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return ret;
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chan->chid = chid;
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return 0;
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}
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void
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nv50_disp_chan_destroy(struct nv50_disp_chan *chan)
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{
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struct nv50_disp_base *base = (void *)nv_object(chan)->parent;
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base->chan &= ~(1 << chan->chid);
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nouveau_namedb_destroy(&chan->base);
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}
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u32
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nv50_disp_chan_rd32(struct nouveau_object *object, u64 addr)
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{
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struct nv50_disp_priv *priv = (void *)object->engine;
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struct nv50_disp_chan *chan = (void *)object;
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return nv_rd32(priv, 0x640000 + (chan->chid * 0x1000) + addr);
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}
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void
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nv50_disp_chan_wr32(struct nouveau_object *object, u64 addr, u32 data)
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{
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struct nv50_disp_priv *priv = (void *)object->engine;
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struct nv50_disp_chan *chan = (void *)object;
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nv_wr32(priv, 0x640000 + (chan->chid * 0x1000) + addr, data);
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}
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/*******************************************************************************
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* EVO DMA channel base class
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******************************************************************************/
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static int
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nv50_disp_dmac_object_attach(struct nouveau_object *parent,
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struct nouveau_object *object, u32 name)
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{
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struct nv50_disp_base *base = (void *)parent->parent;
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struct nv50_disp_chan *chan = (void *)parent;
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u32 addr = nv_gpuobj(object)->node->offset;
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u32 chid = chan->chid;
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u32 data = (chid << 28) | (addr << 10) | chid;
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return nouveau_ramht_insert(base->ramht, chid, name, data);
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}
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static void
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nv50_disp_dmac_object_detach(struct nouveau_object *parent, int cookie)
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{
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struct nv50_disp_base *base = (void *)parent->parent;
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nouveau_ramht_remove(base->ramht, cookie);
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}
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int
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nv50_disp_dmac_create_(struct nouveau_object *parent,
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struct nouveau_object *engine,
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struct nouveau_oclass *oclass, u32 pushbuf, int chid,
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int length, void **pobject)
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{
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struct nv50_disp_dmac *dmac;
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int ret;
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ret = nv50_disp_chan_create_(parent, engine, oclass, chid,
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length, pobject);
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dmac = *pobject;
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if (ret)
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return ret;
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dmac->pushdma = (void *)nouveau_handle_ref(parent, pushbuf);
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if (!dmac->pushdma)
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return -ENOENT;
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switch (nv_mclass(dmac->pushdma)) {
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case 0x0002:
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case 0x003d:
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if (dmac->pushdma->limit - dmac->pushdma->start != 0xfff)
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return -EINVAL;
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switch (dmac->pushdma->target) {
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case NV_MEM_TARGET_VRAM:
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dmac->push = 0x00000000 | dmac->pushdma->start >> 8;
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break;
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case NV_MEM_TARGET_PCI_NOSNOOP:
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dmac->push = 0x00000003 | dmac->pushdma->start >> 8;
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break;
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default:
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return -EINVAL;
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}
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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void
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nv50_disp_dmac_dtor(struct nouveau_object *object)
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{
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struct nv50_disp_dmac *dmac = (void *)object;
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nouveau_object_ref(NULL, (struct nouveau_object **)&dmac->pushdma);
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nv50_disp_chan_destroy(&dmac->base);
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}
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static int
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nv50_disp_dmac_init(struct nouveau_object *object)
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{
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struct nv50_disp_priv *priv = (void *)object->engine;
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struct nv50_disp_dmac *dmac = (void *)object;
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int chid = dmac->base.chid;
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int ret;
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ret = nv50_disp_chan_init(&dmac->base);
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if (ret)
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return ret;
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/* enable error reporting */
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nv_mask(priv, 0x610028, 0x00010001 << chid, 0x00010001 << chid);
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/* initialise channel for dma command submission */
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nv_wr32(priv, 0x610204 + (chid * 0x0010), dmac->push);
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nv_wr32(priv, 0x610208 + (chid * 0x0010), 0x00010000);
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nv_wr32(priv, 0x61020c + (chid * 0x0010), chid);
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nv_mask(priv, 0x610200 + (chid * 0x0010), 0x00000010, 0x00000010);
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nv_wr32(priv, 0x640000 + (chid * 0x1000), 0x00000000);
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nv_wr32(priv, 0x610200 + (chid * 0x0010), 0x00000013);
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/* wait for it to go inactive */
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if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x80000000, 0x00000000)) {
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nv_error(dmac, "init timeout, 0x%08x\n",
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nv_rd32(priv, 0x610200 + (chid * 0x10)));
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return -EBUSY;
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}
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return 0;
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}
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static int
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nv50_disp_dmac_fini(struct nouveau_object *object, bool suspend)
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{
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struct nv50_disp_priv *priv = (void *)object->engine;
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struct nv50_disp_dmac *dmac = (void *)object;
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int chid = dmac->base.chid;
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/* deactivate channel */
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nv_mask(priv, 0x610200 + (chid * 0x0010), 0x00001010, 0x00001000);
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nv_mask(priv, 0x610200 + (chid * 0x0010), 0x00000003, 0x00000000);
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if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x001e0000, 0x00000000)) {
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nv_error(dmac, "fini timeout, 0x%08x\n",
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nv_rd32(priv, 0x610200 + (chid * 0x10)));
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if (suspend)
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return -EBUSY;
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}
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/* disable error reporting */
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nv_mask(priv, 0x610028, 0x00010001 << chid, 0x00000000 << chid);
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return nv50_disp_chan_fini(&dmac->base, suspend);
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}
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/*******************************************************************************
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* EVO master channel object
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******************************************************************************/
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static int
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nv50_disp_mast_ctor(struct nouveau_object *parent,
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struct nouveau_object *engine,
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struct nouveau_oclass *oclass, void *data, u32 size,
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struct nouveau_object **pobject)
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{
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struct nv50_display_mast_class *args = data;
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struct nv50_disp_dmac *mast;
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int ret;
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if (size < sizeof(*args))
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return -EINVAL;
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ret = nv50_disp_dmac_create_(parent, engine, oclass, args->pushbuf,
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0, sizeof(*mast), (void **)&mast);
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*pobject = nv_object(mast);
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if (ret)
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return ret;
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nv_parent(mast)->object_attach = nv50_disp_dmac_object_attach;
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nv_parent(mast)->object_detach = nv50_disp_dmac_object_detach;
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return 0;
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}
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static int
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nv50_disp_mast_init(struct nouveau_object *object)
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{
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struct nv50_disp_priv *priv = (void *)object->engine;
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struct nv50_disp_dmac *mast = (void *)object;
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int ret;
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ret = nv50_disp_chan_init(&mast->base);
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if (ret)
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return ret;
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/* enable error reporting */
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nv_mask(priv, 0x610028, 0x00010001, 0x00010001);
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/* attempt to unstick channel from some unknown state */
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if ((nv_rd32(priv, 0x610200) & 0x009f0000) == 0x00020000)
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nv_mask(priv, 0x610200, 0x00800000, 0x00800000);
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if ((nv_rd32(priv, 0x610200) & 0x003f0000) == 0x00030000)
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nv_mask(priv, 0x610200, 0x00600000, 0x00600000);
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/* initialise channel for dma command submission */
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nv_wr32(priv, 0x610204, mast->push);
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nv_wr32(priv, 0x610208, 0x00010000);
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nv_wr32(priv, 0x61020c, 0x00000000);
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nv_mask(priv, 0x610200, 0x00000010, 0x00000010);
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nv_wr32(priv, 0x640000, 0x00000000);
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nv_wr32(priv, 0x610200, 0x01000013);
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/* wait for it to go inactive */
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if (!nv_wait(priv, 0x610200, 0x80000000, 0x00000000)) {
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nv_error(mast, "init: 0x%08x\n", nv_rd32(priv, 0x610200));
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return -EBUSY;
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}
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return 0;
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}
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static int
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nv50_disp_mast_fini(struct nouveau_object *object, bool suspend)
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{
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struct nv50_disp_priv *priv = (void *)object->engine;
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struct nv50_disp_dmac *mast = (void *)object;
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/* deactivate channel */
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nv_mask(priv, 0x610200, 0x00000010, 0x00000000);
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nv_mask(priv, 0x610200, 0x00000003, 0x00000000);
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if (!nv_wait(priv, 0x610200, 0x001e0000, 0x00000000)) {
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nv_error(mast, "fini: 0x%08x\n", nv_rd32(priv, 0x610200));
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if (suspend)
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return -EBUSY;
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}
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/* disable error reporting */
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nv_mask(priv, 0x610028, 0x00010001, 0x00000000);
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return nv50_disp_chan_fini(&mast->base, suspend);
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}
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struct nouveau_ofuncs
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nv50_disp_mast_ofuncs = {
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.ctor = nv50_disp_mast_ctor,
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.dtor = nv50_disp_dmac_dtor,
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.init = nv50_disp_mast_init,
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.fini = nv50_disp_mast_fini,
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.rd32 = nv50_disp_chan_rd32,
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.wr32 = nv50_disp_chan_wr32,
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};
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/*******************************************************************************
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* EVO sync channel objects
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******************************************************************************/
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static int
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nv50_disp_sync_ctor(struct nouveau_object *parent,
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struct nouveau_object *engine,
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struct nouveau_oclass *oclass, void *data, u32 size,
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struct nouveau_object **pobject)
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{
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struct nv50_display_sync_class *args = data;
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struct nv50_disp_dmac *dmac;
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int ret;
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if (size < sizeof(*data) || args->head > 1)
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return -EINVAL;
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ret = nv50_disp_dmac_create_(parent, engine, oclass, args->pushbuf,
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1 + args->head, sizeof(*dmac),
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(void **)&dmac);
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*pobject = nv_object(dmac);
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if (ret)
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return ret;
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nv_parent(dmac)->object_attach = nv50_disp_dmac_object_attach;
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nv_parent(dmac)->object_detach = nv50_disp_dmac_object_detach;
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return 0;
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}
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struct nouveau_ofuncs
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nv50_disp_sync_ofuncs = {
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.ctor = nv50_disp_sync_ctor,
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.dtor = nv50_disp_dmac_dtor,
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.init = nv50_disp_dmac_init,
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.fini = nv50_disp_dmac_fini,
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.rd32 = nv50_disp_chan_rd32,
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.wr32 = nv50_disp_chan_wr32,
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};
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/*******************************************************************************
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* EVO overlay channel objects
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******************************************************************************/
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static int
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nv50_disp_ovly_ctor(struct nouveau_object *parent,
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struct nouveau_object *engine,
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struct nouveau_oclass *oclass, void *data, u32 size,
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struct nouveau_object **pobject)
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{
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struct nv50_display_ovly_class *args = data;
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struct nv50_disp_dmac *dmac;
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int ret;
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if (size < sizeof(*data) || args->head > 1)
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return -EINVAL;
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ret = nv50_disp_dmac_create_(parent, engine, oclass, args->pushbuf,
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3 + args->head, sizeof(*dmac),
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(void **)&dmac);
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*pobject = nv_object(dmac);
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if (ret)
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return ret;
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nv_parent(dmac)->object_attach = nv50_disp_dmac_object_attach;
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nv_parent(dmac)->object_detach = nv50_disp_dmac_object_detach;
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return 0;
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}
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struct nouveau_ofuncs
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nv50_disp_ovly_ofuncs = {
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.ctor = nv50_disp_ovly_ctor,
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.dtor = nv50_disp_dmac_dtor,
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.init = nv50_disp_dmac_init,
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.fini = nv50_disp_dmac_fini,
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.rd32 = nv50_disp_chan_rd32,
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.wr32 = nv50_disp_chan_wr32,
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};
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/*******************************************************************************
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* EVO PIO channel base class
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******************************************************************************/
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static int
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nv50_disp_pioc_create_(struct nouveau_object *parent,
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struct nouveau_object *engine,
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struct nouveau_oclass *oclass, int chid,
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int length, void **pobject)
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{
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return nv50_disp_chan_create_(parent, engine, oclass, chid,
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length, pobject);
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}
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static void
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nv50_disp_pioc_dtor(struct nouveau_object *object)
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{
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struct nv50_disp_pioc *pioc = (void *)object;
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nv50_disp_chan_destroy(&pioc->base);
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}
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static int
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nv50_disp_pioc_init(struct nouveau_object *object)
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{
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struct nv50_disp_priv *priv = (void *)object->engine;
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struct nv50_disp_pioc *pioc = (void *)object;
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int chid = pioc->base.chid;
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int ret;
|
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|
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ret = nv50_disp_chan_init(&pioc->base);
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if (ret)
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return ret;
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nv_wr32(priv, 0x610200 + (chid * 0x10), 0x00002000);
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if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x00000000, 0x00000000)) {
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nv_error(pioc, "timeout0: 0x%08x\n",
|
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nv_rd32(priv, 0x610200 + (chid * 0x10)));
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return -EBUSY;
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}
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|
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nv_wr32(priv, 0x610200 + (chid * 0x10), 0x00000001);
|
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if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x00030000, 0x00010000)) {
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nv_error(pioc, "timeout1: 0x%08x\n",
|
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nv_rd32(priv, 0x610200 + (chid * 0x10)));
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return -EBUSY;
|
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}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
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nv50_disp_pioc_fini(struct nouveau_object *object, bool suspend)
|
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{
|
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struct nv50_disp_priv *priv = (void *)object->engine;
|
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struct nv50_disp_pioc *pioc = (void *)object;
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int chid = pioc->base.chid;
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nv_mask(priv, 0x610200 + (chid * 0x10), 0x00000001, 0x00000000);
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if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x00030000, 0x00000000)) {
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nv_error(pioc, "timeout: 0x%08x\n",
|
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nv_rd32(priv, 0x610200 + (chid * 0x10)));
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if (suspend)
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return -EBUSY;
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}
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|
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return nv50_disp_chan_fini(&pioc->base, suspend);
|
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}
|
|
|
|
/*******************************************************************************
|
|
* EVO immediate overlay channel objects
|
|
******************************************************************************/
|
|
|
|
static int
|
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nv50_disp_oimm_ctor(struct nouveau_object *parent,
|
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struct nouveau_object *engine,
|
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struct nouveau_oclass *oclass, void *data, u32 size,
|
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struct nouveau_object **pobject)
|
|
{
|
|
struct nv50_display_oimm_class *args = data;
|
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struct nv50_disp_pioc *pioc;
|
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int ret;
|
|
|
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if (size < sizeof(*args) || args->head > 1)
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return -EINVAL;
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|
|
ret = nv50_disp_pioc_create_(parent, engine, oclass, 5 + args->head,
|
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sizeof(*pioc), (void **)&pioc);
|
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*pobject = nv_object(pioc);
|
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if (ret)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
struct nouveau_ofuncs
|
|
nv50_disp_oimm_ofuncs = {
|
|
.ctor = nv50_disp_oimm_ctor,
|
|
.dtor = nv50_disp_pioc_dtor,
|
|
.init = nv50_disp_pioc_init,
|
|
.fini = nv50_disp_pioc_fini,
|
|
.rd32 = nv50_disp_chan_rd32,
|
|
.wr32 = nv50_disp_chan_wr32,
|
|
};
|
|
|
|
/*******************************************************************************
|
|
* EVO cursor channel objects
|
|
******************************************************************************/
|
|
|
|
static int
|
|
nv50_disp_curs_ctor(struct nouveau_object *parent,
|
|
struct nouveau_object *engine,
|
|
struct nouveau_oclass *oclass, void *data, u32 size,
|
|
struct nouveau_object **pobject)
|
|
{
|
|
struct nv50_display_curs_class *args = data;
|
|
struct nv50_disp_pioc *pioc;
|
|
int ret;
|
|
|
|
if (size < sizeof(*args) || args->head > 1)
|
|
return -EINVAL;
|
|
|
|
ret = nv50_disp_pioc_create_(parent, engine, oclass, 7 + args->head,
|
|
sizeof(*pioc), (void **)&pioc);
|
|
*pobject = nv_object(pioc);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
struct nouveau_ofuncs
|
|
nv50_disp_curs_ofuncs = {
|
|
.ctor = nv50_disp_curs_ctor,
|
|
.dtor = nv50_disp_pioc_dtor,
|
|
.init = nv50_disp_pioc_init,
|
|
.fini = nv50_disp_pioc_fini,
|
|
.rd32 = nv50_disp_chan_rd32,
|
|
.wr32 = nv50_disp_chan_wr32,
|
|
};
|
|
|
|
/*******************************************************************************
|
|
* Base display object
|
|
******************************************************************************/
|
|
|
|
static int
|
|
nv50_disp_base_ctor(struct nouveau_object *parent,
|
|
struct nouveau_object *engine,
|
|
struct nouveau_oclass *oclass, void *data, u32 size,
|
|
struct nouveau_object **pobject)
|
|
{
|
|
struct nv50_disp_priv *priv = (void *)engine;
|
|
struct nv50_disp_base *base;
|
|
int ret;
|
|
|
|
ret = nouveau_parent_create(parent, engine, oclass, 0,
|
|
priv->sclass, 0, &base);
|
|
*pobject = nv_object(base);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return nouveau_ramht_new(parent, parent, 0x1000, 0, &base->ramht);
|
|
}
|
|
|
|
static void
|
|
nv50_disp_base_dtor(struct nouveau_object *object)
|
|
{
|
|
struct nv50_disp_base *base = (void *)object;
|
|
nouveau_ramht_ref(NULL, &base->ramht);
|
|
nouveau_parent_destroy(&base->base);
|
|
}
|
|
|
|
static int
|
|
nv50_disp_base_init(struct nouveau_object *object)
|
|
{
|
|
struct nv50_disp_priv *priv = (void *)object->engine;
|
|
struct nv50_disp_base *base = (void *)object;
|
|
int ret, i;
|
|
u32 tmp;
|
|
|
|
ret = nouveau_parent_init(&base->base);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* The below segments of code copying values from one register to
|
|
* another appear to inform EVO of the display capabilities or
|
|
* something similar. NFI what the 0x614004 caps are for..
|
|
*/
|
|
tmp = nv_rd32(priv, 0x614004);
|
|
nv_wr32(priv, 0x610184, tmp);
|
|
|
|
/* ... CRTC caps */
|
|
for (i = 0; i < priv->head.nr; i++) {
|
|
tmp = nv_rd32(priv, 0x616100 + (i * 0x800));
|
|
nv_wr32(priv, 0x610190 + (i * 0x10), tmp);
|
|
tmp = nv_rd32(priv, 0x616104 + (i * 0x800));
|
|
nv_wr32(priv, 0x610194 + (i * 0x10), tmp);
|
|
tmp = nv_rd32(priv, 0x616108 + (i * 0x800));
|
|
nv_wr32(priv, 0x610198 + (i * 0x10), tmp);
|
|
tmp = nv_rd32(priv, 0x61610c + (i * 0x800));
|
|
nv_wr32(priv, 0x61019c + (i * 0x10), tmp);
|
|
}
|
|
|
|
/* ... DAC caps */
|
|
for (i = 0; i < priv->dac.nr; i++) {
|
|
tmp = nv_rd32(priv, 0x61a000 + (i * 0x800));
|
|
nv_wr32(priv, 0x6101d0 + (i * 0x04), tmp);
|
|
}
|
|
|
|
/* ... SOR caps */
|
|
for (i = 0; i < priv->sor.nr; i++) {
|
|
tmp = nv_rd32(priv, 0x61c000 + (i * 0x800));
|
|
nv_wr32(priv, 0x6101e0 + (i * 0x04), tmp);
|
|
}
|
|
|
|
/* ... EXT caps */
|
|
for (i = 0; i < 3; i++) {
|
|
tmp = nv_rd32(priv, 0x61e000 + (i * 0x800));
|
|
nv_wr32(priv, 0x6101f0 + (i * 0x04), tmp);
|
|
}
|
|
|
|
/* steal display away from vbios, or something like that */
|
|
if (nv_rd32(priv, 0x610024) & 0x00000100) {
|
|
nv_wr32(priv, 0x610024, 0x00000100);
|
|
nv_mask(priv, 0x6194e8, 0x00000001, 0x00000000);
|
|
if (!nv_wait(priv, 0x6194e8, 0x00000002, 0x00000000)) {
|
|
nv_error(priv, "timeout acquiring display\n");
|
|
return -EBUSY;
|
|
}
|
|
}
|
|
|
|
/* point at display engine memory area (hash table, objects) */
|
|
nv_wr32(priv, 0x610010, (nv_gpuobj(base->ramht)->addr >> 8) | 9);
|
|
|
|
/* enable supervisor interrupts, disable everything else */
|
|
nv_wr32(priv, 0x61002c, 0x00000370);
|
|
nv_wr32(priv, 0x610028, 0x00000000);
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
nv50_disp_base_fini(struct nouveau_object *object, bool suspend)
|
|
{
|
|
struct nv50_disp_priv *priv = (void *)object->engine;
|
|
struct nv50_disp_base *base = (void *)object;
|
|
|
|
/* disable all interrupts */
|
|
nv_wr32(priv, 0x610024, 0x00000000);
|
|
nv_wr32(priv, 0x610020, 0x00000000);
|
|
|
|
return nouveau_parent_fini(&base->base, suspend);
|
|
}
|
|
|
|
struct nouveau_ofuncs
|
|
nv50_disp_base_ofuncs = {
|
|
.ctor = nv50_disp_base_ctor,
|
|
.dtor = nv50_disp_base_dtor,
|
|
.init = nv50_disp_base_init,
|
|
.fini = nv50_disp_base_fini,
|
|
};
|
|
|
|
static struct nouveau_omthds
|
|
nv50_disp_base_omthds[] = {
|
|
{ SOR_MTHD(NV50_DISP_SOR_PWR) , nv50_sor_mthd },
|
|
{ SOR_MTHD(NV50_DISP_SOR_LVDS_SCRIPT) , nv50_sor_mthd },
|
|
{ DAC_MTHD(NV50_DISP_DAC_PWR) , nv50_dac_mthd },
|
|
{ DAC_MTHD(NV50_DISP_DAC_LOAD) , nv50_dac_mthd },
|
|
{},
|
|
};
|
|
|
|
static struct nouveau_oclass
|
|
nv50_disp_base_oclass[] = {
|
|
{ NV50_DISP_CLASS, &nv50_disp_base_ofuncs, nv50_disp_base_omthds },
|
|
{}
|
|
};
|
|
|
|
static struct nouveau_oclass
|
|
nv50_disp_sclass[] = {
|
|
{ NV50_DISP_MAST_CLASS, &nv50_disp_mast_ofuncs },
|
|
{ NV50_DISP_SYNC_CLASS, &nv50_disp_sync_ofuncs },
|
|
{ NV50_DISP_OVLY_CLASS, &nv50_disp_ovly_ofuncs },
|
|
{ NV50_DISP_OIMM_CLASS, &nv50_disp_oimm_ofuncs },
|
|
{ NV50_DISP_CURS_CLASS, &nv50_disp_curs_ofuncs },
|
|
{}
|
|
};
|
|
|
|
/*******************************************************************************
|
|
* Display context, tracks instmem allocation and prevents more than one
|
|
* client using the display hardware at any time.
|
|
******************************************************************************/
|
|
|
|
static int
|
|
nv50_disp_data_ctor(struct nouveau_object *parent,
|
|
struct nouveau_object *engine,
|
|
struct nouveau_oclass *oclass, void *data, u32 size,
|
|
struct nouveau_object **pobject)
|
|
{
|
|
struct nv50_disp_priv *priv = (void *)engine;
|
|
struct nouveau_engctx *ectx;
|
|
int ret = -EBUSY;
|
|
|
|
/* no context needed for channel objects... */
|
|
if (nv_mclass(parent) != NV_DEVICE_CLASS) {
|
|
atomic_inc(&parent->refcount);
|
|
*pobject = parent;
|
|
return 0;
|
|
}
|
|
|
|
/* allocate display hardware to client */
|
|
mutex_lock(&nv_subdev(priv)->mutex);
|
|
if (list_empty(&nv_engine(priv)->contexts)) {
|
|
ret = nouveau_engctx_create(parent, engine, oclass, NULL,
|
|
0x10000, 0x10000,
|
|
NVOBJ_FLAG_HEAP, &ectx);
|
|
*pobject = nv_object(ectx);
|
|
}
|
|
mutex_unlock(&nv_subdev(priv)->mutex);
|
|
return ret;
|
|
}
|
|
|
|
struct nouveau_oclass
|
|
nv50_disp_cclass = {
|
|
.handle = NV_ENGCTX(DISP, 0x50),
|
|
.ofuncs = &(struct nouveau_ofuncs) {
|
|
.ctor = nv50_disp_data_ctor,
|
|
.dtor = _nouveau_engctx_dtor,
|
|
.init = _nouveau_engctx_init,
|
|
.fini = _nouveau_engctx_fini,
|
|
.rd32 = _nouveau_engctx_rd32,
|
|
.wr32 = _nouveau_engctx_wr32,
|
|
},
|
|
};
|
|
|
|
/*******************************************************************************
|
|
* Display engine implementation
|
|
******************************************************************************/
|
|
|
|
static void
|
|
nv50_disp_intr_error(struct nv50_disp_priv *priv)
|
|
{
|
|
u32 channels = (nv_rd32(priv, 0x610020) & 0x001f0000) >> 16;
|
|
u32 addr, data;
|
|
int chid;
|
|
|
|
for (chid = 0; chid < 5; chid++) {
|
|
if (!(channels & (1 << chid)))
|
|
continue;
|
|
|
|
nv_wr32(priv, 0x610020, 0x00010000 << chid);
|
|
addr = nv_rd32(priv, 0x610080 + (chid * 0x08));
|
|
data = nv_rd32(priv, 0x610084 + (chid * 0x08));
|
|
nv_wr32(priv, 0x610080 + (chid * 0x08), 0x90000000);
|
|
|
|
nv_error(priv, "chid %d mthd 0x%04x data 0x%08x 0x%08x\n",
|
|
chid, addr & 0xffc, data, addr);
|
|
}
|
|
}
|
|
|
|
static void
|
|
nv50_disp_intr_vblank(struct nv50_disp_priv *priv, int crtc)
|
|
{
|
|
struct nouveau_bar *bar = nouveau_bar(priv);
|
|
struct nouveau_disp *disp = &priv->base;
|
|
struct nouveau_software_chan *chan, *temp;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&disp->vblank.lock, flags);
|
|
list_for_each_entry_safe(chan, temp, &disp->vblank.list, vblank.head) {
|
|
if (chan->vblank.crtc != crtc)
|
|
continue;
|
|
|
|
if (nv_device(priv)->chipset >= 0xc0) {
|
|
nv_wr32(priv, 0x001718, 0x80000000 | chan->vblank.channel);
|
|
bar->flush(bar);
|
|
nv_wr32(priv, 0x06000c,
|
|
upper_32_bits(chan->vblank.offset));
|
|
nv_wr32(priv, 0x060010,
|
|
lower_32_bits(chan->vblank.offset));
|
|
nv_wr32(priv, 0x060014, chan->vblank.value);
|
|
} else {
|
|
nv_wr32(priv, 0x001704, chan->vblank.channel);
|
|
nv_wr32(priv, 0x001710, 0x80000000 | chan->vblank.ctxdma);
|
|
bar->flush(bar);
|
|
if (nv_device(priv)->chipset == 0x50) {
|
|
nv_wr32(priv, 0x001570, chan->vblank.offset);
|
|
nv_wr32(priv, 0x001574, chan->vblank.value);
|
|
} else {
|
|
nv_wr32(priv, 0x060010, chan->vblank.offset);
|
|
nv_wr32(priv, 0x060014, chan->vblank.value);
|
|
}
|
|
}
|
|
|
|
list_del(&chan->vblank.head);
|
|
if (disp->vblank.put)
|
|
disp->vblank.put(disp->vblank.data, crtc);
|
|
}
|
|
spin_unlock_irqrestore(&disp->vblank.lock, flags);
|
|
|
|
if (disp->vblank.notify)
|
|
disp->vblank.notify(disp->vblank.data, crtc);
|
|
}
|
|
|
|
static u16
|
|
exec_lookup(struct nv50_disp_priv *priv, int head, int outp, u32 ctrl,
|
|
struct dcb_output *dcb, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
|
|
struct nvbios_outp *info)
|
|
{
|
|
struct nouveau_bios *bios = nouveau_bios(priv);
|
|
u16 mask, type, data;
|
|
|
|
if (outp < 4) {
|
|
type = DCB_OUTPUT_ANALOG;
|
|
mask = 0;
|
|
} else {
|
|
outp -= 4;
|
|
switch (ctrl & 0x00000f00) {
|
|
case 0x00000000: type = DCB_OUTPUT_LVDS; mask = 1; break;
|
|
case 0x00000100: type = DCB_OUTPUT_TMDS; mask = 1; break;
|
|
case 0x00000200: type = DCB_OUTPUT_TMDS; mask = 2; break;
|
|
case 0x00000500: type = DCB_OUTPUT_TMDS; mask = 3; break;
|
|
case 0x00000800: type = DCB_OUTPUT_DP; mask = 1; break;
|
|
case 0x00000900: type = DCB_OUTPUT_DP; mask = 2; break;
|
|
default:
|
|
nv_error(priv, "unknown SOR mc 0x%08x\n", ctrl);
|
|
return 0x0000;
|
|
}
|
|
}
|
|
|
|
mask = 0x00c0 & (mask << 6);
|
|
mask |= 0x0001 << outp;
|
|
mask |= 0x0100 << head;
|
|
|
|
data = dcb_outp_match(bios, type, mask, ver, hdr, dcb);
|
|
if (!data)
|
|
return 0x0000;
|
|
|
|
return nvbios_outp_match(bios, type, mask, ver, hdr, cnt, len, info);
|
|
}
|
|
|
|
static bool
|
|
exec_script(struct nv50_disp_priv *priv, int head, int id)
|
|
{
|
|
struct nouveau_bios *bios = nouveau_bios(priv);
|
|
struct nvbios_outp info;
|
|
struct dcb_output dcb;
|
|
u8 ver, hdr, cnt, len;
|
|
u16 data;
|
|
u32 ctrl = 0x00000000;
|
|
int i;
|
|
|
|
for (i = 0; !(ctrl & (1 << head)) && i < 3; i++)
|
|
ctrl = nv_rd32(priv, 0x610b5c + (i * 8));
|
|
|
|
if (!(ctrl & (1 << head))) {
|
|
if (nv_device(priv)->chipset < 0x90 ||
|
|
nv_device(priv)->chipset == 0x92 ||
|
|
nv_device(priv)->chipset == 0xa0) {
|
|
for (i = 0; !(ctrl & (1 << head)) && i < 2; i++)
|
|
ctrl = nv_rd32(priv, 0x610b74 + (i * 8));
|
|
i += 4;
|
|
} else {
|
|
for (i = 0; !(ctrl & (1 << head)) && i < 4; i++)
|
|
ctrl = nv_rd32(priv, 0x610798 + (i * 8));
|
|
i += 4;
|
|
}
|
|
}
|
|
|
|
if (!(ctrl & (1 << head)))
|
|
return false;
|
|
i--;
|
|
|
|
data = exec_lookup(priv, head, i, ctrl, &dcb, &ver, &hdr, &cnt, &len, &info);
|
|
if (data) {
|
|
struct nvbios_init init = {
|
|
.subdev = nv_subdev(priv),
|
|
.bios = bios,
|
|
.offset = info.script[id],
|
|
.outp = &dcb,
|
|
.crtc = head,
|
|
.execute = 1,
|
|
};
|
|
|
|
return nvbios_exec(&init) == 0;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
static u32
|
|
exec_clkcmp(struct nv50_disp_priv *priv, int head, int id, u32 pclk,
|
|
struct dcb_output *outp)
|
|
{
|
|
struct nouveau_bios *bios = nouveau_bios(priv);
|
|
struct nvbios_outp info1;
|
|
struct nvbios_ocfg info2;
|
|
u8 ver, hdr, cnt, len;
|
|
u16 data, conf;
|
|
u32 ctrl = 0x00000000;
|
|
int i;
|
|
|
|
for (i = 0; !(ctrl & (1 << head)) && i < 3; i++)
|
|
ctrl = nv_rd32(priv, 0x610b58 + (i * 8));
|
|
|
|
if (!(ctrl & (1 << head))) {
|
|
if (nv_device(priv)->chipset < 0x90 ||
|
|
nv_device(priv)->chipset == 0x92 ||
|
|
nv_device(priv)->chipset == 0xa0) {
|
|
for (i = 0; !(ctrl & (1 << head)) && i < 2; i++)
|
|
ctrl = nv_rd32(priv, 0x610b70 + (i * 8));
|
|
i += 4;
|
|
} else {
|
|
for (i = 0; !(ctrl & (1 << head)) && i < 4; i++)
|
|
ctrl = nv_rd32(priv, 0x610794 + (i * 8));
|
|
i += 4;
|
|
}
|
|
}
|
|
|
|
if (!(ctrl & (1 << head)))
|
|
return 0x0000;
|
|
i--;
|
|
|
|
data = exec_lookup(priv, head, i, ctrl, outp, &ver, &hdr, &cnt, &len, &info1);
|
|
if (!data)
|
|
return 0x0000;
|
|
|
|
switch (outp->type) {
|
|
case DCB_OUTPUT_TMDS:
|
|
conf = (ctrl & 0x00000f00) >> 8;
|
|
if (pclk >= 165000)
|
|
conf |= 0x0100;
|
|
break;
|
|
case DCB_OUTPUT_LVDS:
|
|
conf = priv->sor.lvdsconf;
|
|
break;
|
|
case DCB_OUTPUT_DP:
|
|
conf = (ctrl & 0x00000f00) >> 8;
|
|
break;
|
|
case DCB_OUTPUT_ANALOG:
|
|
default:
|
|
conf = 0x00ff;
|
|
break;
|
|
}
|
|
|
|
data = nvbios_ocfg_match(bios, data, conf, &ver, &hdr, &cnt, &len, &info2);
|
|
if (data) {
|
|
data = nvbios_oclk_match(bios, info2.clkcmp[id], pclk);
|
|
if (data) {
|
|
struct nvbios_init init = {
|
|
.subdev = nv_subdev(priv),
|
|
.bios = bios,
|
|
.offset = data,
|
|
.outp = outp,
|
|
.crtc = head,
|
|
.execute = 1,
|
|
};
|
|
|
|
if (nvbios_exec(&init))
|
|
return 0x0000;
|
|
return conf;
|
|
}
|
|
}
|
|
|
|
return 0x0000;
|
|
}
|
|
|
|
static void
|
|
nv50_disp_intr_unk10(struct nv50_disp_priv *priv, u32 super)
|
|
{
|
|
int head = ffs((super & 0x00000060) >> 5) - 1;
|
|
if (head >= 0) {
|
|
head = ffs((super & 0x00000180) >> 7) - 1;
|
|
if (head >= 0)
|
|
exec_script(priv, head, 1);
|
|
}
|
|
|
|
nv_wr32(priv, 0x610024, 0x00000010);
|
|
nv_wr32(priv, 0x610030, 0x80000000);
|
|
}
|
|
|
|
static void
|
|
nv50_disp_intr_unk20_dp(struct nv50_disp_priv *priv,
|
|
struct dcb_output *outp, u32 pclk)
|
|
{
|
|
const int link = !(outp->sorconf.link & 1);
|
|
const int or = ffs(outp->or) - 1;
|
|
const u32 soff = ( or * 0x800);
|
|
const u32 loff = (link * 0x080) + soff;
|
|
const u32 ctrl = nv_rd32(priv, 0x610794 + (or * 8));
|
|
const u32 symbol = 100000;
|
|
u32 dpctrl = nv_rd32(priv, 0x61c10c + loff) & 0x0000f0000;
|
|
u32 clksor = nv_rd32(priv, 0x614300 + soff);
|
|
int bestTU = 0, bestVTUi = 0, bestVTUf = 0, bestVTUa = 0;
|
|
int TU, VTUi, VTUf, VTUa;
|
|
u64 link_data_rate, link_ratio, unk;
|
|
u32 best_diff = 64 * symbol;
|
|
u32 link_nr, link_bw, bits, r;
|
|
|
|
/* calculate packed data rate for each lane */
|
|
if (dpctrl > 0x00030000) link_nr = 4;
|
|
else if (dpctrl > 0x00010000) link_nr = 2;
|
|
else link_nr = 1;
|
|
|
|
if (clksor & 0x000c0000)
|
|
link_bw = 270000;
|
|
else
|
|
link_bw = 162000;
|
|
|
|
if ((ctrl & 0xf0000) == 0x60000) bits = 30;
|
|
else if ((ctrl & 0xf0000) == 0x50000) bits = 24;
|
|
else bits = 18;
|
|
|
|
link_data_rate = (pclk * bits / 8) / link_nr;
|
|
|
|
/* calculate ratio of packed data rate to link symbol rate */
|
|
link_ratio = link_data_rate * symbol;
|
|
r = do_div(link_ratio, link_bw);
|
|
|
|
for (TU = 64; TU >= 32; TU--) {
|
|
/* calculate average number of valid symbols in each TU */
|
|
u32 tu_valid = link_ratio * TU;
|
|
u32 calc, diff;
|
|
|
|
/* find a hw representation for the fraction.. */
|
|
VTUi = tu_valid / symbol;
|
|
calc = VTUi * symbol;
|
|
diff = tu_valid - calc;
|
|
if (diff) {
|
|
if (diff >= (symbol / 2)) {
|
|
VTUf = symbol / (symbol - diff);
|
|
if (symbol - (VTUf * diff))
|
|
VTUf++;
|
|
|
|
if (VTUf <= 15) {
|
|
VTUa = 1;
|
|
calc += symbol - (symbol / VTUf);
|
|
} else {
|
|
VTUa = 0;
|
|
VTUf = 1;
|
|
calc += symbol;
|
|
}
|
|
} else {
|
|
VTUa = 0;
|
|
VTUf = min((int)(symbol / diff), 15);
|
|
calc += symbol / VTUf;
|
|
}
|
|
|
|
diff = calc - tu_valid;
|
|
} else {
|
|
/* no remainder, but the hw doesn't like the fractional
|
|
* part to be zero. decrement the integer part and
|
|
* have the fraction add a whole symbol back
|
|
*/
|
|
VTUa = 0;
|
|
VTUf = 1;
|
|
VTUi--;
|
|
}
|
|
|
|
if (diff < best_diff) {
|
|
best_diff = diff;
|
|
bestTU = TU;
|
|
bestVTUa = VTUa;
|
|
bestVTUf = VTUf;
|
|
bestVTUi = VTUi;
|
|
if (diff == 0)
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (!bestTU) {
|
|
nv_error(priv, "unable to find suitable dp config\n");
|
|
return;
|
|
}
|
|
|
|
/* XXX close to vbios numbers, but not right */
|
|
unk = (symbol - link_ratio) * bestTU;
|
|
unk *= link_ratio;
|
|
r = do_div(unk, symbol);
|
|
r = do_div(unk, symbol);
|
|
unk += 6;
|
|
|
|
nv_mask(priv, 0x61c10c + loff, 0x000001fc, bestTU << 2);
|
|
nv_mask(priv, 0x61c128 + loff, 0x010f7f3f, bestVTUa << 24 |
|
|
bestVTUf << 16 |
|
|
bestVTUi << 8 | unk);
|
|
}
|
|
|
|
static void
|
|
nv50_disp_intr_unk20(struct nv50_disp_priv *priv, u32 super)
|
|
{
|
|
struct dcb_output outp;
|
|
u32 addr, mask, data;
|
|
int head;
|
|
|
|
/* finish detaching encoder? */
|
|
head = ffs((super & 0x00000180) >> 7) - 1;
|
|
if (head >= 0)
|
|
exec_script(priv, head, 2);
|
|
|
|
/* check whether a vpll change is required */
|
|
head = ffs((super & 0x00000600) >> 9) - 1;
|
|
if (head >= 0) {
|
|
u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff;
|
|
if (pclk) {
|
|
struct nouveau_clock *clk = nouveau_clock(priv);
|
|
clk->pll_set(clk, PLL_VPLL0 + head, pclk);
|
|
}
|
|
|
|
nv_mask(priv, 0x614200 + head * 0x800, 0x0000000f, 0x00000000);
|
|
}
|
|
|
|
/* (re)attach the relevant OR to the head */
|
|
head = ffs((super & 0x00000180) >> 7) - 1;
|
|
if (head >= 0) {
|
|
u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff;
|
|
u32 conf = exec_clkcmp(priv, head, 0, pclk, &outp);
|
|
if (conf) {
|
|
if (outp.type == DCB_OUTPUT_ANALOG) {
|
|
addr = 0x614280 + (ffs(outp.or) - 1) * 0x800;
|
|
mask = 0xffffffff;
|
|
data = 0x00000000;
|
|
} else {
|
|
if (outp.type == DCB_OUTPUT_DP)
|
|
nv50_disp_intr_unk20_dp(priv, &outp, pclk);
|
|
addr = 0x614300 + (ffs(outp.or) - 1) * 0x800;
|
|
mask = 0x00000707;
|
|
data = (conf & 0x0100) ? 0x0101 : 0x0000;
|
|
}
|
|
|
|
nv_mask(priv, addr, mask, data);
|
|
}
|
|
}
|
|
|
|
nv_wr32(priv, 0x610024, 0x00000020);
|
|
nv_wr32(priv, 0x610030, 0x80000000);
|
|
}
|
|
|
|
/* If programming a TMDS output on a SOR that can also be configured for
|
|
* DisplayPort, make sure NV50_SOR_DP_CTRL_ENABLE is forced off.
|
|
*
|
|
* It looks like the VBIOS TMDS scripts make an attempt at this, however,
|
|
* the VBIOS scripts on at least one board I have only switch it off on
|
|
* link 0, causing a blank display if the output has previously been
|
|
* programmed for DisplayPort.
|
|
*/
|
|
static void
|
|
nv50_disp_intr_unk40_tmds(struct nv50_disp_priv *priv, struct dcb_output *outp)
|
|
{
|
|
struct nouveau_bios *bios = nouveau_bios(priv);
|
|
const int link = !(outp->sorconf.link & 1);
|
|
const int or = ffs(outp->or) - 1;
|
|
const u32 loff = (or * 0x800) + (link * 0x80);
|
|
const u16 mask = (outp->sorconf.link << 6) | outp->or;
|
|
u8 ver, hdr;
|
|
|
|
if (dcb_outp_match(bios, DCB_OUTPUT_DP, mask, &ver, &hdr, outp))
|
|
nv_mask(priv, 0x61c10c + loff, 0x00000001, 0x00000000);
|
|
}
|
|
|
|
static void
|
|
nv50_disp_intr_unk40(struct nv50_disp_priv *priv, u32 super)
|
|
{
|
|
int head = ffs((super & 0x00000180) >> 7) - 1;
|
|
if (head >= 0) {
|
|
struct dcb_output outp;
|
|
u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff;
|
|
if (pclk && exec_clkcmp(priv, head, 1, pclk, &outp)) {
|
|
if (outp.type == DCB_OUTPUT_TMDS)
|
|
nv50_disp_intr_unk40_tmds(priv, &outp);
|
|
}
|
|
}
|
|
|
|
nv_wr32(priv, 0x610024, 0x00000040);
|
|
nv_wr32(priv, 0x610030, 0x80000000);
|
|
}
|
|
|
|
static void
|
|
nv50_disp_intr_super(struct nv50_disp_priv *priv, u32 intr1)
|
|
{
|
|
u32 super = nv_rd32(priv, 0x610030);
|
|
|
|
nv_debug(priv, "supervisor 0x%08x 0x%08x\n", intr1, super);
|
|
|
|
if (intr1 & 0x00000010)
|
|
nv50_disp_intr_unk10(priv, super);
|
|
if (intr1 & 0x00000020)
|
|
nv50_disp_intr_unk20(priv, super);
|
|
if (intr1 & 0x00000040)
|
|
nv50_disp_intr_unk40(priv, super);
|
|
}
|
|
|
|
void
|
|
nv50_disp_intr(struct nouveau_subdev *subdev)
|
|
{
|
|
struct nv50_disp_priv *priv = (void *)subdev;
|
|
u32 intr0 = nv_rd32(priv, 0x610020);
|
|
u32 intr1 = nv_rd32(priv, 0x610024);
|
|
|
|
if (intr0 & 0x001f0000) {
|
|
nv50_disp_intr_error(priv);
|
|
intr0 &= ~0x001f0000;
|
|
}
|
|
|
|
if (intr1 & 0x00000004) {
|
|
nv50_disp_intr_vblank(priv, 0);
|
|
nv_wr32(priv, 0x610024, 0x00000004);
|
|
intr1 &= ~0x00000004;
|
|
}
|
|
|
|
if (intr1 & 0x00000008) {
|
|
nv50_disp_intr_vblank(priv, 1);
|
|
nv_wr32(priv, 0x610024, 0x00000008);
|
|
intr1 &= ~0x00000008;
|
|
}
|
|
|
|
if (intr1 & 0x00000070) {
|
|
nv50_disp_intr_super(priv, intr1);
|
|
intr1 &= ~0x00000070;
|
|
}
|
|
}
|
|
|
|
static int
|
|
nv50_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
|
|
struct nouveau_oclass *oclass, void *data, u32 size,
|
|
struct nouveau_object **pobject)
|
|
{
|
|
struct nv50_disp_priv *priv;
|
|
int ret;
|
|
|
|
ret = nouveau_disp_create(parent, engine, oclass, "PDISP",
|
|
"display", &priv);
|
|
*pobject = nv_object(priv);
|
|
if (ret)
|
|
return ret;
|
|
|
|
nv_engine(priv)->sclass = nv50_disp_base_oclass;
|
|
nv_engine(priv)->cclass = &nv50_disp_cclass;
|
|
nv_subdev(priv)->intr = nv50_disp_intr;
|
|
priv->sclass = nv50_disp_sclass;
|
|
priv->head.nr = 2;
|
|
priv->dac.nr = 3;
|
|
priv->sor.nr = 2;
|
|
priv->dac.power = nv50_dac_power;
|
|
priv->dac.sense = nv50_dac_sense;
|
|
priv->sor.power = nv50_sor_power;
|
|
|
|
INIT_LIST_HEAD(&priv->base.vblank.list);
|
|
spin_lock_init(&priv->base.vblank.lock);
|
|
return 0;
|
|
}
|
|
|
|
struct nouveau_oclass
|
|
nv50_disp_oclass = {
|
|
.handle = NV_ENGINE(DISP, 0x50),
|
|
.ofuncs = &(struct nouveau_ofuncs) {
|
|
.ctor = nv50_disp_ctor,
|
|
.dtor = _nouveau_disp_dtor,
|
|
.init = _nouveau_disp_init,
|
|
.fini = _nouveau_disp_fini,
|
|
},
|
|
};
|