b98348bdd0
Teach AVR32 to use the "GPIO Library" when exposing its GPIOs, so that signals on external chips (like GPIO expanders) can easily be used. This mostly reorganizes some existing logic, with two minor changes in behavior: - The PSR registers are used instead of the previous "gpio_mask" values, matching AT91 behavior and removing some duplication between that role and that of "pinmux_mask". - NR_IRQs grew to acommodate a bank of external GPIOs. Eventually this number should probably become a board-specific config option. There's a debugfs dump of status for the built-in GPIOs, showing which pins have deglitching, pullups, or open drain drive enabled, as well as the ID string used when requesting each IRQ. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Acked-by: Haavard Skinnemoen <hskinnemoen@atmel.com> Cc: Jean Delvare <khali@linux-fr.org> Cc: Eric Miao <eric.miao@marvell.com> Cc: Sam Ravnborg <sam@ravnborg.org> Cc: Philipp Zabel <philipp.zabel@gmail.com> Cc: Russell King <rmk@arm.linux.org.uk> Cc: Ben Gardner <bgardner@wabtec.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
15 lines
402 B
C
15 lines
402 B
C
#ifndef __ASM_AVR32_ARCH_IRQ_H
|
|
#define __ASM_AVR32_ARCH_IRQ_H
|
|
|
|
#define EIM_IRQ_BASE NR_INTERNAL_IRQS
|
|
#define NR_EIM_IRQS 32
|
|
#define AT32_EXTINT(n) (EIM_IRQ_BASE + (n))
|
|
|
|
#define GPIO_IRQ_BASE (EIM_IRQ_BASE + NR_EIM_IRQS)
|
|
#define NR_GPIO_CTLR (5 /*internal*/ + 1 /*external*/)
|
|
#define NR_GPIO_IRQS (NR_GPIO_CTLR * 32)
|
|
|
|
#define NR_IRQS (GPIO_IRQ_BASE + NR_GPIO_IRQS)
|
|
|
|
#endif /* __ASM_AVR32_ARCH_IRQ_H */
|