![Matt Hsu](/assets/img/avatar_default.png)
Select the correct EINT configuration register when configuring the external interrupt level/edge type. Signed-off-by: Matt Hsu <matt_hsu@openmoko.org> [ben-linux@fluff.org: description improvement] Signed-off-by: Ben Dooks <ben-linux@fluff.org>
203 lines
4.5 KiB
C
203 lines
4.5 KiB
C
/* arch/arm/plat-s3c64xx/irq-eint.c
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* S3C64XX - Interrupt handling for IRQ_EINT(x)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <asm/hardware/vic.h>
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#include <plat/regs-irqtype.h>
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#include <mach/map.h>
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#include <plat/cpu.h>
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/* GPIO is 0x7F008xxx, */
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#define S3C64XX_GPIOREG(x) (S3C64XX_VA_GPIO + (x))
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#define S3C64XX_EINT0CON0 S3C64XX_GPIOREG(0x900)
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#define S3C64XX_EINT0CON1 S3C64XX_GPIOREG(0x904)
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#define S3C64XX_EINT0FLTCON0 S3C64XX_GPIOREG(0x910)
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#define S3C64XX_EINT0FLTCON1 S3C64XX_GPIOREG(0x914)
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#define S3C64XX_EINT0FLTCON2 S3C64XX_GPIOREG(0x918)
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#define S3C64XX_EINT0FLTCON3 S3C64XX_GPIOREG(0x91C)
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#define S3C64XX_EINT0MASK S3C64XX_GPIOREG(0x920)
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#define S3C64XX_EINT0PEND S3C64XX_GPIOREG(0x924)
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#define eint_offset(irq) ((irq) - IRQ_EINT(0))
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#define eint_irq_to_bit(irq) (1 << eint_offset(irq))
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static inline void s3c_irq_eint_mask(unsigned int irq)
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{
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u32 mask;
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mask = __raw_readl(S3C64XX_EINT0MASK);
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mask |= eint_irq_to_bit(irq);
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__raw_writel(mask, S3C64XX_EINT0MASK);
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}
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static void s3c_irq_eint_unmask(unsigned int irq)
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{
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u32 mask;
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mask = __raw_readl(S3C64XX_EINT0MASK);
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mask |= eint_irq_to_bit(irq);
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__raw_writel(mask, S3C64XX_EINT0MASK);
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}
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static inline void s3c_irq_eint_ack(unsigned int irq)
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{
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__raw_writel(eint_irq_to_bit(irq), S3C64XX_EINT0PEND);
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}
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static void s3c_irq_eint_maskack(unsigned int irq)
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{
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/* compiler should in-line these */
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s3c_irq_eint_mask(irq);
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s3c_irq_eint_ack(irq);
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}
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static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type)
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{
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int offs = eint_offset(irq);
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int shift;
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u32 ctrl, mask;
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u32 newvalue = 0;
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void __iomem *reg;
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if (offs > 27)
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return -EINVAL;
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if (offs <= 15)
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reg = S3C64XX_EINT0CON0;
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else
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reg = S3C64XX_EINT0CON1;
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switch (type) {
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case IRQ_TYPE_NONE:
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printk(KERN_WARNING "No edge setting!\n");
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break;
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case IRQ_TYPE_EDGE_RISING:
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newvalue = S3C2410_EXTINT_RISEEDGE;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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newvalue = S3C2410_EXTINT_FALLEDGE;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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newvalue = S3C2410_EXTINT_BOTHEDGE;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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newvalue = S3C2410_EXTINT_LOWLEV;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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newvalue = S3C2410_EXTINT_HILEV;
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break;
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default:
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printk(KERN_ERR "No such irq type %d", type);
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return -1;
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}
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shift = (offs / 2) * 4;
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mask = 0x7 << shift;
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ctrl = __raw_readl(reg);
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ctrl &= ~mask;
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ctrl |= newvalue << shift;
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__raw_writel(ctrl, reg);
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return 0;
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}
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static struct irq_chip s3c_irq_eint = {
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.name = "s3c-eint",
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.mask = s3c_irq_eint_mask,
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.unmask = s3c_irq_eint_unmask,
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.mask_ack = s3c_irq_eint_maskack,
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.ack = s3c_irq_eint_ack,
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.set_type = s3c_irq_eint_set_type,
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};
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/* s3c_irq_demux_eint
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*
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* This function demuxes the IRQ from the group0 external interrupts,
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* from IRQ_EINT(0) to IRQ_EINT(27). It is designed to be inlined into
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* the specific handlers s3c_irq_demux_eintX_Y.
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*/
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static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end)
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{
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u32 status = __raw_readl(S3C64XX_EINT0PEND);
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u32 mask = __raw_readl(S3C64XX_EINT0MASK);
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unsigned int irq;
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status &= ~mask;
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status >>= start;
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status &= (1 << (end - start + 1)) - 1;
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for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
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if (status & 1)
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generic_handle_irq(irq);
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status >>= 1;
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}
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}
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static void s3c_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
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{
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s3c_irq_demux_eint(0, 3);
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}
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static void s3c_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
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{
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s3c_irq_demux_eint(4, 11);
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}
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static void s3c_irq_demux_eint12_19(unsigned int irq, struct irq_desc *desc)
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{
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s3c_irq_demux_eint(12, 19);
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}
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static void s3c_irq_demux_eint20_27(unsigned int irq, struct irq_desc *desc)
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{
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s3c_irq_demux_eint(20, 27);
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}
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int __init s3c64xx_init_irq_eint(void)
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{
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int irq;
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for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) {
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set_irq_chip(irq, &s3c_irq_eint);
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set_irq_handler(irq, handle_level_irq);
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set_irq_flags(irq, IRQF_VALID);
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}
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set_irq_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3);
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set_irq_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11);
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set_irq_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19);
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set_irq_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27);
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return 0;
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}
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arch_initcall(s3c64xx_init_irq_eint);
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