9d325f2341
The S3C64XX timer is running at the wrong rate due to the assumptions made in the timer initialisation about the way the pwm dividers work. This means that time on the S3C64XX runs twice as fast as it should. Fix the problem by moving to using the clk framework to setup the pwm timer clock muxes, as the pwm-clock code has all the necessary knowledge of how the timer clock inputs are routed. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
286 lines
7 KiB
C
286 lines
7 KiB
C
/* linux/arch/arm/plat-s3c24xx/time.c
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*
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* Copyright (C) 2003-2005 Simtec Electronics
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* Ben Dooks, <ben@simtec.co.uk>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <asm/system.h>
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#include <asm/leds.h>
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#include <asm/mach-types.h>
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#include <asm/irq.h>
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#include <mach/map.h>
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#include <plat/regs-timer.h>
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#include <mach/regs-irq.h>
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#include <asm/mach/time.h>
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#include <mach/tick.h>
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#include <plat/clock.h>
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#include <plat/cpu.h>
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static unsigned long timer_startval;
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static unsigned long timer_usec_ticks;
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#ifndef TICK_MAX
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#define TICK_MAX (0xffff)
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#endif
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#define TIMER_USEC_SHIFT 16
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/* we use the shifted arithmetic to work out the ratio of timer ticks
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* to usecs, as often the peripheral clock is not a nice even multiple
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* of 1MHz.
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*
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* shift of 14 and 15 are too low for the 12MHz, 16 seems to be ok
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* for the current HZ value of 200 without producing overflows.
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*
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* Original patch by Dimitry Andric, updated by Ben Dooks
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*/
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/* timer_mask_usec_ticks
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*
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* given a clock and divisor, make the value to pass into timer_ticks_to_usec
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* to scale the ticks into usecs
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*/
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static inline unsigned long
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timer_mask_usec_ticks(unsigned long scaler, unsigned long pclk)
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{
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unsigned long den = pclk / 1000;
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return ((1000 << TIMER_USEC_SHIFT) * scaler + (den >> 1)) / den;
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}
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/* timer_ticks_to_usec
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*
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* convert timer ticks to usec.
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*/
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static inline unsigned long timer_ticks_to_usec(unsigned long ticks)
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{
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unsigned long res;
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res = ticks * timer_usec_ticks;
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res += 1 << (TIMER_USEC_SHIFT - 4); /* round up slightly */
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return res >> TIMER_USEC_SHIFT;
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}
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/***
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* Returns microsecond since last clock interrupt. Note that interrupts
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* will have been disabled by do_gettimeoffset()
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* IRQs are disabled before entering here from do_gettimeofday()
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*/
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static unsigned long s3c2410_gettimeoffset (void)
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{
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unsigned long tdone;
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unsigned long tval;
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/* work out how many ticks have gone since last timer interrupt */
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tval = __raw_readl(S3C2410_TCNTO(4));
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tdone = timer_startval - tval;
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/* check to see if there is an interrupt pending */
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if (s3c24xx_ostimer_pending()) {
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/* re-read the timer, and try and fix up for the missed
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* interrupt. Note, the interrupt may go off before the
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* timer has re-loaded from wrapping.
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*/
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tval = __raw_readl(S3C2410_TCNTO(4));
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tdone = timer_startval - tval;
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if (tval != 0)
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tdone += timer_startval;
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}
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return timer_ticks_to_usec(tdone);
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}
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/*
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* IRQ handler for the timer
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*/
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static irqreturn_t
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s3c2410_timer_interrupt(int irq, void *dev_id)
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{
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timer_tick();
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return IRQ_HANDLED;
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}
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static struct irqaction s3c2410_timer_irq = {
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.name = "S3C2410 Timer Tick",
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.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
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.handler = s3c2410_timer_interrupt,
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};
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#define use_tclk1_12() ( \
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machine_is_bast() || \
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machine_is_vr1000() || \
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machine_is_anubis() || \
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machine_is_osiris())
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static struct clk *tin;
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static struct clk *tdiv;
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static struct clk *timerclk;
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/*
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* Set up timer interrupt, and return the current time in seconds.
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*
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* Currently we only use timer4, as it is the only timer which has no
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* other function that can be exploited externally
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*/
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static void s3c2410_timer_setup (void)
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{
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unsigned long tcon;
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unsigned long tcnt;
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unsigned long tcfg1;
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unsigned long tcfg0;
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tcnt = TICK_MAX; /* default value for tcnt */
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/* configure the system for whichever machine is in use */
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if (use_tclk1_12()) {
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/* timer is at 12MHz, scaler is 1 */
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timer_usec_ticks = timer_mask_usec_ticks(1, 12000000);
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tcnt = 12000000 / HZ;
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tcfg1 = __raw_readl(S3C2410_TCFG1);
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tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK;
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tcfg1 |= S3C2410_TCFG1_MUX4_TCLK1;
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__raw_writel(tcfg1, S3C2410_TCFG1);
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} else {
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unsigned long pclk;
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struct clk *tscaler;
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/* for the h1940 (and others), we use the pclk from the core
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* to generate the timer values. since values around 50 to
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* 70MHz are not values we can directly generate the timer
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* value from, we need to pre-scale and divide before using it.
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*
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* for instance, using 50.7MHz and dividing by 6 gives 8.45MHz
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* (8.45 ticks per usec)
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*/
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pclk = clk_get_rate(timerclk);
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/* configure clock tick */
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timer_usec_ticks = timer_mask_usec_ticks(6, pclk);
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tscaler = clk_get_parent(tdiv);
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clk_set_rate(tscaler, pclk / 3);
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clk_set_rate(tdiv, pclk / 6);
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clk_set_parent(tin, tdiv);
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tcnt = clk_get_rate(tin) / HZ;
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}
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tcon = __raw_readl(S3C2410_TCON);
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tcfg0 = __raw_readl(S3C2410_TCFG0);
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tcfg1 = __raw_readl(S3C2410_TCFG1);
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/* timers reload after counting zero, so reduce the count by 1 */
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tcnt--;
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printk(KERN_DEBUG "timer tcon=%08lx, tcnt %04lx, tcfg %08lx,%08lx, usec %08lx\n",
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tcon, tcnt, tcfg0, tcfg1, timer_usec_ticks);
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/* check to see if timer is within 16bit range... */
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if (tcnt > TICK_MAX) {
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panic("setup_timer: HZ is too small, cannot configure timer!");
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return;
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}
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__raw_writel(tcfg1, S3C2410_TCFG1);
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__raw_writel(tcfg0, S3C2410_TCFG0);
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timer_startval = tcnt;
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__raw_writel(tcnt, S3C2410_TCNTB(4));
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/* ensure timer is stopped... */
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tcon &= ~(7<<20);
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tcon |= S3C2410_TCON_T4RELOAD;
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tcon |= S3C2410_TCON_T4MANUALUPD;
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__raw_writel(tcon, S3C2410_TCON);
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__raw_writel(tcnt, S3C2410_TCNTB(4));
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__raw_writel(tcnt, S3C2410_TCMPB(4));
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/* start the timer running */
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tcon |= S3C2410_TCON_T4START;
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tcon &= ~S3C2410_TCON_T4MANUALUPD;
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__raw_writel(tcon, S3C2410_TCON);
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}
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static void __init s3c2410_timer_resources(void)
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{
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struct platform_device tmpdev;
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tmpdev.dev.bus = &platform_bus_type;
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tmpdev.id = 4;
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timerclk = clk_get(NULL, "timers");
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if (IS_ERR(timerclk))
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panic("failed to get clock for system timer");
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clk_enable(timerclk);
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if (!use_tclk1_12()) {
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tin = clk_get(&tmpdev.dev, "pwm-tin");
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if (IS_ERR(tin))
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panic("failed to get pwm-tin clock for system timer");
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tdiv = clk_get(&tmpdev.dev, "pwm-tdiv");
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if (IS_ERR(tdiv))
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panic("failed to get pwm-tdiv clock for system timer");
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}
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clk_enable(tin);
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}
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static void __init s3c2410_timer_init(void)
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{
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s3c2410_timer_resources();
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s3c2410_timer_setup();
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setup_irq(IRQ_TIMER4, &s3c2410_timer_irq);
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}
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struct sys_timer s3c24xx_timer = {
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.init = s3c2410_timer_init,
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.offset = s3c2410_gettimeoffset,
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.resume = s3c2410_timer_setup
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};
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