![Ronen Shitrit](/assets/img/avatar_default.png)
Add support to the Kirkwood port for newer device models and silicon revisions. Instead of looking at the DEVICE_ID register, the device version is now determined by looking at the PCI-Express device ID and revision registers, as it is done for orion5x, and this information is used to determine the TCLK frequency, again, as it is done for orion5x. Signed-off-by: Ronen Shitrit <rshitrit@marvell.com> Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
187 lines
4 KiB
C
187 lines
4 KiB
C
/*
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* arch/arm/mach-kirkwood/pcie.c
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*
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* PCIe functions for Marvell Kirkwood SoCs
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/mbus.h>
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#include <asm/mach/pci.h>
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#include <plat/pcie.h>
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#include "common.h"
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#define PCIE_BASE ((void __iomem *)PCIE_VIRT_BASE)
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void __init kirkwood_pcie_id(u32 *dev, u32 *rev)
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{
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*dev = orion_pcie_dev_id(PCIE_BASE);
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*rev = orion_pcie_rev(PCIE_BASE);
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}
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static int pcie_valid_config(int bus, int dev)
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{
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/*
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* Don't go out when trying to access --
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* 1. nonexisting device on local bus
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* 2. where there's no device connected (no link)
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*/
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if (bus == 0 && dev == 0)
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return 1;
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if (!orion_pcie_link_up(PCIE_BASE))
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return 0;
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if (bus == 0 && dev != 1)
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return 0;
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return 1;
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}
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/*
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* PCIe config cycles are done by programming the PCIE_CONF_ADDR register
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* and then reading the PCIE_CONF_DATA register. Need to make sure these
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* transactions are atomic.
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*/
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static DEFINE_SPINLOCK(kirkwood_pcie_lock);
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static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
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int size, u32 *val)
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{
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unsigned long flags;
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int ret;
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if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
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*val = 0xffffffff;
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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spin_lock_irqsave(&kirkwood_pcie_lock, flags);
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ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val);
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spin_unlock_irqrestore(&kirkwood_pcie_lock, flags);
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return ret;
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}
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static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
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int where, int size, u32 val)
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{
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unsigned long flags;
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int ret;
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if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
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return PCIBIOS_DEVICE_NOT_FOUND;
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spin_lock_irqsave(&kirkwood_pcie_lock, flags);
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ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val);
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spin_unlock_irqrestore(&kirkwood_pcie_lock, flags);
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return ret;
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}
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static struct pci_ops pcie_ops = {
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.read = pcie_rd_conf,
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.write = pcie_wr_conf,
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};
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static int kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
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{
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struct resource *res;
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/*
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* Generic PCIe unit setup.
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*/
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orion_pcie_setup(PCIE_BASE, &kirkwood_mbus_dram_info);
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/*
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* Request resources.
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*/
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res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
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if (!res)
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panic("pcie_setup unable to alloc resources");
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/*
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* IORESOURCE_IO
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*/
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res[0].name = "PCIe I/O Space";
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res[0].flags = IORESOURCE_IO;
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res[0].start = KIRKWOOD_PCIE_IO_PHYS_BASE;
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res[0].end = res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
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if (request_resource(&ioport_resource, &res[0]))
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panic("Request PCIe IO resource failed\n");
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sys->resource[0] = &res[0];
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/*
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* IORESOURCE_MEM
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*/
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res[1].name = "PCIe Memory Space";
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res[1].flags = IORESOURCE_MEM;
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res[1].start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
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res[1].end = res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1;
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if (request_resource(&iomem_resource, &res[1]))
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panic("Request PCIe Memory resource failed\n");
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sys->resource[1] = &res[1];
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sys->resource[2] = NULL;
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sys->io_offset = 0;
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return 1;
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}
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static void __devinit rc_pci_fixup(struct pci_dev *dev)
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{
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/*
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* Prevent enumeration of root complex.
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*/
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if (dev->bus->parent == NULL && dev->devfn == 0) {
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int i;
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for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
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dev->resource[i].start = 0;
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dev->resource[i].end = 0;
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dev->resource[i].flags = 0;
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}
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}
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
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static struct pci_bus __init *
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kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
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{
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struct pci_bus *bus;
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if (nr == 0) {
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bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
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} else {
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bus = NULL;
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BUG();
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}
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return bus;
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}
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static int __init kirkwood_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
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{
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return IRQ_KIRKWOOD_PCIE;
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}
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static struct hw_pci kirkwood_pci __initdata = {
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.nr_controllers = 1,
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.swizzle = pci_std_swizzle,
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.setup = kirkwood_pcie_setup,
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.scan = kirkwood_pcie_scan_bus,
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.map_irq = kirkwood_pcie_map_irq,
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};
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void __init kirkwood_pcie_init(void)
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{
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pci_common_init(&kirkwood_pci);
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}
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