![Mark Langsdorf](/assets/img/avatar_default.png)
When a CPU core is shut down, all of its caches need to be flushed to prevent stale data from causing errors if the core is resumed. Current Linux suspend code performs an assignment after the flush, which can add dirty data back to the cache. On some AMD platforms, additional speculative reads have caused crashes on resume because of this dirty data. Relocate the cache flush to be the very last thing done before halting. Tie into an assembly line so the compile will not reorder it. Add some documentation explaining what is going on and why we're doing this. Signed-off-by: Mark Langsdorf <mark.langsdorf@amd.com> Acked-by: Mark Borden <mark.borden@amd.com> Acked-by: Michael Hohmuth <michael.hohmuth@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
947 lines
22 KiB
C
947 lines
22 KiB
C
#ifndef __ASM_X86_PROCESSOR_H
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#define __ASM_X86_PROCESSOR_H
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#include <asm/processor-flags.h>
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/* Forward declaration, a strange C thing */
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struct task_struct;
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struct mm_struct;
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#include <asm/vm86.h>
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#include <asm/math_emu.h>
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#include <asm/segment.h>
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#include <asm/types.h>
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#include <asm/sigcontext.h>
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#include <asm/current.h>
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#include <asm/cpufeature.h>
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#include <asm/system.h>
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#include <asm/page.h>
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#include <asm/percpu.h>
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#include <asm/msr.h>
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#include <asm/desc_defs.h>
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#include <asm/nops.h>
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#include <linux/personality.h>
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#include <linux/cpumask.h>
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#include <linux/cache.h>
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#include <linux/threads.h>
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#include <linux/init.h>
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/*
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* Default implementation of macro that returns current
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* instruction pointer ("program counter").
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*/
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static inline void *current_text_addr(void)
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{
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void *pc;
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asm volatile("mov $1f, %0; 1:":"=r" (pc));
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return pc;
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}
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#ifdef CONFIG_X86_VSMP
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# define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
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# define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
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#else
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# define ARCH_MIN_TASKALIGN 16
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# define ARCH_MIN_MMSTRUCT_ALIGN 0
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#endif
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/*
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* CPU type and hardware bug flags. Kept separately for each CPU.
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* Members of this structure are referenced in head.S, so think twice
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* before touching them. [mj]
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*/
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struct cpuinfo_x86 {
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__u8 x86; /* CPU family */
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__u8 x86_vendor; /* CPU vendor */
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__u8 x86_model;
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__u8 x86_mask;
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#ifdef CONFIG_X86_32
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char wp_works_ok; /* It doesn't on 386's */
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/* Problems on some 486Dx4's and old 386's: */
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char hlt_works_ok;
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char hard_math;
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char rfu;
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char fdiv_bug;
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char f00f_bug;
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char coma_bug;
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char pad0;
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#else
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/* Number of 4K pages in DTLB/ITLB combined(in pages): */
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int x86_tlbsize;
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__u8 x86_virt_bits;
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__u8 x86_phys_bits;
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/* CPUID returned core id bits: */
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__u8 x86_coreid_bits;
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/* Max extended CPUID function supported: */
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__u32 extended_cpuid_level;
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#endif
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/* Maximum supported CPUID level, -1=no CPUID: */
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int cpuid_level;
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__u32 x86_capability[NCAPINTS];
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char x86_vendor_id[16];
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char x86_model_id[64];
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/* in KB - valid for CPUS which support this call: */
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int x86_cache_size;
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int x86_cache_alignment; /* In bytes */
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int x86_power;
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unsigned long loops_per_jiffy;
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#ifdef CONFIG_SMP
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/* cpus sharing the last level cache: */
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cpumask_t llc_shared_map;
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#endif
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/* cpuid returned max cores value: */
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u16 x86_max_cores;
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u16 apicid;
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u16 initial_apicid;
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u16 x86_clflush_size;
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#ifdef CONFIG_SMP
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/* number of cores as seen by the OS: */
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u16 booted_cores;
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/* Physical processor id: */
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u16 phys_proc_id;
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/* Core id: */
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u16 cpu_core_id;
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/* Index into per_cpu list: */
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u16 cpu_index;
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#endif
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} __attribute__((__aligned__(SMP_CACHE_BYTES)));
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#define X86_VENDOR_INTEL 0
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#define X86_VENDOR_CYRIX 1
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#define X86_VENDOR_AMD 2
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#define X86_VENDOR_UMC 3
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#define X86_VENDOR_CENTAUR 5
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#define X86_VENDOR_TRANSMETA 7
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#define X86_VENDOR_NSC 8
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#define X86_VENDOR_NUM 9
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#define X86_VENDOR_UNKNOWN 0xff
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/*
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* capabilities of CPUs
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*/
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extern struct cpuinfo_x86 boot_cpu_data;
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extern struct cpuinfo_x86 new_cpu_data;
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extern struct tss_struct doublefault_tss;
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extern __u32 cleared_cpu_caps[NCAPINTS];
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#ifdef CONFIG_SMP
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DECLARE_PER_CPU(struct cpuinfo_x86, cpu_info);
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#define cpu_data(cpu) per_cpu(cpu_info, cpu)
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#define current_cpu_data __get_cpu_var(cpu_info)
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#else
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#define cpu_data(cpu) boot_cpu_data
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#define current_cpu_data boot_cpu_data
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#endif
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static inline int hlt_works(int cpu)
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{
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#ifdef CONFIG_X86_32
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return cpu_data(cpu).hlt_works_ok;
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#else
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return 1;
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#endif
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}
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#define cache_line_size() (boot_cpu_data.x86_cache_alignment)
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extern void cpu_detect(struct cpuinfo_x86 *c);
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extern void early_cpu_init(void);
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extern void identify_boot_cpu(void);
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extern void identify_secondary_cpu(struct cpuinfo_x86 *);
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extern void print_cpu_info(struct cpuinfo_x86 *);
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extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
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extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
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extern unsigned short num_cache_leaves;
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#if defined(CONFIG_X86_HT) || defined(CONFIG_X86_64)
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extern void detect_ht(struct cpuinfo_x86 *c);
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#else
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static inline void detect_ht(struct cpuinfo_x86 *c) {}
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#endif
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static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
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unsigned int *ecx, unsigned int *edx)
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{
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/* ecx is often an input as well as an output. */
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asm("cpuid"
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: "=a" (*eax),
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"=b" (*ebx),
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"=c" (*ecx),
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"=d" (*edx)
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: "0" (*eax), "2" (*ecx));
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}
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static inline void load_cr3(pgd_t *pgdir)
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{
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write_cr3(__pa(pgdir));
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}
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#ifdef CONFIG_X86_32
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/* This is the TSS defined by the hardware. */
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struct x86_hw_tss {
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unsigned short back_link, __blh;
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unsigned long sp0;
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unsigned short ss0, __ss0h;
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unsigned long sp1;
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/* ss1 caches MSR_IA32_SYSENTER_CS: */
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unsigned short ss1, __ss1h;
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unsigned long sp2;
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unsigned short ss2, __ss2h;
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unsigned long __cr3;
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unsigned long ip;
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unsigned long flags;
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unsigned long ax;
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unsigned long cx;
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unsigned long dx;
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unsigned long bx;
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unsigned long sp;
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unsigned long bp;
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unsigned long si;
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unsigned long di;
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unsigned short es, __esh;
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unsigned short cs, __csh;
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unsigned short ss, __ssh;
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unsigned short ds, __dsh;
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unsigned short fs, __fsh;
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unsigned short gs, __gsh;
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unsigned short ldt, __ldth;
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unsigned short trace;
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unsigned short io_bitmap_base;
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} __attribute__((packed));
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#else
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struct x86_hw_tss {
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u32 reserved1;
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u64 sp0;
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u64 sp1;
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u64 sp2;
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u64 reserved2;
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u64 ist[7];
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u32 reserved3;
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u32 reserved4;
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u16 reserved5;
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u16 io_bitmap_base;
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} __attribute__((packed)) ____cacheline_aligned;
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#endif
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/*
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* IO-bitmap sizes:
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*/
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#define IO_BITMAP_BITS 65536
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#define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
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#define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
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#define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
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#define INVALID_IO_BITMAP_OFFSET 0x8000
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#define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
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struct tss_struct {
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/*
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* The hardware state:
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*/
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struct x86_hw_tss x86_tss;
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/*
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* The extra 1 is there because the CPU will access an
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* additional byte beyond the end of the IO permission
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* bitmap. The extra byte must be all 1 bits, and must
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* be within the limit.
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*/
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unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
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/*
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* Cache the current maximum and the last task that used the bitmap:
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*/
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unsigned long io_bitmap_max;
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struct thread_struct *io_bitmap_owner;
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/*
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* .. and then another 0x100 bytes for the emergency kernel stack:
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*/
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unsigned long stack[64];
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} ____cacheline_aligned;
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DECLARE_PER_CPU(struct tss_struct, init_tss);
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/*
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* Save the original ist values for checking stack pointers during debugging
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*/
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struct orig_ist {
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unsigned long ist[7];
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};
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#define MXCSR_DEFAULT 0x1f80
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struct i387_fsave_struct {
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u32 cwd; /* FPU Control Word */
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u32 swd; /* FPU Status Word */
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u32 twd; /* FPU Tag Word */
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u32 fip; /* FPU IP Offset */
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u32 fcs; /* FPU IP Selector */
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u32 foo; /* FPU Operand Pointer Offset */
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u32 fos; /* FPU Operand Pointer Selector */
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/* 8*10 bytes for each FP-reg = 80 bytes: */
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u32 st_space[20];
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/* Software status information [not touched by FSAVE ]: */
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u32 status;
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};
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struct i387_fxsave_struct {
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u16 cwd; /* Control Word */
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u16 swd; /* Status Word */
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u16 twd; /* Tag Word */
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u16 fop; /* Last Instruction Opcode */
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union {
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struct {
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u64 rip; /* Instruction Pointer */
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u64 rdp; /* Data Pointer */
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};
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struct {
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u32 fip; /* FPU IP Offset */
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u32 fcs; /* FPU IP Selector */
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u32 foo; /* FPU Operand Offset */
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u32 fos; /* FPU Operand Selector */
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};
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};
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u32 mxcsr; /* MXCSR Register State */
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u32 mxcsr_mask; /* MXCSR Mask */
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/* 8*16 bytes for each FP-reg = 128 bytes: */
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u32 st_space[32];
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/* 16*16 bytes for each XMM-reg = 256 bytes: */
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u32 xmm_space[64];
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u32 padding[24];
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} __attribute__((aligned(16)));
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struct i387_soft_struct {
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u32 cwd;
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u32 swd;
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u32 twd;
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u32 fip;
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u32 fcs;
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u32 foo;
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u32 fos;
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/* 8*10 bytes for each FP-reg = 80 bytes: */
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u32 st_space[20];
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u8 ftop;
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u8 changed;
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u8 lookahead;
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u8 no_update;
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u8 rm;
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u8 alimit;
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struct info *info;
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u32 entry_eip;
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};
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union thread_xstate {
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struct i387_fsave_struct fsave;
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struct i387_fxsave_struct fxsave;
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struct i387_soft_struct soft;
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};
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#ifdef CONFIG_X86_64
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DECLARE_PER_CPU(struct orig_ist, orig_ist);
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#endif
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extern void print_cpu_info(struct cpuinfo_x86 *);
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extern unsigned int xstate_size;
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extern void free_thread_xstate(struct task_struct *);
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extern struct kmem_cache *task_xstate_cachep;
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extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
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extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
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extern unsigned short num_cache_leaves;
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struct thread_struct {
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/* Cached TLS descriptors: */
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struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
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unsigned long sp0;
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unsigned long sp;
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#ifdef CONFIG_X86_32
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unsigned long sysenter_cs;
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#else
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unsigned long usersp; /* Copy from PDA */
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unsigned short es;
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unsigned short ds;
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unsigned short fsindex;
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unsigned short gsindex;
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#endif
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unsigned long ip;
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unsigned long fs;
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unsigned long gs;
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/* Hardware debugging registers: */
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unsigned long debugreg0;
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unsigned long debugreg1;
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unsigned long debugreg2;
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unsigned long debugreg3;
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unsigned long debugreg6;
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unsigned long debugreg7;
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/* Fault info: */
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unsigned long cr2;
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unsigned long trap_no;
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unsigned long error_code;
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/* floating point and extended processor state */
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union thread_xstate *xstate;
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#ifdef CONFIG_X86_32
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/* Virtual 86 mode info */
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struct vm86_struct __user *vm86_info;
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unsigned long screen_bitmap;
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unsigned long v86flags;
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unsigned long v86mask;
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unsigned long saved_sp0;
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unsigned int saved_fs;
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unsigned int saved_gs;
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#endif
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/* IO permissions: */
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unsigned long *io_bitmap_ptr;
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unsigned long iopl;
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/* Max allowed port in the bitmap, in bytes: */
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unsigned io_bitmap_max;
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/* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set. */
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unsigned long debugctlmsr;
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/* Debug Store - if not 0 points to a DS Save Area configuration;
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* goes into MSR_IA32_DS_AREA */
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unsigned long ds_area_msr;
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};
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static inline unsigned long native_get_debugreg(int regno)
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{
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unsigned long val = 0; /* Damn you, gcc! */
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switch (regno) {
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case 0:
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asm("mov %%db0, %0" :"=r" (val));
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break;
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case 1:
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asm("mov %%db1, %0" :"=r" (val));
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break;
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case 2:
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asm("mov %%db2, %0" :"=r" (val));
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break;
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case 3:
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asm("mov %%db3, %0" :"=r" (val));
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break;
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case 6:
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asm("mov %%db6, %0" :"=r" (val));
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break;
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case 7:
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asm("mov %%db7, %0" :"=r" (val));
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break;
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default:
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BUG();
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}
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return val;
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}
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static inline void native_set_debugreg(int regno, unsigned long value)
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{
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switch (regno) {
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case 0:
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asm("mov %0, %%db0" ::"r" (value));
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break;
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case 1:
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asm("mov %0, %%db1" ::"r" (value));
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break;
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case 2:
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asm("mov %0, %%db2" ::"r" (value));
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break;
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case 3:
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asm("mov %0, %%db3" ::"r" (value));
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break;
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case 6:
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asm("mov %0, %%db6" ::"r" (value));
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break;
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case 7:
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asm("mov %0, %%db7" ::"r" (value));
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break;
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default:
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BUG();
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}
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}
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/*
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* Set IOPL bits in EFLAGS from given mask
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*/
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static inline void native_set_iopl_mask(unsigned mask)
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{
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#ifdef CONFIG_X86_32
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unsigned int reg;
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asm volatile ("pushfl;"
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"popl %0;"
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"andl %1, %0;"
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"orl %2, %0;"
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"pushl %0;"
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"popfl"
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: "=&r" (reg)
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: "i" (~X86_EFLAGS_IOPL), "r" (mask));
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#endif
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}
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|
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static inline void
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native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
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{
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tss->x86_tss.sp0 = thread->sp0;
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#ifdef CONFIG_X86_32
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/* Only happens when SEP is enabled, no need to test "SEP"arately: */
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if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
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tss->x86_tss.ss1 = thread->sysenter_cs;
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wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
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}
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#endif
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}
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static inline void native_swapgs(void)
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{
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#ifdef CONFIG_X86_64
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asm volatile("swapgs" ::: "memory");
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#endif
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}
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|
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#ifdef CONFIG_PARAVIRT
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#include <asm/paravirt.h>
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#else
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#define __cpuid native_cpuid
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#define paravirt_enabled() 0
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|
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/*
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|
* These special macros can be used to get or set a debugging register
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*/
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#define get_debugreg(var, register) \
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(var) = native_get_debugreg(register)
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#define set_debugreg(value, register) \
|
|
native_set_debugreg(register, value)
|
|
|
|
static inline void load_sp0(struct tss_struct *tss,
|
|
struct thread_struct *thread)
|
|
{
|
|
native_load_sp0(tss, thread);
|
|
}
|
|
|
|
#define set_iopl_mask native_set_iopl_mask
|
|
#endif /* CONFIG_PARAVIRT */
|
|
|
|
/*
|
|
* Save the cr4 feature set we're using (ie
|
|
* Pentium 4MB enable and PPro Global page
|
|
* enable), so that any CPU's that boot up
|
|
* after us can get the correct flags.
|
|
*/
|
|
extern unsigned long mmu_cr4_features;
|
|
|
|
static inline void set_in_cr4(unsigned long mask)
|
|
{
|
|
unsigned cr4;
|
|
|
|
mmu_cr4_features |= mask;
|
|
cr4 = read_cr4();
|
|
cr4 |= mask;
|
|
write_cr4(cr4);
|
|
}
|
|
|
|
static inline void clear_in_cr4(unsigned long mask)
|
|
{
|
|
unsigned cr4;
|
|
|
|
mmu_cr4_features &= ~mask;
|
|
cr4 = read_cr4();
|
|
cr4 &= ~mask;
|
|
write_cr4(cr4);
|
|
}
|
|
|
|
struct microcode_header {
|
|
unsigned int hdrver;
|
|
unsigned int rev;
|
|
unsigned int date;
|
|
unsigned int sig;
|
|
unsigned int cksum;
|
|
unsigned int ldrver;
|
|
unsigned int pf;
|
|
unsigned int datasize;
|
|
unsigned int totalsize;
|
|
unsigned int reserved[3];
|
|
};
|
|
|
|
struct microcode {
|
|
struct microcode_header hdr;
|
|
unsigned int bits[0];
|
|
};
|
|
|
|
typedef struct microcode microcode_t;
|
|
typedef struct microcode_header microcode_header_t;
|
|
|
|
/* microcode format is extended from prescott processors */
|
|
struct extended_signature {
|
|
unsigned int sig;
|
|
unsigned int pf;
|
|
unsigned int cksum;
|
|
};
|
|
|
|
struct extended_sigtable {
|
|
unsigned int count;
|
|
unsigned int cksum;
|
|
unsigned int reserved[3];
|
|
struct extended_signature sigs[0];
|
|
};
|
|
|
|
typedef struct {
|
|
unsigned long seg;
|
|
} mm_segment_t;
|
|
|
|
|
|
/*
|
|
* create a kernel thread without removing it from tasklists
|
|
*/
|
|
extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
|
|
|
|
/* Free all resources held by a thread. */
|
|
extern void release_thread(struct task_struct *);
|
|
|
|
/* Prepare to copy thread state - unlazy all lazy state */
|
|
extern void prepare_to_copy(struct task_struct *tsk);
|
|
|
|
unsigned long get_wchan(struct task_struct *p);
|
|
|
|
/*
|
|
* Generic CPUID function
|
|
* clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
|
|
* resulting in stale register contents being returned.
|
|
*/
|
|
static inline void cpuid(unsigned int op,
|
|
unsigned int *eax, unsigned int *ebx,
|
|
unsigned int *ecx, unsigned int *edx)
|
|
{
|
|
*eax = op;
|
|
*ecx = 0;
|
|
__cpuid(eax, ebx, ecx, edx);
|
|
}
|
|
|
|
/* Some CPUID calls want 'count' to be placed in ecx */
|
|
static inline void cpuid_count(unsigned int op, int count,
|
|
unsigned int *eax, unsigned int *ebx,
|
|
unsigned int *ecx, unsigned int *edx)
|
|
{
|
|
*eax = op;
|
|
*ecx = count;
|
|
__cpuid(eax, ebx, ecx, edx);
|
|
}
|
|
|
|
/*
|
|
* CPUID functions returning a single datum
|
|
*/
|
|
static inline unsigned int cpuid_eax(unsigned int op)
|
|
{
|
|
unsigned int eax, ebx, ecx, edx;
|
|
|
|
cpuid(op, &eax, &ebx, &ecx, &edx);
|
|
|
|
return eax;
|
|
}
|
|
|
|
static inline unsigned int cpuid_ebx(unsigned int op)
|
|
{
|
|
unsigned int eax, ebx, ecx, edx;
|
|
|
|
cpuid(op, &eax, &ebx, &ecx, &edx);
|
|
|
|
return ebx;
|
|
}
|
|
|
|
static inline unsigned int cpuid_ecx(unsigned int op)
|
|
{
|
|
unsigned int eax, ebx, ecx, edx;
|
|
|
|
cpuid(op, &eax, &ebx, &ecx, &edx);
|
|
|
|
return ecx;
|
|
}
|
|
|
|
static inline unsigned int cpuid_edx(unsigned int op)
|
|
{
|
|
unsigned int eax, ebx, ecx, edx;
|
|
|
|
cpuid(op, &eax, &ebx, &ecx, &edx);
|
|
|
|
return edx;
|
|
}
|
|
|
|
/* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
|
|
static inline void rep_nop(void)
|
|
{
|
|
asm volatile("rep; nop" ::: "memory");
|
|
}
|
|
|
|
static inline void cpu_relax(void)
|
|
{
|
|
rep_nop();
|
|
}
|
|
|
|
/* Stop speculative execution: */
|
|
static inline void sync_core(void)
|
|
{
|
|
int tmp;
|
|
|
|
asm volatile("cpuid" : "=a" (tmp) : "0" (1)
|
|
: "ebx", "ecx", "edx", "memory");
|
|
}
|
|
|
|
static inline void __monitor(const void *eax, unsigned long ecx,
|
|
unsigned long edx)
|
|
{
|
|
/* "monitor %eax, %ecx, %edx;" */
|
|
asm volatile(".byte 0x0f, 0x01, 0xc8;"
|
|
:: "a" (eax), "c" (ecx), "d"(edx));
|
|
}
|
|
|
|
static inline void __mwait(unsigned long eax, unsigned long ecx)
|
|
{
|
|
/* "mwait %eax, %ecx;" */
|
|
asm volatile(".byte 0x0f, 0x01, 0xc9;"
|
|
:: "a" (eax), "c" (ecx));
|
|
}
|
|
|
|
static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
|
|
{
|
|
trace_hardirqs_on();
|
|
/* "mwait %eax, %ecx;" */
|
|
asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
|
|
:: "a" (eax), "c" (ecx));
|
|
}
|
|
|
|
extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
|
|
|
|
extern void select_idle_routine(const struct cpuinfo_x86 *c);
|
|
|
|
extern unsigned long boot_option_idle_override;
|
|
extern unsigned long idle_halt;
|
|
extern unsigned long idle_nomwait;
|
|
|
|
/*
|
|
* on systems with caches, caches must be flashed as the absolute
|
|
* last instruction before going into a suspended halt. Otherwise,
|
|
* dirty data can linger in the cache and become stale on resume,
|
|
* leading to strange errors.
|
|
*
|
|
* perform a variety of operations to guarantee that the compiler
|
|
* will not reorder instructions. wbinvd itself is serializing
|
|
* so the processor will not reorder.
|
|
*
|
|
* Systems without cache can just go into halt.
|
|
*/
|
|
static inline void wbinvd_halt(void)
|
|
{
|
|
mb();
|
|
/* check for clflush to determine if wbinvd is legal */
|
|
if (cpu_has_clflush)
|
|
asm volatile("cli; wbinvd; 1: hlt; jmp 1b" : : : "memory");
|
|
else
|
|
while (1)
|
|
halt();
|
|
}
|
|
|
|
extern void enable_sep_cpu(void);
|
|
extern int sysenter_setup(void);
|
|
|
|
/* Defined in head.S */
|
|
extern struct desc_ptr early_gdt_descr;
|
|
|
|
extern void cpu_set_gdt(int);
|
|
extern void switch_to_new_gdt(void);
|
|
extern void cpu_init(void);
|
|
extern void init_gdt(int cpu);
|
|
|
|
static inline void update_debugctlmsr(unsigned long debugctlmsr)
|
|
{
|
|
#ifndef CONFIG_X86_DEBUGCTLMSR
|
|
if (boot_cpu_data.x86 < 6)
|
|
return;
|
|
#endif
|
|
wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
|
|
}
|
|
|
|
/*
|
|
* from system description table in BIOS. Mostly for MCA use, but
|
|
* others may find it useful:
|
|
*/
|
|
extern unsigned int machine_id;
|
|
extern unsigned int machine_submodel_id;
|
|
extern unsigned int BIOS_revision;
|
|
|
|
/* Boot loader type from the setup header: */
|
|
extern int bootloader_type;
|
|
|
|
extern char ignore_fpu_irq;
|
|
|
|
#define HAVE_ARCH_PICK_MMAP_LAYOUT 1
|
|
#define ARCH_HAS_PREFETCHW
|
|
#define ARCH_HAS_SPINLOCK_PREFETCH
|
|
|
|
#ifdef CONFIG_X86_32
|
|
# define BASE_PREFETCH ASM_NOP4
|
|
# define ARCH_HAS_PREFETCH
|
|
#else
|
|
# define BASE_PREFETCH "prefetcht0 (%1)"
|
|
#endif
|
|
|
|
/*
|
|
* Prefetch instructions for Pentium III (+) and AMD Athlon (+)
|
|
*
|
|
* It's not worth to care about 3dnow prefetches for the K6
|
|
* because they are microcoded there and very slow.
|
|
*/
|
|
static inline void prefetch(const void *x)
|
|
{
|
|
alternative_input(BASE_PREFETCH,
|
|
"prefetchnta (%1)",
|
|
X86_FEATURE_XMM,
|
|
"r" (x));
|
|
}
|
|
|
|
/*
|
|
* 3dnow prefetch to get an exclusive cache line.
|
|
* Useful for spinlocks to avoid one state transition in the
|
|
* cache coherency protocol:
|
|
*/
|
|
static inline void prefetchw(const void *x)
|
|
{
|
|
alternative_input(BASE_PREFETCH,
|
|
"prefetchw (%1)",
|
|
X86_FEATURE_3DNOW,
|
|
"r" (x));
|
|
}
|
|
|
|
static inline void spin_lock_prefetch(const void *x)
|
|
{
|
|
prefetchw(x);
|
|
}
|
|
|
|
#ifdef CONFIG_X86_32
|
|
/*
|
|
* User space process size: 3GB (default).
|
|
*/
|
|
#define TASK_SIZE PAGE_OFFSET
|
|
#define STACK_TOP TASK_SIZE
|
|
#define STACK_TOP_MAX STACK_TOP
|
|
|
|
#define INIT_THREAD { \
|
|
.sp0 = sizeof(init_stack) + (long)&init_stack, \
|
|
.vm86_info = NULL, \
|
|
.sysenter_cs = __KERNEL_CS, \
|
|
.io_bitmap_ptr = NULL, \
|
|
.fs = __KERNEL_PERCPU, \
|
|
}
|
|
|
|
/*
|
|
* Note that the .io_bitmap member must be extra-big. This is because
|
|
* the CPU will access an additional byte beyond the end of the IO
|
|
* permission bitmap. The extra byte must be all 1 bits, and must
|
|
* be within the limit.
|
|
*/
|
|
#define INIT_TSS { \
|
|
.x86_tss = { \
|
|
.sp0 = sizeof(init_stack) + (long)&init_stack, \
|
|
.ss0 = __KERNEL_DS, \
|
|
.ss1 = __KERNEL_CS, \
|
|
.io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
|
|
}, \
|
|
.io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \
|
|
}
|
|
|
|
extern unsigned long thread_saved_pc(struct task_struct *tsk);
|
|
|
|
#define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
|
|
#define KSTK_TOP(info) \
|
|
({ \
|
|
unsigned long *__ptr = (unsigned long *)(info); \
|
|
(unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
|
|
})
|
|
|
|
/*
|
|
* The below -8 is to reserve 8 bytes on top of the ring0 stack.
|
|
* This is necessary to guarantee that the entire "struct pt_regs"
|
|
* is accessable even if the CPU haven't stored the SS/ESP registers
|
|
* on the stack (interrupt gate does not save these registers
|
|
* when switching to the same priv ring).
|
|
* Therefore beware: accessing the ss/esp fields of the
|
|
* "struct pt_regs" is possible, but they may contain the
|
|
* completely wrong values.
|
|
*/
|
|
#define task_pt_regs(task) \
|
|
({ \
|
|
struct pt_regs *__regs__; \
|
|
__regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
|
|
__regs__ - 1; \
|
|
})
|
|
|
|
#define KSTK_ESP(task) (task_pt_regs(task)->sp)
|
|
|
|
#else
|
|
/*
|
|
* User space process size. 47bits minus one guard page.
|
|
*/
|
|
#define TASK_SIZE64 ((1UL << 47) - PAGE_SIZE)
|
|
|
|
/* This decides where the kernel will search for a free chunk of vm
|
|
* space during mmap's.
|
|
*/
|
|
#define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
|
|
0xc0000000 : 0xFFFFe000)
|
|
|
|
#define TASK_SIZE (test_thread_flag(TIF_IA32) ? \
|
|
IA32_PAGE_OFFSET : TASK_SIZE64)
|
|
#define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_IA32)) ? \
|
|
IA32_PAGE_OFFSET : TASK_SIZE64)
|
|
|
|
#define STACK_TOP TASK_SIZE
|
|
#define STACK_TOP_MAX TASK_SIZE64
|
|
|
|
#define INIT_THREAD { \
|
|
.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
|
|
}
|
|
|
|
#define INIT_TSS { \
|
|
.x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
|
|
}
|
|
|
|
/*
|
|
* Return saved PC of a blocked thread.
|
|
* What is this good for? it will be always the scheduler or ret_from_fork.
|
|
*/
|
|
#define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8))
|
|
|
|
#define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
|
|
#define KSTK_ESP(tsk) -1 /* sorry. doesn't work for syscall. */
|
|
#endif /* CONFIG_X86_64 */
|
|
|
|
extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
|
|
unsigned long new_sp);
|
|
|
|
/*
|
|
* This decides where the kernel will search for a free chunk of vm
|
|
* space during mmap's.
|
|
*/
|
|
#define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
|
|
|
|
#define KSTK_EIP(task) (task_pt_regs(task)->ip)
|
|
|
|
/* Get/set a process' ability to use the timestamp counter instruction */
|
|
#define GET_TSC_CTL(adr) get_tsc_mode((adr))
|
|
#define SET_TSC_CTL(val) set_tsc_mode((val))
|
|
|
|
extern int get_tsc_mode(unsigned long adr);
|
|
extern int set_tsc_mode(unsigned int val);
|
|
|
|
#endif
|