afa9fdc2f5
This patch against tip/x86/iommu virtually reverts
2842e5bf31. But just reverting the
commit breaks AMD IOMMU so this patch also includes some fixes.
The above commit adds new two options to x86 IOMMU generic kernel boot
options, fullflush and nofullflush. But such change that affects all
the IOMMUs needs more discussion (all IOMMU parties need the chance to
discuss it):
http://lkml.org/lkml/2008/9/19/106
Signed-off-by: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp>
Acked-by: Joerg Roedel <joerg.roedel@amd.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
405 lines
11 KiB
C
405 lines
11 KiB
C
/*
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* Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
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* Author: Joerg Roedel <joerg.roedel@amd.com>
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* Leo Duran <leo.duran@amd.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __AMD_IOMMU_TYPES_H__
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#define __AMD_IOMMU_TYPES_H__
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#include <linux/types.h>
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#include <linux/list.h>
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#include <linux/spinlock.h>
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/*
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* some size calculation constants
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*/
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#define DEV_TABLE_ENTRY_SIZE 32
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#define ALIAS_TABLE_ENTRY_SIZE 2
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#define RLOOKUP_TABLE_ENTRY_SIZE (sizeof(void *))
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/* Length of the MMIO region for the AMD IOMMU */
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#define MMIO_REGION_LENGTH 0x4000
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/* Capability offsets used by the driver */
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#define MMIO_CAP_HDR_OFFSET 0x00
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#define MMIO_RANGE_OFFSET 0x0c
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#define MMIO_MISC_OFFSET 0x10
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/* Masks, shifts and macros to parse the device range capability */
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#define MMIO_RANGE_LD_MASK 0xff000000
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#define MMIO_RANGE_FD_MASK 0x00ff0000
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#define MMIO_RANGE_BUS_MASK 0x0000ff00
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#define MMIO_RANGE_LD_SHIFT 24
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#define MMIO_RANGE_FD_SHIFT 16
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#define MMIO_RANGE_BUS_SHIFT 8
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#define MMIO_GET_LD(x) (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT)
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#define MMIO_GET_FD(x) (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT)
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#define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT)
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#define MMIO_MSI_NUM(x) ((x) & 0x1f)
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/* Flag masks for the AMD IOMMU exclusion range */
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#define MMIO_EXCL_ENABLE_MASK 0x01ULL
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#define MMIO_EXCL_ALLOW_MASK 0x02ULL
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/* Used offsets into the MMIO space */
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#define MMIO_DEV_TABLE_OFFSET 0x0000
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#define MMIO_CMD_BUF_OFFSET 0x0008
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#define MMIO_EVT_BUF_OFFSET 0x0010
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#define MMIO_CONTROL_OFFSET 0x0018
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#define MMIO_EXCL_BASE_OFFSET 0x0020
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#define MMIO_EXCL_LIMIT_OFFSET 0x0028
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#define MMIO_CMD_HEAD_OFFSET 0x2000
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#define MMIO_CMD_TAIL_OFFSET 0x2008
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#define MMIO_EVT_HEAD_OFFSET 0x2010
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#define MMIO_EVT_TAIL_OFFSET 0x2018
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#define MMIO_STATUS_OFFSET 0x2020
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/* MMIO status bits */
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#define MMIO_STATUS_COM_WAIT_INT_MASK 0x04
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/* event logging constants */
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#define EVENT_ENTRY_SIZE 0x10
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#define EVENT_TYPE_SHIFT 28
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#define EVENT_TYPE_MASK 0xf
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#define EVENT_TYPE_ILL_DEV 0x1
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#define EVENT_TYPE_IO_FAULT 0x2
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#define EVENT_TYPE_DEV_TAB_ERR 0x3
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#define EVENT_TYPE_PAGE_TAB_ERR 0x4
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#define EVENT_TYPE_ILL_CMD 0x5
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#define EVENT_TYPE_CMD_HARD_ERR 0x6
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#define EVENT_TYPE_IOTLB_INV_TO 0x7
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#define EVENT_TYPE_INV_DEV_REQ 0x8
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#define EVENT_DEVID_MASK 0xffff
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#define EVENT_DEVID_SHIFT 0
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#define EVENT_DOMID_MASK 0xffff
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#define EVENT_DOMID_SHIFT 0
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#define EVENT_FLAGS_MASK 0xfff
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#define EVENT_FLAGS_SHIFT 0x10
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/* feature control bits */
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#define CONTROL_IOMMU_EN 0x00ULL
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#define CONTROL_HT_TUN_EN 0x01ULL
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#define CONTROL_EVT_LOG_EN 0x02ULL
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#define CONTROL_EVT_INT_EN 0x03ULL
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#define CONTROL_COMWAIT_EN 0x04ULL
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#define CONTROL_PASSPW_EN 0x08ULL
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#define CONTROL_RESPASSPW_EN 0x09ULL
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#define CONTROL_COHERENT_EN 0x0aULL
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#define CONTROL_ISOC_EN 0x0bULL
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#define CONTROL_CMDBUF_EN 0x0cULL
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#define CONTROL_PPFLOG_EN 0x0dULL
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#define CONTROL_PPFINT_EN 0x0eULL
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/* command specific defines */
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#define CMD_COMPL_WAIT 0x01
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#define CMD_INV_DEV_ENTRY 0x02
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#define CMD_INV_IOMMU_PAGES 0x03
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#define CMD_COMPL_WAIT_STORE_MASK 0x01
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#define CMD_COMPL_WAIT_INT_MASK 0x02
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#define CMD_INV_IOMMU_PAGES_SIZE_MASK 0x01
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#define CMD_INV_IOMMU_PAGES_PDE_MASK 0x02
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#define CMD_INV_IOMMU_ALL_PAGES_ADDRESS 0x7fffffffffffffffULL
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/* macros and definitions for device table entries */
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#define DEV_ENTRY_VALID 0x00
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#define DEV_ENTRY_TRANSLATION 0x01
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#define DEV_ENTRY_IR 0x3d
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#define DEV_ENTRY_IW 0x3e
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#define DEV_ENTRY_NO_PAGE_FAULT 0x62
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#define DEV_ENTRY_EX 0x67
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#define DEV_ENTRY_SYSMGT1 0x68
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#define DEV_ENTRY_SYSMGT2 0x69
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#define DEV_ENTRY_INIT_PASS 0xb8
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#define DEV_ENTRY_EINT_PASS 0xb9
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#define DEV_ENTRY_NMI_PASS 0xba
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#define DEV_ENTRY_LINT0_PASS 0xbe
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#define DEV_ENTRY_LINT1_PASS 0xbf
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#define DEV_ENTRY_MODE_MASK 0x07
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#define DEV_ENTRY_MODE_SHIFT 0x09
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/* constants to configure the command buffer */
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#define CMD_BUFFER_SIZE 8192
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#define CMD_BUFFER_ENTRIES 512
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#define MMIO_CMD_SIZE_SHIFT 56
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#define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT)
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/* constants for event buffer handling */
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#define EVT_BUFFER_SIZE 8192 /* 512 entries */
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#define EVT_LEN_MASK (0x9ULL << 56)
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#define PAGE_MODE_1_LEVEL 0x01
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#define PAGE_MODE_2_LEVEL 0x02
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#define PAGE_MODE_3_LEVEL 0x03
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#define IOMMU_PDE_NL_0 0x000ULL
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#define IOMMU_PDE_NL_1 0x200ULL
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#define IOMMU_PDE_NL_2 0x400ULL
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#define IOMMU_PDE_NL_3 0x600ULL
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#define IOMMU_PTE_L2_INDEX(address) (((address) >> 30) & 0x1ffULL)
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#define IOMMU_PTE_L1_INDEX(address) (((address) >> 21) & 0x1ffULL)
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#define IOMMU_PTE_L0_INDEX(address) (((address) >> 12) & 0x1ffULL)
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#define IOMMU_MAP_SIZE_L1 (1ULL << 21)
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#define IOMMU_MAP_SIZE_L2 (1ULL << 30)
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#define IOMMU_MAP_SIZE_L3 (1ULL << 39)
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#define IOMMU_PTE_P (1ULL << 0)
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#define IOMMU_PTE_TV (1ULL << 1)
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#define IOMMU_PTE_U (1ULL << 59)
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#define IOMMU_PTE_FC (1ULL << 60)
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#define IOMMU_PTE_IR (1ULL << 61)
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#define IOMMU_PTE_IW (1ULL << 62)
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#define IOMMU_L1_PDE(address) \
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((address) | IOMMU_PDE_NL_1 | IOMMU_PTE_P | IOMMU_PTE_IR | IOMMU_PTE_IW)
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#define IOMMU_L2_PDE(address) \
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((address) | IOMMU_PDE_NL_2 | IOMMU_PTE_P | IOMMU_PTE_IR | IOMMU_PTE_IW)
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#define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL)
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#define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_P)
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#define IOMMU_PTE_PAGE(pte) (phys_to_virt((pte) & IOMMU_PAGE_MASK))
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#define IOMMU_PTE_MODE(pte) (((pte) >> 9) & 0x07)
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#define IOMMU_PROT_MASK 0x03
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#define IOMMU_PROT_IR 0x01
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#define IOMMU_PROT_IW 0x02
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/* IOMMU capabilities */
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#define IOMMU_CAP_IOTLB 24
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#define IOMMU_CAP_NPCACHE 26
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#define MAX_DOMAIN_ID 65536
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/* FIXME: move this macro to <linux/pci.h> */
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#define PCI_BUS(x) (((x) >> 8) & 0xff)
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/*
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* This structure contains generic data for IOMMU protection domains
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* independent of their use.
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*/
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struct protection_domain {
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spinlock_t lock; /* mostly used to lock the page table*/
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u16 id; /* the domain id written to the device table */
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int mode; /* paging mode (0-6 levels) */
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u64 *pt_root; /* page table root pointer */
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void *priv; /* private data */
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};
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/*
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* Data container for a dma_ops specific protection domain
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*/
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struct dma_ops_domain {
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struct list_head list;
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/* generic protection domain information */
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struct protection_domain domain;
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/* size of the aperture for the mappings */
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unsigned long aperture_size;
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/* address we start to search for free addresses */
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unsigned long next_bit;
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/* address allocation bitmap */
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unsigned long *bitmap;
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/*
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* Array of PTE pages for the aperture. In this array we save all the
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* leaf pages of the domain page table used for the aperture. This way
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* we don't need to walk the page table to find a specific PTE. We can
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* just calculate its address in constant time.
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*/
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u64 **pte_pages;
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/* This will be set to true when TLB needs to be flushed */
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bool need_flush;
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/*
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* if this is a preallocated domain, keep the device for which it was
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* preallocated in this variable
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*/
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u16 target_dev;
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};
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/*
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* Structure where we save information about one hardware AMD IOMMU in the
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* system.
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*/
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struct amd_iommu {
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struct list_head list;
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/* locks the accesses to the hardware */
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spinlock_t lock;
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/* Pointer to PCI device of this IOMMU */
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struct pci_dev *dev;
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/*
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* Capability pointer. There could be more than one IOMMU per PCI
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* device function if there are more than one AMD IOMMU capability
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* pointers.
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*/
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u16 cap_ptr;
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/* physical address of MMIO space */
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u64 mmio_phys;
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/* virtual address of MMIO space */
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u8 *mmio_base;
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/* capabilities of that IOMMU read from ACPI */
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u32 cap;
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/* pci domain of this IOMMU */
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u16 pci_seg;
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/* first device this IOMMU handles. read from PCI */
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u16 first_device;
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/* last device this IOMMU handles. read from PCI */
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u16 last_device;
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/* start of exclusion range of that IOMMU */
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u64 exclusion_start;
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/* length of exclusion range of that IOMMU */
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u64 exclusion_length;
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/* command buffer virtual address */
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u8 *cmd_buf;
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/* size of command buffer */
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u32 cmd_buf_size;
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/* event buffer virtual address */
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u8 *evt_buf;
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/* size of event buffer */
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u32 evt_buf_size;
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/* MSI number for event interrupt */
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u16 evt_msi_num;
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/* if one, we need to send a completion wait command */
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int need_sync;
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/* true if interrupts for this IOMMU are already enabled */
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bool int_enabled;
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/* default dma_ops domain for that IOMMU */
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struct dma_ops_domain *default_dom;
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};
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/*
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* List with all IOMMUs in the system. This list is not locked because it is
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* only written and read at driver initialization or suspend time
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*/
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extern struct list_head amd_iommu_list;
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/*
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* Structure defining one entry in the device table
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*/
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struct dev_table_entry {
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u32 data[8];
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};
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/*
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* One entry for unity mappings parsed out of the ACPI table.
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*/
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struct unity_map_entry {
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struct list_head list;
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/* starting device id this entry is used for (including) */
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u16 devid_start;
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/* end device id this entry is used for (including) */
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u16 devid_end;
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/* start address to unity map (including) */
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u64 address_start;
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/* end address to unity map (including) */
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u64 address_end;
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/* required protection */
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int prot;
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};
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/*
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* List of all unity mappings. It is not locked because as runtime it is only
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* read. It is created at ACPI table parsing time.
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*/
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extern struct list_head amd_iommu_unity_map;
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/*
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* Data structures for device handling
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*/
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/*
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* Device table used by hardware. Read and write accesses by software are
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* locked with the amd_iommu_pd_table lock.
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*/
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extern struct dev_table_entry *amd_iommu_dev_table;
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/*
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* Alias table to find requestor ids to device ids. Not locked because only
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* read on runtime.
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*/
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extern u16 *amd_iommu_alias_table;
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/*
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* Reverse lookup table to find the IOMMU which translates a specific device.
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*/
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extern struct amd_iommu **amd_iommu_rlookup_table;
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/* size of the dma_ops aperture as power of 2 */
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extern unsigned amd_iommu_aperture_order;
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/* largest PCI device id we expect translation requests for */
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extern u16 amd_iommu_last_bdf;
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/* data structures for protection domain handling */
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extern struct protection_domain **amd_iommu_pd_table;
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/* allocation bitmap for domain ids */
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extern unsigned long *amd_iommu_pd_alloc_bitmap;
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/* will be 1 if device isolation is enabled */
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extern int amd_iommu_isolate;
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/*
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* If true, the addresses will be flushed on unmap time, not when
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* they are reused
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*/
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extern bool amd_iommu_unmap_flush;
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/* takes a PCI device id and prints it out in a readable form */
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static inline void print_devid(u16 devid, int nl)
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{
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int bus = devid >> 8;
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int dev = devid >> 3 & 0x1f;
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int fn = devid & 0x07;
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printk("%02x:%02x.%x", bus, dev, fn);
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if (nl)
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printk("\n");
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}
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/* takes bus and device/function and returns the device id
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* FIXME: should that be in generic PCI code? */
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static inline u16 calc_devid(u8 bus, u8 devfn)
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{
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return (((u16)bus) << 8) | devfn;
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}
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#endif
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