621dd24743
The GPIOs on ports C/D/E on the BF538/BF539 do not behave the same way as the other ports on the part and the same way as all other Blackfin parts. The MMRs are programmed slightly different and they cannot be used to generate interrupts or wakeup a sleeping system. Since these guys don't fit into the existing code, create a simple gpiolib driver for them. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
114 lines
4.1 KiB
C
114 lines
4.1 KiB
C
/*
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* Copyright 2008-2009 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#ifndef _MACH_PORTMUX_H_
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#define _MACH_PORTMUX_H_
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#define MAX_RESOURCES 64
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#define P_TMR2 (P_DONTCARE)
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#define P_TMR1 (P_DONTCARE)
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#define P_TMR0 (P_DONTCARE)
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#define P_TMRCLK (P_DONTCARE)
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#define P_PPI0_CLK (P_DONTCARE)
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#define P_PPI0_FS1 (P_DONTCARE)
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#define P_PPI0_FS2 (P_DONTCARE)
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#define P_TWI0_SCL (P_DONTCARE)
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#define P_TWI0_SDA (P_DONTCARE)
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#define P_TWI1_SCL (P_DONTCARE)
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#define P_TWI1_SDA (P_DONTCARE)
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#define P_SPORT1_TSCLK (P_DONTCARE)
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#define P_SPORT1_RSCLK (P_DONTCARE)
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#define P_SPORT0_TSCLK (P_DONTCARE)
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#define P_SPORT0_RSCLK (P_DONTCARE)
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#define P_SPORT1_DRSEC (P_DONTCARE)
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#define P_SPORT1_RFS (P_DONTCARE)
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#define P_SPORT1_DTPRI (P_DONTCARE)
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#define P_SPORT1_DTSEC (P_DONTCARE)
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#define P_SPORT1_TFS (P_DONTCARE)
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#define P_SPORT1_DRPRI (P_DONTCARE)
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#define P_SPORT0_DRSEC (P_DONTCARE)
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#define P_SPORT0_RFS (P_DONTCARE)
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#define P_SPORT0_DTPRI (P_DONTCARE)
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#define P_SPORT0_DTSEC (P_DONTCARE)
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#define P_SPORT0_TFS (P_DONTCARE)
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#define P_SPORT0_DRPRI (P_DONTCARE)
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#define P_UART0_RX (P_DONTCARE)
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#define P_UART0_TX (P_DONTCARE)
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#define P_SPI0_MOSI (P_DONTCARE)
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#define P_SPI0_MISO (P_DONTCARE)
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#define P_SPI0_SCK (P_DONTCARE)
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#define P_PPI0_D0 (P_DONTCARE)
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#define P_PPI0_D1 (P_DONTCARE)
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#define P_PPI0_D2 (P_DONTCARE)
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#define P_PPI0_D3 (P_DONTCARE)
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#define P_CAN0_TX (P_DEFINED | P_IDENT(GPIO_PC0))
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#define P_CAN0_RX (P_DEFINED | P_IDENT(GPIO_PC1))
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#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PD0))
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#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PD1))
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#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PD2))
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#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PD3))
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#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PD4))
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#define P_SPI2_MOSI (P_DEFINED | P_IDENT(GPIO_PD5))
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#define P_SPI2_MISO (P_DEFINED | P_IDENT(GPIO_PD6))
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#define P_SPI2_SCK (P_DEFINED | P_IDENT(GPIO_PD7))
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#define P_SPI2_SS (P_DEFINED | P_IDENT(GPIO_PD8))
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#define P_SPI2_SSEL1 (P_DEFINED | P_IDENT(GPIO_PD9))
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#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PD10))
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#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PD11))
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#define P_UART2_RX (P_DEFINED | P_IDENT(GPIO_PD12))
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#define P_UART2_TX (P_DEFINED | P_IDENT(GPIO_PD13))
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#define P_SPORT2_RSCLK (P_DEFINED | P_IDENT(GPIO_PE0))
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#define P_SPORT2_RFS (P_DEFINED | P_IDENT(GPIO_PE1))
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#define P_SPORT2_DRPRI (P_DEFINED | P_IDENT(GPIO_PE2))
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#define P_SPORT2_DRSEC (P_DEFINED | P_IDENT(GPIO_PE3))
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#define P_SPORT2_TSCLK (P_DEFINED | P_IDENT(GPIO_PE4))
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#define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PE5))
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#define P_SPORT2_DTPRI (P_DEFINED | P_IDENT(GPIO_PE6))
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#define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PE7))
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#define P_SPORT3_RSCLK (P_DEFINED | P_IDENT(GPIO_PE8))
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#define P_SPORT3_RFS (P_DEFINED | P_IDENT(GPIO_PE9))
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#define P_SPORT3_DRPRI (P_DEFINED | P_IDENT(GPIO_PE10))
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#define P_SPORT3_DRSEC (P_DEFINED | P_IDENT(GPIO_PE11))
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#define P_SPORT3_TSCLK (P_DEFINED | P_IDENT(GPIO_PE12))
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#define P_SPORT3_TFS (P_DEFINED | P_IDENT(GPIO_PE13))
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#define P_SPORT3_DTPRI (P_DEFINED | P_IDENT(GPIO_PE14))
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#define P_SPORT3_DTSEC (P_DEFINED | P_IDENT(GPIO_PE15))
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#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PF3))
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#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF4))
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#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF5))
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#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF6))
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#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF7))
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#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF8))
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#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF9))
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#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF10))
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#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF11))
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#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF15))
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#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF14))
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#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF13))
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#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF12))
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#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7))
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#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6))
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#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5))
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#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4))
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#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3))
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#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2))
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#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1))
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#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0))
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#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
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#endif /* _MACH_PORTMUX_H_ */
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