![Hannes Eder](/assets/img/avatar_default.png)
Impact: Remove redundant variables. Fix this sparse warnings: drivers/net/tokenring/lanstreamer.c:619:21: warning: symbol 'i' shadows an earlier one drivers/net/tokenring/lanstreamer.c:589:13: originally declared here drivers/net/tokenring/madgemc.c:695:34: warning: symbol 'tp' shadows an earlier one drivers/net/tokenring/madgemc.c:689:26: originally declared here drivers/net/tokenring/olympic.c:702:21: warning: symbol 'i' shadows an earlier one drivers/net/tokenring/olympic.c:440:13: originally declared here Signed-off-by: Hannes Eder <hannes@hanneseder.net> Signed-off-by: David S. Miller <davem@davemloft.net>
774 lines
20 KiB
C
774 lines
20 KiB
C
/*
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* madgemc.c: Driver for the Madge Smart 16/4 MC16 MCA token ring card.
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*
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* Written 2000 by Adam Fritzler
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*
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* This software may be used and distributed according to the terms
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* of the GNU General Public License, incorporated herein by reference.
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*
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* This driver module supports the following cards:
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* - Madge Smart 16/4 Ringnode MC16
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* - Madge Smart 16/4 Ringnode MC32 (??)
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*
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* Maintainer(s):
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* AF Adam Fritzler
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*
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* Modification History:
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* 16-Jan-00 AF Created
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*
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*/
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static const char version[] = "madgemc.c: v0.91 23/01/2000 by Adam Fritzler\n";
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#include <linux/module.h>
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#include <linux/mca.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/netdevice.h>
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#include <linux/trdevice.h>
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#include <asm/system.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include "tms380tr.h"
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#include "madgemc.h" /* Madge-specific constants */
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#define MADGEMC_IO_EXTENT 32
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#define MADGEMC_SIF_OFFSET 0x08
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struct card_info {
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/*
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* These are read from the BIA ROM.
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*/
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unsigned int manid;
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unsigned int cardtype;
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unsigned int cardrev;
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unsigned int ramsize;
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/*
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* These are read from the MCA POS registers.
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*/
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unsigned int burstmode:2;
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unsigned int fairness:1; /* 0 = Fair, 1 = Unfair */
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unsigned int arblevel:4;
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unsigned int ringspeed:2; /* 0 = 4mb, 1 = 16, 2 = Auto/none */
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unsigned int cabletype:1; /* 0 = RJ45, 1 = DB9 */
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};
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static int madgemc_open(struct net_device *dev);
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static int madgemc_close(struct net_device *dev);
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static int madgemc_chipset_init(struct net_device *dev);
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static void madgemc_read_rom(struct net_device *dev, struct card_info *card);
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static unsigned short madgemc_setnselout_pins(struct net_device *dev);
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static void madgemc_setcabletype(struct net_device *dev, int type);
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static int madgemc_mcaproc(char *buf, int slot, void *d);
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static void madgemc_setregpage(struct net_device *dev, int page);
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static void madgemc_setsifsel(struct net_device *dev, int val);
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static void madgemc_setint(struct net_device *dev, int val);
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static irqreturn_t madgemc_interrupt(int irq, void *dev_id);
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/*
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* These work around paging, however they don't guarentee you're on the
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* right page.
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*/
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#define SIFREADB(reg) (inb(dev->base_addr + ((reg<0x8)?reg:reg-0x8)))
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#define SIFWRITEB(val, reg) (outb(val, dev->base_addr + ((reg<0x8)?reg:reg-0x8)))
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#define SIFREADW(reg) (inw(dev->base_addr + ((reg<0x8)?reg:reg-0x8)))
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#define SIFWRITEW(val, reg) (outw(val, dev->base_addr + ((reg<0x8)?reg:reg-0x8)))
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/*
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* Read a byte-length value from the register.
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*/
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static unsigned short madgemc_sifreadb(struct net_device *dev, unsigned short reg)
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{
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unsigned short ret;
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if (reg<0x8)
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ret = SIFREADB(reg);
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else {
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madgemc_setregpage(dev, 1);
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ret = SIFREADB(reg);
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madgemc_setregpage(dev, 0);
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}
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return ret;
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}
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/*
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* Write a byte-length value to a register.
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*/
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static void madgemc_sifwriteb(struct net_device *dev, unsigned short val, unsigned short reg)
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{
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if (reg<0x8)
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SIFWRITEB(val, reg);
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else {
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madgemc_setregpage(dev, 1);
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SIFWRITEB(val, reg);
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madgemc_setregpage(dev, 0);
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}
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return;
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}
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/*
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* Read a word-length value from a register
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*/
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static unsigned short madgemc_sifreadw(struct net_device *dev, unsigned short reg)
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{
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unsigned short ret;
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if (reg<0x8)
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ret = SIFREADW(reg);
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else {
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madgemc_setregpage(dev, 1);
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ret = SIFREADW(reg);
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madgemc_setregpage(dev, 0);
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}
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return ret;
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}
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/*
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* Write a word-length value to a register.
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*/
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static void madgemc_sifwritew(struct net_device *dev, unsigned short val, unsigned short reg)
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{
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if (reg<0x8)
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SIFWRITEW(val, reg);
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else {
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madgemc_setregpage(dev, 1);
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SIFWRITEW(val, reg);
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madgemc_setregpage(dev, 0);
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}
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return;
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}
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static int __devinit madgemc_probe(struct device *device)
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{
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static int versionprinted;
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struct net_device *dev;
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struct net_local *tp;
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struct card_info *card;
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struct mca_device *mdev = to_mca_device(device);
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int ret = 0;
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if (versionprinted++ == 0)
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printk("%s", version);
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if(mca_device_claimed(mdev))
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return -EBUSY;
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mca_device_set_claim(mdev, 1);
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dev = alloc_trdev(sizeof(struct net_local));
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if (!dev) {
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printk("madgemc: unable to allocate dev space\n");
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mca_device_set_claim(mdev, 0);
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ret = -ENOMEM;
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goto getout;
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}
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dev->dma = 0;
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card = kmalloc(sizeof(struct card_info), GFP_KERNEL);
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if (card==NULL) {
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printk("madgemc: unable to allocate card struct\n");
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ret = -ENOMEM;
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goto getout1;
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}
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/*
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* Parse configuration information. This all comes
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* directly from the publicly available @002d.ADF.
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* Get it from Madge or your local ADF library.
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*/
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/*
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* Base address
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*/
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dev->base_addr = 0x0a20 +
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((mdev->pos[2] & MC16_POS2_ADDR2)?0x0400:0) +
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((mdev->pos[0] & MC16_POS0_ADDR1)?0x1000:0) +
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((mdev->pos[3] & MC16_POS3_ADDR3)?0x2000:0);
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/*
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* Interrupt line
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*/
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switch(mdev->pos[0] >> 6) { /* upper two bits */
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case 0x1: dev->irq = 3; break;
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case 0x2: dev->irq = 9; break; /* IRQ 2 = IRQ 9 */
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case 0x3: dev->irq = 10; break;
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default: dev->irq = 0; break;
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}
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if (dev->irq == 0) {
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printk("%s: invalid IRQ\n", dev->name);
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ret = -EBUSY;
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goto getout2;
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}
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if (!request_region(dev->base_addr, MADGEMC_IO_EXTENT,
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"madgemc")) {
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printk(KERN_INFO "madgemc: unable to setup Smart MC in slot %d because of I/O base conflict at 0x%04lx\n", mdev->slot, dev->base_addr);
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dev->base_addr += MADGEMC_SIF_OFFSET;
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ret = -EBUSY;
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goto getout2;
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}
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dev->base_addr += MADGEMC_SIF_OFFSET;
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/*
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* Arbitration Level
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*/
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card->arblevel = ((mdev->pos[0] >> 1) & 0x7) + 8;
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/*
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* Burst mode and Fairness
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*/
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card->burstmode = ((mdev->pos[2] >> 6) & 0x3);
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card->fairness = ((mdev->pos[2] >> 4) & 0x1);
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/*
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* Ring Speed
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*/
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if ((mdev->pos[1] >> 2)&0x1)
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card->ringspeed = 2; /* not selected */
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else if ((mdev->pos[2] >> 5) & 0x1)
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card->ringspeed = 1; /* 16Mb */
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else
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card->ringspeed = 0; /* 4Mb */
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/*
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* Cable type
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*/
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if ((mdev->pos[1] >> 6)&0x1)
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card->cabletype = 1; /* STP/DB9 */
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else
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card->cabletype = 0; /* UTP/RJ-45 */
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/*
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* ROM Info. This requires us to actually twiddle
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* bits on the card, so we must ensure above that
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* the base address is free of conflict (request_region above).
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*/
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madgemc_read_rom(dev, card);
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if (card->manid != 0x4d) { /* something went wrong */
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printk(KERN_INFO "%s: Madge MC ROM read failed (unknown manufacturer ID %02x)\n", dev->name, card->manid);
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goto getout3;
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}
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if ((card->cardtype != 0x08) && (card->cardtype != 0x0d)) {
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printk(KERN_INFO "%s: Madge MC ROM read failed (unknown card ID %02x)\n", dev->name, card->cardtype);
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ret = -EIO;
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goto getout3;
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}
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/* All cards except Rev 0 and 1 MC16's have 256kb of RAM */
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if ((card->cardtype == 0x08) && (card->cardrev <= 0x01))
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card->ramsize = 128;
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else
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card->ramsize = 256;
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printk("%s: %s Rev %d at 0x%04lx IRQ %d\n",
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dev->name,
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(card->cardtype == 0x08)?MADGEMC16_CARDNAME:
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MADGEMC32_CARDNAME, card->cardrev,
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dev->base_addr, dev->irq);
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if (card->cardtype == 0x0d)
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printk("%s: Warning: MC32 support is experimental and highly untested\n", dev->name);
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if (card->ringspeed==2) { /* Unknown */
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printk("%s: Warning: Ring speed not set in POS -- Please run the reference disk and set it!\n", dev->name);
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card->ringspeed = 1; /* default to 16mb */
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}
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printk("%s: RAM Size: %dKB\n", dev->name, card->ramsize);
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printk("%s: Ring Speed: %dMb/sec on %s\n", dev->name,
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(card->ringspeed)?16:4,
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card->cabletype?"STP/DB9":"UTP/RJ-45");
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printk("%s: Arbitration Level: %d\n", dev->name,
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card->arblevel);
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printk("%s: Burst Mode: ", dev->name);
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switch(card->burstmode) {
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case 0: printk("Cycle steal"); break;
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case 1: printk("Limited burst"); break;
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case 2: printk("Delayed release"); break;
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case 3: printk("Immediate release"); break;
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}
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printk(" (%s)\n", (card->fairness)?"Unfair":"Fair");
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/*
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* Enable SIF before we assign the interrupt handler,
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* just in case we get spurious interrupts that need
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* handling.
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*/
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outb(0, dev->base_addr + MC_CONTROL_REG0); /* sanity */
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madgemc_setsifsel(dev, 1);
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if (request_irq(dev->irq, madgemc_interrupt, IRQF_SHARED,
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"madgemc", dev)) {
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ret = -EBUSY;
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goto getout3;
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}
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madgemc_chipset_init(dev); /* enables interrupts! */
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madgemc_setcabletype(dev, card->cabletype);
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/* Setup MCA structures */
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mca_device_set_name(mdev, (card->cardtype == 0x08)?MADGEMC16_CARDNAME:MADGEMC32_CARDNAME);
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mca_set_adapter_procfn(mdev->slot, madgemc_mcaproc, dev);
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printk("%s: Ring Station Address: %pM\n",
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dev->name, dev->dev_addr);
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if (tmsdev_init(dev, device)) {
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printk("%s: unable to get memory for dev->priv.\n",
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dev->name);
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ret = -ENOMEM;
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goto getout4;
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}
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tp = netdev_priv(dev);
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/*
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* The MC16 is physically a 32bit card. However, Madge
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* insists on calling it 16bit, so I'll assume here that
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* they know what they're talking about. Cut off DMA
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* at 16mb.
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*/
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tp->setnselout = madgemc_setnselout_pins;
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tp->sifwriteb = madgemc_sifwriteb;
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tp->sifreadb = madgemc_sifreadb;
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tp->sifwritew = madgemc_sifwritew;
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tp->sifreadw = madgemc_sifreadw;
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tp->DataRate = (card->ringspeed)?SPEED_16:SPEED_4;
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memcpy(tp->ProductID, "Madge MCA 16/4 ", PROD_ID_SIZE + 1);
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dev->open = madgemc_open;
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dev->stop = madgemc_close;
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tp->tmspriv = card;
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dev_set_drvdata(device, dev);
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if (register_netdev(dev) == 0)
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return 0;
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dev_set_drvdata(device, NULL);
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ret = -ENOMEM;
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getout4:
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free_irq(dev->irq, dev);
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getout3:
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release_region(dev->base_addr-MADGEMC_SIF_OFFSET,
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MADGEMC_IO_EXTENT);
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getout2:
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kfree(card);
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getout1:
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free_netdev(dev);
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getout:
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mca_device_set_claim(mdev, 0);
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return ret;
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}
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/*
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* Handle interrupts generated by the card
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*
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* The MicroChannel Madge cards need slightly more handling
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* after an interrupt than other TMS380 cards do.
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*
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* First we must make sure it was this card that generated the
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* interrupt (since interrupt sharing is allowed). Then,
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* because we're using level-triggered interrupts (as is
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* standard on MCA), we must toggle the interrupt line
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* on the card in order to claim and acknowledge the interrupt.
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* Once that is done, the interrupt should be handlable in
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* the normal tms380tr_interrupt() routine.
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*
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* There's two ways we can check to see if the interrupt is ours,
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* both with their own disadvantages...
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*
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* 1) Read in the SIFSTS register from the TMS controller. This
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* is guarenteed to be accurate, however, there's a fairly
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* large performance penalty for doing so: the Madge chips
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* must request the register from the Eagle, the Eagle must
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* read them from its internal bus, and then take the route
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* back out again, for a 16bit read.
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*
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* 2) Use the MC_CONTROL_REG0_SINTR bit from the Madge ASICs.
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* The major disadvantage here is that the accuracy of the
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* bit is in question. However, it cuts out the extra read
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* cycles it takes to read the Eagle's SIF, as its only an
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* 8bit read, and theoretically the Madge bit is directly
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* connected to the interrupt latch coming out of the Eagle
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* hardware (that statement is not verified).
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*
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* I can't determine which of these methods has the best win. For now,
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* we make a compromise. Use the Madge way for the first interrupt,
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* which should be the fast-path, and then once we hit the first
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* interrupt, keep on trying using the SIF method until we've
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* exhausted all contiguous interrupts.
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*
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*/
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static irqreturn_t madgemc_interrupt(int irq, void *dev_id)
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{
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int pending,reg1;
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struct net_device *dev;
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if (!dev_id) {
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printk("madgemc_interrupt: was not passed a dev_id!\n");
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return IRQ_NONE;
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}
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dev = (struct net_device *)dev_id;
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/* Make sure its really us. -- the Madge way */
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pending = inb(dev->base_addr + MC_CONTROL_REG0);
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if (!(pending & MC_CONTROL_REG0_SINTR))
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return IRQ_NONE; /* not our interrupt */
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/*
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* Since we're level-triggered, we may miss the rising edge
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* of the next interrupt while we're off handling this one,
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* so keep checking until the SIF verifies that it has nothing
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* left for us to do.
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*/
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pending = STS_SYSTEM_IRQ;
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do {
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if (pending & STS_SYSTEM_IRQ) {
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/* Toggle the interrupt to reset the latch on card */
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reg1 = inb(dev->base_addr + MC_CONTROL_REG1);
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outb(reg1 ^ MC_CONTROL_REG1_SINTEN,
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dev->base_addr + MC_CONTROL_REG1);
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outb(reg1, dev->base_addr + MC_CONTROL_REG1);
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/* Continue handling as normal */
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tms380tr_interrupt(irq, dev_id);
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pending = SIFREADW(SIFSTS); /* restart - the SIF way */
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} else
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return IRQ_HANDLED;
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} while (1);
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return IRQ_HANDLED; /* not reachable */
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}
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/*
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* Set the card to the prefered ring speed.
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*
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* Unlike newer cards, the MC16/32 have their speed selection
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* circuit connected to the Madge ASICs and not to the TMS380
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* NSELOUT pins. Set the ASIC bits correctly here, and return
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* zero to leave the TMS NSELOUT bits unaffected.
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*
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*/
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static unsigned short madgemc_setnselout_pins(struct net_device *dev)
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{
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unsigned char reg1;
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struct net_local *tp = netdev_priv(dev);
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reg1 = inb(dev->base_addr + MC_CONTROL_REG1);
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if(tp->DataRate == SPEED_16)
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reg1 |= MC_CONTROL_REG1_SPEED_SEL; /* add for 16mb */
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else if (reg1 & MC_CONTROL_REG1_SPEED_SEL)
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reg1 ^= MC_CONTROL_REG1_SPEED_SEL; /* remove for 4mb */
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outb(reg1, dev->base_addr + MC_CONTROL_REG1);
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return 0; /* no change */
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}
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/*
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* Set the register page. This equates to the SRSX line
|
|
* on the TMS380Cx6.
|
|
*
|
|
* Register selection is normally done via three contiguous
|
|
* bits. However, some boards (such as the MC16/32) use only
|
|
* two bits, plus a separate bit in the glue chip. This
|
|
* sets the SRSX bit (the top bit). See page 4-17 in the
|
|
* Yellow Book for which registers are affected.
|
|
*
|
|
*/
|
|
static void madgemc_setregpage(struct net_device *dev, int page)
|
|
{
|
|
static int reg1;
|
|
|
|
reg1 = inb(dev->base_addr + MC_CONTROL_REG1);
|
|
if ((page == 0) && (reg1 & MC_CONTROL_REG1_SRSX)) {
|
|
outb(reg1 ^ MC_CONTROL_REG1_SRSX,
|
|
dev->base_addr + MC_CONTROL_REG1);
|
|
}
|
|
else if (page == 1) {
|
|
outb(reg1 | MC_CONTROL_REG1_SRSX,
|
|
dev->base_addr + MC_CONTROL_REG1);
|
|
}
|
|
reg1 = inb(dev->base_addr + MC_CONTROL_REG1);
|
|
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* The SIF registers are not mapped into register space by default
|
|
* Set this to 1 to map them, 0 to map the BIA ROM.
|
|
*
|
|
*/
|
|
static void madgemc_setsifsel(struct net_device *dev, int val)
|
|
{
|
|
unsigned int reg0;
|
|
|
|
reg0 = inb(dev->base_addr + MC_CONTROL_REG0);
|
|
if ((val == 0) && (reg0 & MC_CONTROL_REG0_SIFSEL)) {
|
|
outb(reg0 ^ MC_CONTROL_REG0_SIFSEL,
|
|
dev->base_addr + MC_CONTROL_REG0);
|
|
} else if (val == 1) {
|
|
outb(reg0 | MC_CONTROL_REG0_SIFSEL,
|
|
dev->base_addr + MC_CONTROL_REG0);
|
|
}
|
|
reg0 = inb(dev->base_addr + MC_CONTROL_REG0);
|
|
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Enable SIF interrupts
|
|
*
|
|
* This does not enable interrupts in the SIF, but rather
|
|
* enables SIF interrupts to be passed onto the host.
|
|
*
|
|
*/
|
|
static void madgemc_setint(struct net_device *dev, int val)
|
|
{
|
|
unsigned int reg1;
|
|
|
|
reg1 = inb(dev->base_addr + MC_CONTROL_REG1);
|
|
if ((val == 0) && (reg1 & MC_CONTROL_REG1_SINTEN)) {
|
|
outb(reg1 ^ MC_CONTROL_REG1_SINTEN,
|
|
dev->base_addr + MC_CONTROL_REG1);
|
|
} else if (val == 1) {
|
|
outb(reg1 | MC_CONTROL_REG1_SINTEN,
|
|
dev->base_addr + MC_CONTROL_REG1);
|
|
}
|
|
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Cable type is set via control register 7. Bit zero high
|
|
* for UTP, low for STP.
|
|
*/
|
|
static void madgemc_setcabletype(struct net_device *dev, int type)
|
|
{
|
|
outb((type==0)?MC_CONTROL_REG7_CABLEUTP:MC_CONTROL_REG7_CABLESTP,
|
|
dev->base_addr + MC_CONTROL_REG7);
|
|
}
|
|
|
|
/*
|
|
* Enable the functions of the Madge chipset needed for
|
|
* full working order.
|
|
*/
|
|
static int madgemc_chipset_init(struct net_device *dev)
|
|
{
|
|
outb(0, dev->base_addr + MC_CONTROL_REG1); /* pull SRESET low */
|
|
tms380tr_wait(100); /* wait for card to reset */
|
|
|
|
/* bring back into normal operating mode */
|
|
outb(MC_CONTROL_REG1_NSRESET, dev->base_addr + MC_CONTROL_REG1);
|
|
|
|
/* map SIF registers */
|
|
madgemc_setsifsel(dev, 1);
|
|
|
|
/* enable SIF interrupts */
|
|
madgemc_setint(dev, 1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Disable the board, and put back into power-up state.
|
|
*/
|
|
static void madgemc_chipset_close(struct net_device *dev)
|
|
{
|
|
/* disable interrupts */
|
|
madgemc_setint(dev, 0);
|
|
/* unmap SIF registers */
|
|
madgemc_setsifsel(dev, 0);
|
|
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Read the card type (MC16 or MC32) from the card.
|
|
*
|
|
* The configuration registers are stored in two separate
|
|
* pages. Pages are flipped by clearing bit 3 of CONTROL_REG0 (PAGE)
|
|
* for page zero, or setting bit 3 for page one.
|
|
*
|
|
* Page zero contains the following data:
|
|
* Byte 0: Manufacturer ID (0x4D -- ASCII "M")
|
|
* Byte 1: Card type:
|
|
* 0x08 for MC16
|
|
* 0x0D for MC32
|
|
* Byte 2: Card revision
|
|
* Byte 3: Mirror of POS config register 0
|
|
* Byte 4: Mirror of POS 1
|
|
* Byte 5: Mirror of POS 2
|
|
*
|
|
* Page one contains the following data:
|
|
* Byte 0: Unused
|
|
* Byte 1-6: BIA, MSB to LSB.
|
|
*
|
|
* Note that to read the BIA, we must unmap the SIF registers
|
|
* by clearing bit 2 of CONTROL_REG0 (SIFSEL), as the data
|
|
* will reside in the same logical location. For this reason,
|
|
* _never_ read the BIA while the Eagle processor is running!
|
|
* The SIF will be completely inaccessible until the BIA operation
|
|
* is complete.
|
|
*
|
|
*/
|
|
static void madgemc_read_rom(struct net_device *dev, struct card_info *card)
|
|
{
|
|
unsigned long ioaddr;
|
|
unsigned char reg0, reg1, tmpreg0, i;
|
|
|
|
ioaddr = dev->base_addr;
|
|
|
|
reg0 = inb(ioaddr + MC_CONTROL_REG0);
|
|
reg1 = inb(ioaddr + MC_CONTROL_REG1);
|
|
|
|
/* Switch to page zero and unmap SIF */
|
|
tmpreg0 = reg0 & ~(MC_CONTROL_REG0_PAGE + MC_CONTROL_REG0_SIFSEL);
|
|
outb(tmpreg0, ioaddr + MC_CONTROL_REG0);
|
|
|
|
card->manid = inb(ioaddr + MC_ROM_MANUFACTURERID);
|
|
card->cardtype = inb(ioaddr + MC_ROM_ADAPTERID);
|
|
card->cardrev = inb(ioaddr + MC_ROM_REVISION);
|
|
|
|
/* Switch to rom page one */
|
|
outb(tmpreg0 | MC_CONTROL_REG0_PAGE, ioaddr + MC_CONTROL_REG0);
|
|
|
|
/* Read BIA */
|
|
dev->addr_len = 6;
|
|
for (i = 0; i < 6; i++)
|
|
dev->dev_addr[i] = inb(ioaddr + MC_ROM_BIA_START + i);
|
|
|
|
/* Restore original register values */
|
|
outb(reg0, ioaddr + MC_CONTROL_REG0);
|
|
outb(reg1, ioaddr + MC_CONTROL_REG1);
|
|
|
|
return;
|
|
}
|
|
|
|
static int madgemc_open(struct net_device *dev)
|
|
{
|
|
/*
|
|
* Go ahead and reinitialize the chipset again, just to
|
|
* make sure we didn't get left in a bad state.
|
|
*/
|
|
madgemc_chipset_init(dev);
|
|
tms380tr_open(dev);
|
|
return 0;
|
|
}
|
|
|
|
static int madgemc_close(struct net_device *dev)
|
|
{
|
|
tms380tr_close(dev);
|
|
madgemc_chipset_close(dev);
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Give some details available from /proc/mca/slotX
|
|
*/
|
|
static int madgemc_mcaproc(char *buf, int slot, void *d)
|
|
{
|
|
struct net_device *dev = (struct net_device *)d;
|
|
struct net_local *tp = netdev_priv(dev);
|
|
struct card_info *curcard = tp->tmspriv;
|
|
int len = 0;
|
|
|
|
len += sprintf(buf+len, "-------\n");
|
|
if (curcard) {
|
|
len += sprintf(buf+len, "Card Revision: %d\n", curcard->cardrev);
|
|
len += sprintf(buf+len, "RAM Size: %dkb\n", curcard->ramsize);
|
|
len += sprintf(buf+len, "Cable type: %s\n", (curcard->cabletype)?"STP/DB9":"UTP/RJ-45");
|
|
len += sprintf(buf+len, "Configured ring speed: %dMb/sec\n", (curcard->ringspeed)?16:4);
|
|
len += sprintf(buf+len, "Running ring speed: %dMb/sec\n", (tp->DataRate==SPEED_16)?16:4);
|
|
len += sprintf(buf+len, "Device: %s\n", dev->name);
|
|
len += sprintf(buf+len, "IO Port: 0x%04lx\n", dev->base_addr);
|
|
len += sprintf(buf+len, "IRQ: %d\n", dev->irq);
|
|
len += sprintf(buf+len, "Arbitration Level: %d\n", curcard->arblevel);
|
|
len += sprintf(buf+len, "Burst Mode: ");
|
|
switch(curcard->burstmode) {
|
|
case 0: len += sprintf(buf+len, "Cycle steal"); break;
|
|
case 1: len += sprintf(buf+len, "Limited burst"); break;
|
|
case 2: len += sprintf(buf+len, "Delayed release"); break;
|
|
case 3: len += sprintf(buf+len, "Immediate release"); break;
|
|
}
|
|
len += sprintf(buf+len, " (%s)\n", (curcard->fairness)?"Unfair":"Fair");
|
|
|
|
len += sprintf(buf+len, "Ring Station Address: %pM\n",
|
|
dev->dev_addr);
|
|
} else
|
|
len += sprintf(buf+len, "Card not configured\n");
|
|
|
|
return len;
|
|
}
|
|
|
|
static int __devexit madgemc_remove(struct device *device)
|
|
{
|
|
struct net_device *dev = dev_get_drvdata(device);
|
|
struct net_local *tp;
|
|
struct card_info *card;
|
|
|
|
BUG_ON(!dev);
|
|
|
|
tp = netdev_priv(dev);
|
|
card = tp->tmspriv;
|
|
kfree(card);
|
|
tp->tmspriv = NULL;
|
|
|
|
unregister_netdev(dev);
|
|
release_region(dev->base_addr-MADGEMC_SIF_OFFSET, MADGEMC_IO_EXTENT);
|
|
free_irq(dev->irq, dev);
|
|
tmsdev_term(dev);
|
|
free_netdev(dev);
|
|
dev_set_drvdata(device, NULL);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static short madgemc_adapter_ids[] __initdata = {
|
|
0x002d,
|
|
0x0000
|
|
};
|
|
|
|
static struct mca_driver madgemc_driver = {
|
|
.id_table = madgemc_adapter_ids,
|
|
.driver = {
|
|
.name = "madgemc",
|
|
.bus = &mca_bus_type,
|
|
.probe = madgemc_probe,
|
|
.remove = __devexit_p(madgemc_remove),
|
|
},
|
|
};
|
|
|
|
static int __init madgemc_init (void)
|
|
{
|
|
return mca_register_driver (&madgemc_driver);
|
|
}
|
|
|
|
static void __exit madgemc_exit (void)
|
|
{
|
|
mca_unregister_driver (&madgemc_driver);
|
|
}
|
|
|
|
module_init(madgemc_init);
|
|
module_exit(madgemc_exit);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
|