![Jeremy Fitzhardinge](/assets/img/avatar_default.png)
For some reason tlb_uv was including linux/mc146818rtc.h. It really just needs linux/seq_file.h Signed-off-by: Jeremy Fitzhardinge <jeremy.fitzhardinge@citix.com> Cc: Cliff Wickman <cpw@sgi.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
794 lines
21 KiB
C
794 lines
21 KiB
C
/*
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* SGI UltraViolet TLB flush routines.
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*
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* (c) 2008 Cliff Wickman <cpw@sgi.com>, SGI.
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*
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* This code is released under the GNU General Public License version 2 or
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* later.
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*/
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#include <linux/seq_file.h>
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#include <linux/proc_fs.h>
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#include <linux/kernel.h>
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#include <asm/mmu_context.h>
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#include <asm/uv/uv_mmrs.h>
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#include <asm/uv/uv_hub.h>
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#include <asm/uv/uv_bau.h>
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#include <asm/genapic.h>
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#include <asm/idle.h>
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#include <asm/tsc.h>
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#include <asm/irq_vectors.h>
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#include <mach_apic.h>
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static struct bau_control **uv_bau_table_bases __read_mostly;
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static int uv_bau_retry_limit __read_mostly;
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/* position of pnode (which is nasid>>1): */
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static int uv_nshift __read_mostly;
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static unsigned long uv_mmask __read_mostly;
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static DEFINE_PER_CPU(struct ptc_stats, ptcstats);
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static DEFINE_PER_CPU(struct bau_control, bau_control);
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/*
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* Free a software acknowledge hardware resource by clearing its Pending
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* bit. This will return a reply to the sender.
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* If the message has timed out, a reply has already been sent by the
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* hardware but the resource has not been released. In that case our
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* clear of the Timeout bit (as well) will free the resource. No reply will
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* be sent (the hardware will only do one reply per message).
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*/
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static void uv_reply_to_message(int resource,
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struct bau_payload_queue_entry *msg,
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struct bau_msg_status *msp)
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{
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unsigned long dw;
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dw = (1 << (resource + UV_SW_ACK_NPENDING)) | (1 << resource);
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msg->replied_to = 1;
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msg->sw_ack_vector = 0;
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if (msp)
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msp->seen_by.bits = 0;
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uv_write_local_mmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, dw);
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}
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/*
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* Do all the things a cpu should do for a TLB shootdown message.
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* Other cpu's may come here at the same time for this message.
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*/
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static void uv_bau_process_message(struct bau_payload_queue_entry *msg,
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int msg_slot, int sw_ack_slot)
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{
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unsigned long this_cpu_mask;
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struct bau_msg_status *msp;
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int cpu;
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msp = __get_cpu_var(bau_control).msg_statuses + msg_slot;
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cpu = uv_blade_processor_id();
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msg->number_of_cpus =
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uv_blade_nr_online_cpus(uv_node_to_blade_id(numa_node_id()));
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this_cpu_mask = 1UL << cpu;
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if (msp->seen_by.bits & this_cpu_mask)
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return;
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atomic_or_long(&msp->seen_by.bits, this_cpu_mask);
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if (msg->replied_to == 1)
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return;
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if (msg->address == TLB_FLUSH_ALL) {
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local_flush_tlb();
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__get_cpu_var(ptcstats).alltlb++;
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} else {
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__flush_tlb_one(msg->address);
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__get_cpu_var(ptcstats).onetlb++;
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}
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__get_cpu_var(ptcstats).requestee++;
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atomic_inc_short(&msg->acknowledge_count);
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if (msg->number_of_cpus == msg->acknowledge_count)
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uv_reply_to_message(sw_ack_slot, msg, msp);
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}
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/*
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* Examine the payload queue on one distribution node to see
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* which messages have not been seen, and which cpu(s) have not seen them.
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*
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* Returns the number of cpu's that have not responded.
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*/
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static int uv_examine_destination(struct bau_control *bau_tablesp, int sender)
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{
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struct bau_payload_queue_entry *msg;
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struct bau_msg_status *msp;
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int count = 0;
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int i;
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int j;
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for (msg = bau_tablesp->va_queue_first, i = 0; i < DEST_Q_SIZE;
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msg++, i++) {
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if ((msg->sending_cpu == sender) && (!msg->replied_to)) {
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msp = bau_tablesp->msg_statuses + i;
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printk(KERN_DEBUG
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"blade %d: address:%#lx %d of %d, not cpu(s): ",
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i, msg->address, msg->acknowledge_count,
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msg->number_of_cpus);
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for (j = 0; j < msg->number_of_cpus; j++) {
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if (!((1L << j) & msp->seen_by.bits)) {
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count++;
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printk("%d ", j);
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}
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}
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printk("\n");
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}
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}
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return count;
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}
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/*
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* Examine the payload queue on all the distribution nodes to see
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* which messages have not been seen, and which cpu(s) have not seen them.
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*
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* Returns the number of cpu's that have not responded.
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*/
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static int uv_examine_destinations(struct bau_target_nodemask *distribution)
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{
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int sender;
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int i;
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int count = 0;
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sender = smp_processor_id();
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for (i = 0; i < sizeof(struct bau_target_nodemask) * BITSPERBYTE; i++) {
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if (!bau_node_isset(i, distribution))
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continue;
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count += uv_examine_destination(uv_bau_table_bases[i], sender);
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}
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return count;
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}
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/*
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* wait for completion of a broadcast message
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*
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* return COMPLETE, RETRY or GIVEUP
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*/
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static int uv_wait_completion(struct bau_desc *bau_desc,
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unsigned long mmr_offset, int right_shift)
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{
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int exams = 0;
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long destination_timeouts = 0;
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long source_timeouts = 0;
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unsigned long descriptor_status;
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while ((descriptor_status = (((unsigned long)
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uv_read_local_mmr(mmr_offset) >>
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right_shift) & UV_ACT_STATUS_MASK)) !=
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DESC_STATUS_IDLE) {
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if (descriptor_status == DESC_STATUS_SOURCE_TIMEOUT) {
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source_timeouts++;
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if (source_timeouts > SOURCE_TIMEOUT_LIMIT)
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source_timeouts = 0;
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__get_cpu_var(ptcstats).s_retry++;
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return FLUSH_RETRY;
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}
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/*
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* spin here looking for progress at the destinations
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*/
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if (descriptor_status == DESC_STATUS_DESTINATION_TIMEOUT) {
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destination_timeouts++;
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if (destination_timeouts > DESTINATION_TIMEOUT_LIMIT) {
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/*
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* returns number of cpus not responding
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*/
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if (uv_examine_destinations
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(&bau_desc->distribution) == 0) {
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__get_cpu_var(ptcstats).d_retry++;
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return FLUSH_RETRY;
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}
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exams++;
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if (exams >= uv_bau_retry_limit) {
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printk(KERN_DEBUG
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"uv_flush_tlb_others");
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printk("giving up on cpu %d\n",
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smp_processor_id());
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return FLUSH_GIVEUP;
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}
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/*
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* delays can hang the simulator
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udelay(1000);
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*/
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destination_timeouts = 0;
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}
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}
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}
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return FLUSH_COMPLETE;
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}
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/**
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* uv_flush_send_and_wait
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*
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* Send a broadcast and wait for a broadcast message to complete.
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*
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* The cpumaskp mask contains the cpus the broadcast was sent to.
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*
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* Returns 1 if all remote flushing was done. The mask is zeroed.
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* Returns 0 if some remote flushing remains to be done. The mask is left
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* unchanged.
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*/
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int uv_flush_send_and_wait(int cpu, int this_blade, struct bau_desc *bau_desc,
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cpumask_t *cpumaskp)
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{
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int completion_status = 0;
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int right_shift;
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int tries = 0;
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int blade;
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int bit;
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unsigned long mmr_offset;
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unsigned long index;
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cycles_t time1;
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cycles_t time2;
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if (cpu < UV_CPUS_PER_ACT_STATUS) {
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mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_0;
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right_shift = cpu * UV_ACT_STATUS_SIZE;
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} else {
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mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_1;
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right_shift =
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((cpu - UV_CPUS_PER_ACT_STATUS) * UV_ACT_STATUS_SIZE);
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}
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time1 = get_cycles();
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do {
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tries++;
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index = (1UL << UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT) |
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cpu;
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uv_write_local_mmr(UVH_LB_BAU_SB_ACTIVATION_CONTROL, index);
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completion_status = uv_wait_completion(bau_desc, mmr_offset,
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right_shift);
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} while (completion_status == FLUSH_RETRY);
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time2 = get_cycles();
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__get_cpu_var(ptcstats).sflush += (time2 - time1);
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if (tries > 1)
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__get_cpu_var(ptcstats).retriesok++;
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if (completion_status == FLUSH_GIVEUP) {
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/*
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* Cause the caller to do an IPI-style TLB shootdown on
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* the cpu's, all of which are still in the mask.
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*/
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__get_cpu_var(ptcstats).ptc_i++;
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return 0;
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}
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/*
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* Success, so clear the remote cpu's from the mask so we don't
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* use the IPI method of shootdown on them.
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*/
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for_each_cpu_mask(bit, *cpumaskp) {
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blade = uv_cpu_to_blade_id(bit);
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if (blade == this_blade)
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continue;
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cpu_clear(bit, *cpumaskp);
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}
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if (!cpus_empty(*cpumaskp))
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return 0;
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return 1;
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}
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/**
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* uv_flush_tlb_others - globally purge translation cache of a virtual
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* address or all TLB's
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* @cpumaskp: mask of all cpu's in which the address is to be removed
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* @mm: mm_struct containing virtual address range
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* @va: virtual address to be removed (or TLB_FLUSH_ALL for all TLB's on cpu)
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*
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* This is the entry point for initiating any UV global TLB shootdown.
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*
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* Purges the translation caches of all specified processors of the given
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* virtual address, or purges all TLB's on specified processors.
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*
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* The caller has derived the cpumaskp from the mm_struct and has subtracted
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* the local cpu from the mask. This function is called only if there
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* are bits set in the mask. (e.g. flush_tlb_page())
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*
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* The cpumaskp is converted into a nodemask of the nodes containing
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* the cpus.
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*
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* Returns 1 if all remote flushing was done.
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* Returns 0 if some remote flushing remains to be done.
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*/
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int uv_flush_tlb_others(cpumask_t *cpumaskp, struct mm_struct *mm,
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unsigned long va)
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{
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int i;
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int bit;
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int blade;
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int cpu;
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int this_blade;
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int locals = 0;
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struct bau_desc *bau_desc;
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cpu = uv_blade_processor_id();
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this_blade = uv_numa_blade_id();
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bau_desc = __get_cpu_var(bau_control).descriptor_base;
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bau_desc += UV_ITEMS_PER_DESCRIPTOR * cpu;
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bau_nodes_clear(&bau_desc->distribution, UV_DISTRIBUTION_SIZE);
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i = 0;
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for_each_cpu_mask(bit, *cpumaskp) {
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blade = uv_cpu_to_blade_id(bit);
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BUG_ON(blade > (UV_DISTRIBUTION_SIZE - 1));
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if (blade == this_blade) {
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locals++;
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continue;
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}
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bau_node_set(blade, &bau_desc->distribution);
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i++;
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}
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if (i == 0) {
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/*
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* no off_node flushing; return status for local node
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*/
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if (locals)
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return 0;
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else
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return 1;
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}
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__get_cpu_var(ptcstats).requestor++;
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__get_cpu_var(ptcstats).ntargeted += i;
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bau_desc->payload.address = va;
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bau_desc->payload.sending_cpu = smp_processor_id();
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return uv_flush_send_and_wait(cpu, this_blade, bau_desc, cpumaskp);
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}
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/*
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* The BAU message interrupt comes here. (registered by set_intr_gate)
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* See entry_64.S
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*
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* We received a broadcast assist message.
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*
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* Interrupts may have been disabled; this interrupt could represent
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* the receipt of several messages.
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*
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* All cores/threads on this node get this interrupt.
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* The last one to see it does the s/w ack.
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* (the resource will not be freed until noninterruptable cpus see this
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* interrupt; hardware will timeout the s/w ack and reply ERROR)
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*/
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void uv_bau_message_interrupt(struct pt_regs *regs)
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{
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struct bau_payload_queue_entry *va_queue_first;
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struct bau_payload_queue_entry *va_queue_last;
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struct bau_payload_queue_entry *msg;
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struct pt_regs *old_regs = set_irq_regs(regs);
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cycles_t time1;
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cycles_t time2;
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int msg_slot;
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int sw_ack_slot;
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int fw;
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int count = 0;
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unsigned long local_pnode;
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ack_APIC_irq();
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exit_idle();
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irq_enter();
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time1 = get_cycles();
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local_pnode = uv_blade_to_pnode(uv_numa_blade_id());
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va_queue_first = __get_cpu_var(bau_control).va_queue_first;
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va_queue_last = __get_cpu_var(bau_control).va_queue_last;
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msg = __get_cpu_var(bau_control).bau_msg_head;
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while (msg->sw_ack_vector) {
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count++;
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fw = msg->sw_ack_vector;
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msg_slot = msg - va_queue_first;
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sw_ack_slot = ffs(fw) - 1;
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uv_bau_process_message(msg, msg_slot, sw_ack_slot);
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msg++;
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if (msg > va_queue_last)
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msg = va_queue_first;
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__get_cpu_var(bau_control).bau_msg_head = msg;
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}
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if (!count)
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__get_cpu_var(ptcstats).nomsg++;
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else if (count > 1)
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__get_cpu_var(ptcstats).multmsg++;
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time2 = get_cycles();
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__get_cpu_var(ptcstats).dflush += (time2 - time1);
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irq_exit();
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set_irq_regs(old_regs);
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}
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static void uv_enable_timeouts(void)
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{
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int i;
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int blade;
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int last_blade;
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int pnode;
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int cur_cpu = 0;
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unsigned long apicid;
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last_blade = -1;
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for_each_online_node(i) {
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blade = uv_node_to_blade_id(i);
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if (blade == last_blade)
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continue;
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last_blade = blade;
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apicid = per_cpu(x86_cpu_to_apicid, cur_cpu);
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pnode = uv_blade_to_pnode(blade);
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cur_cpu += uv_blade_nr_possible_cpus(i);
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}
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}
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static void *uv_ptc_seq_start(struct seq_file *file, loff_t *offset)
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{
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if (*offset < num_possible_cpus())
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return offset;
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return NULL;
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}
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static void *uv_ptc_seq_next(struct seq_file *file, void *data, loff_t *offset)
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{
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(*offset)++;
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if (*offset < num_possible_cpus())
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return offset;
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return NULL;
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}
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static void uv_ptc_seq_stop(struct seq_file *file, void *data)
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{
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}
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/*
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* Display the statistics thru /proc
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* data points to the cpu number
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*/
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static int uv_ptc_seq_show(struct seq_file *file, void *data)
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{
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struct ptc_stats *stat;
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int cpu;
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cpu = *(loff_t *)data;
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if (!cpu) {
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seq_printf(file,
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"# cpu requestor requestee one all sretry dretry ptc_i ");
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seq_printf(file,
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"sw_ack sflush dflush sok dnomsg dmult starget\n");
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}
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if (cpu < num_possible_cpus() && cpu_online(cpu)) {
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stat = &per_cpu(ptcstats, cpu);
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seq_printf(file, "cpu %d %ld %ld %ld %ld %ld %ld %ld ",
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cpu, stat->requestor,
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stat->requestee, stat->onetlb, stat->alltlb,
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stat->s_retry, stat->d_retry, stat->ptc_i);
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seq_printf(file, "%lx %ld %ld %ld %ld %ld %ld\n",
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uv_read_global_mmr64(uv_blade_to_pnode
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(uv_cpu_to_blade_id(cpu)),
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UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE),
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stat->sflush, stat->dflush,
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stat->retriesok, stat->nomsg,
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stat->multmsg, stat->ntargeted);
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}
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return 0;
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}
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/*
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* 0: display meaning of the statistics
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* >0: retry limit
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*/
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static ssize_t uv_ptc_proc_write(struct file *file, const char __user *user,
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size_t count, loff_t *data)
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{
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long newmode;
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char optstr[64];
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if (count == 0 || count > sizeof(optstr))
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return -EINVAL;
|
|
if (copy_from_user(optstr, user, count))
|
|
return -EFAULT;
|
|
optstr[count - 1] = '\0';
|
|
if (strict_strtoul(optstr, 10, &newmode) < 0) {
|
|
printk(KERN_DEBUG "%s is invalid\n", optstr);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (newmode == 0) {
|
|
printk(KERN_DEBUG "# cpu: cpu number\n");
|
|
printk(KERN_DEBUG
|
|
"requestor: times this cpu was the flush requestor\n");
|
|
printk(KERN_DEBUG
|
|
"requestee: times this cpu was requested to flush its TLBs\n");
|
|
printk(KERN_DEBUG
|
|
"one: times requested to flush a single address\n");
|
|
printk(KERN_DEBUG
|
|
"all: times requested to flush all TLB's\n");
|
|
printk(KERN_DEBUG
|
|
"sretry: number of retries of source-side timeouts\n");
|
|
printk(KERN_DEBUG
|
|
"dretry: number of retries of destination-side timeouts\n");
|
|
printk(KERN_DEBUG
|
|
"ptc_i: times UV fell through to IPI-style flushes\n");
|
|
printk(KERN_DEBUG
|
|
"sw_ack: image of UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE\n");
|
|
printk(KERN_DEBUG
|
|
"sflush_us: cycles spent in uv_flush_tlb_others()\n");
|
|
printk(KERN_DEBUG
|
|
"dflush_us: cycles spent in handling flush requests\n");
|
|
printk(KERN_DEBUG "sok: successes on retry\n");
|
|
printk(KERN_DEBUG "dnomsg: interrupts with no message\n");
|
|
printk(KERN_DEBUG
|
|
"dmult: interrupts with multiple messages\n");
|
|
printk(KERN_DEBUG "starget: nodes targeted\n");
|
|
} else {
|
|
uv_bau_retry_limit = newmode;
|
|
printk(KERN_DEBUG "timeout retry limit:%d\n",
|
|
uv_bau_retry_limit);
|
|
}
|
|
|
|
return count;
|
|
}
|
|
|
|
static const struct seq_operations uv_ptc_seq_ops = {
|
|
.start = uv_ptc_seq_start,
|
|
.next = uv_ptc_seq_next,
|
|
.stop = uv_ptc_seq_stop,
|
|
.show = uv_ptc_seq_show
|
|
};
|
|
|
|
static int uv_ptc_proc_open(struct inode *inode, struct file *file)
|
|
{
|
|
return seq_open(file, &uv_ptc_seq_ops);
|
|
}
|
|
|
|
static const struct file_operations proc_uv_ptc_operations = {
|
|
.open = uv_ptc_proc_open,
|
|
.read = seq_read,
|
|
.write = uv_ptc_proc_write,
|
|
.llseek = seq_lseek,
|
|
.release = seq_release,
|
|
};
|
|
|
|
static int __init uv_ptc_init(void)
|
|
{
|
|
struct proc_dir_entry *proc_uv_ptc;
|
|
|
|
if (!is_uv_system())
|
|
return 0;
|
|
|
|
if (!proc_mkdir("sgi_uv", NULL))
|
|
return -EINVAL;
|
|
|
|
proc_uv_ptc = create_proc_entry(UV_PTC_BASENAME, 0444, NULL);
|
|
if (!proc_uv_ptc) {
|
|
printk(KERN_ERR "unable to create %s proc entry\n",
|
|
UV_PTC_BASENAME);
|
|
remove_proc_entry("sgi_uv", NULL);
|
|
return -EINVAL;
|
|
}
|
|
proc_uv_ptc->proc_fops = &proc_uv_ptc_operations;
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* begin the initialization of the per-blade control structures
|
|
*/
|
|
static struct bau_control * __init uv_table_bases_init(int blade, int node)
|
|
{
|
|
int i;
|
|
int *ip;
|
|
struct bau_msg_status *msp;
|
|
struct bau_control *bau_tabp;
|
|
|
|
bau_tabp =
|
|
kmalloc_node(sizeof(struct bau_control), GFP_KERNEL, node);
|
|
BUG_ON(!bau_tabp);
|
|
|
|
bau_tabp->msg_statuses =
|
|
kmalloc_node(sizeof(struct bau_msg_status) *
|
|
DEST_Q_SIZE, GFP_KERNEL, node);
|
|
BUG_ON(!bau_tabp->msg_statuses);
|
|
|
|
for (i = 0, msp = bau_tabp->msg_statuses; i < DEST_Q_SIZE; i++, msp++)
|
|
bau_cpubits_clear(&msp->seen_by, (int)
|
|
uv_blade_nr_possible_cpus(blade));
|
|
|
|
bau_tabp->watching =
|
|
kmalloc_node(sizeof(int) * DEST_NUM_RESOURCES, GFP_KERNEL, node);
|
|
BUG_ON(!bau_tabp->watching);
|
|
|
|
for (i = 0, ip = bau_tabp->watching; i < DEST_Q_SIZE; i++, ip++)
|
|
*ip = 0;
|
|
|
|
uv_bau_table_bases[blade] = bau_tabp;
|
|
|
|
return bau_tabp;
|
|
}
|
|
|
|
/*
|
|
* finish the initialization of the per-blade control structures
|
|
*/
|
|
static void __init
|
|
uv_table_bases_finish(int blade, int node, int cur_cpu,
|
|
struct bau_control *bau_tablesp,
|
|
struct bau_desc *adp)
|
|
{
|
|
struct bau_control *bcp;
|
|
int i;
|
|
|
|
for (i = cur_cpu; i < cur_cpu + uv_blade_nr_possible_cpus(blade); i++) {
|
|
bcp = (struct bau_control *)&per_cpu(bau_control, i);
|
|
|
|
bcp->bau_msg_head = bau_tablesp->va_queue_first;
|
|
bcp->va_queue_first = bau_tablesp->va_queue_first;
|
|
bcp->va_queue_last = bau_tablesp->va_queue_last;
|
|
bcp->watching = bau_tablesp->watching;
|
|
bcp->msg_statuses = bau_tablesp->msg_statuses;
|
|
bcp->descriptor_base = adp;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* initialize the sending side's sending buffers
|
|
*/
|
|
static struct bau_desc * __init
|
|
uv_activation_descriptor_init(int node, int pnode)
|
|
{
|
|
int i;
|
|
unsigned long pa;
|
|
unsigned long m;
|
|
unsigned long n;
|
|
unsigned long mmr_image;
|
|
struct bau_desc *adp;
|
|
struct bau_desc *ad2;
|
|
|
|
adp = (struct bau_desc *)
|
|
kmalloc_node(16384, GFP_KERNEL, node);
|
|
BUG_ON(!adp);
|
|
|
|
pa = __pa((unsigned long)adp);
|
|
n = pa >> uv_nshift;
|
|
m = pa & uv_mmask;
|
|
|
|
mmr_image = uv_read_global_mmr64(pnode, UVH_LB_BAU_SB_DESCRIPTOR_BASE);
|
|
if (mmr_image) {
|
|
uv_write_global_mmr64(pnode, (unsigned long)
|
|
UVH_LB_BAU_SB_DESCRIPTOR_BASE,
|
|
(n << UV_DESC_BASE_PNODE_SHIFT | m));
|
|
}
|
|
|
|
for (i = 0, ad2 = adp; i < UV_ACTIVATION_DESCRIPTOR_SIZE; i++, ad2++) {
|
|
memset(ad2, 0, sizeof(struct bau_desc));
|
|
ad2->header.sw_ack_flag = 1;
|
|
ad2->header.base_dest_nodeid =
|
|
uv_blade_to_pnode(uv_cpu_to_blade_id(0));
|
|
ad2->header.command = UV_NET_ENDPOINT_INTD;
|
|
ad2->header.int_both = 1;
|
|
/*
|
|
* all others need to be set to zero:
|
|
* fairness chaining multilevel count replied_to
|
|
*/
|
|
}
|
|
return adp;
|
|
}
|
|
|
|
/*
|
|
* initialize the destination side's receiving buffers
|
|
*/
|
|
static struct bau_payload_queue_entry * __init
|
|
uv_payload_queue_init(int node, int pnode, struct bau_control *bau_tablesp)
|
|
{
|
|
struct bau_payload_queue_entry *pqp;
|
|
char *cp;
|
|
|
|
pqp = (struct bau_payload_queue_entry *) kmalloc_node(
|
|
(DEST_Q_SIZE + 1) * sizeof(struct bau_payload_queue_entry),
|
|
GFP_KERNEL, node);
|
|
BUG_ON(!pqp);
|
|
|
|
cp = (char *)pqp + 31;
|
|
pqp = (struct bau_payload_queue_entry *)(((unsigned long)cp >> 5) << 5);
|
|
bau_tablesp->va_queue_first = pqp;
|
|
uv_write_global_mmr64(pnode,
|
|
UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST,
|
|
((unsigned long)pnode <<
|
|
UV_PAYLOADQ_PNODE_SHIFT) |
|
|
uv_physnodeaddr(pqp));
|
|
uv_write_global_mmr64(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL,
|
|
uv_physnodeaddr(pqp));
|
|
bau_tablesp->va_queue_last = pqp + (DEST_Q_SIZE - 1);
|
|
uv_write_global_mmr64(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST,
|
|
(unsigned long)
|
|
uv_physnodeaddr(bau_tablesp->va_queue_last));
|
|
memset(pqp, 0, sizeof(struct bau_payload_queue_entry) * DEST_Q_SIZE);
|
|
|
|
return pqp;
|
|
}
|
|
|
|
/*
|
|
* Initialization of each UV blade's structures
|
|
*/
|
|
static int __init uv_init_blade(int blade, int node, int cur_cpu)
|
|
{
|
|
int pnode;
|
|
unsigned long pa;
|
|
unsigned long apicid;
|
|
struct bau_desc *adp;
|
|
struct bau_payload_queue_entry *pqp;
|
|
struct bau_control *bau_tablesp;
|
|
|
|
bau_tablesp = uv_table_bases_init(blade, node);
|
|
pnode = uv_blade_to_pnode(blade);
|
|
adp = uv_activation_descriptor_init(node, pnode);
|
|
pqp = uv_payload_queue_init(node, pnode, bau_tablesp);
|
|
uv_table_bases_finish(blade, node, cur_cpu, bau_tablesp, adp);
|
|
/*
|
|
* the below initialization can't be in firmware because the
|
|
* messaging IRQ will be determined by the OS
|
|
*/
|
|
apicid = per_cpu(x86_cpu_to_apicid, cur_cpu);
|
|
pa = uv_read_global_mmr64(pnode, UVH_BAU_DATA_CONFIG);
|
|
if ((pa & 0xff) != UV_BAU_MESSAGE) {
|
|
uv_write_global_mmr64(pnode, UVH_BAU_DATA_CONFIG,
|
|
((apicid << 32) | UV_BAU_MESSAGE));
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Initialization of BAU-related structures
|
|
*/
|
|
static int __init uv_bau_init(void)
|
|
{
|
|
int blade;
|
|
int node;
|
|
int nblades;
|
|
int last_blade;
|
|
int cur_cpu = 0;
|
|
|
|
if (!is_uv_system())
|
|
return 0;
|
|
|
|
uv_bau_retry_limit = 1;
|
|
uv_nshift = uv_hub_info->n_val;
|
|
uv_mmask = (1UL << uv_hub_info->n_val) - 1;
|
|
nblades = 0;
|
|
last_blade = -1;
|
|
for_each_online_node(node) {
|
|
blade = uv_node_to_blade_id(node);
|
|
if (blade == last_blade)
|
|
continue;
|
|
last_blade = blade;
|
|
nblades++;
|
|
}
|
|
uv_bau_table_bases = (struct bau_control **)
|
|
kmalloc(nblades * sizeof(struct bau_control *), GFP_KERNEL);
|
|
BUG_ON(!uv_bau_table_bases);
|
|
|
|
last_blade = -1;
|
|
for_each_online_node(node) {
|
|
blade = uv_node_to_blade_id(node);
|
|
if (blade == last_blade)
|
|
continue;
|
|
last_blade = blade;
|
|
uv_init_blade(blade, node, cur_cpu);
|
|
cur_cpu += uv_blade_nr_possible_cpus(blade);
|
|
}
|
|
alloc_intr_gate(UV_BAU_MESSAGE, uv_bau_message_intr1);
|
|
uv_enable_timeouts();
|
|
|
|
return 0;
|
|
}
|
|
__initcall(uv_bau_init);
|
|
__initcall(uv_ptc_init);
|