3a082ec9b2
This patch adds support for EHCI compliant HSUSB Host controller found on Marvell Socs. It fits both OTG and SPH controller on marvell Socs, including PXA9xx/MMP2/MMP3/MGx. Signed-off-by: Neil Zhang <zhangwm@marvell.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
65 lines
1.6 KiB
C
65 lines
1.6 KiB
C
/*
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* Copyright (C) 2011 Marvell International Ltd. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef __MV_PLATFORM_USB_H
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#define __MV_PLATFORM_USB_H
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enum pxa_ehci_type {
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EHCI_UNDEFINED = 0,
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PXA_U2OEHCI, /* pxa 168, 9xx */
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PXA_SPH, /* pxa 168, 9xx SPH */
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MMP3_HSIC, /* mmp3 hsic */
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MMP3_FSIC, /* mmp3 fsic */
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};
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enum {
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MV_USB_MODE_OTG,
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MV_USB_MODE_HOST,
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};
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enum {
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VBUS_LOW = 0,
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VBUS_HIGH = 1 << 0,
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};
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struct mv_usb_addon_irq {
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unsigned int irq;
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int (*poll)(void);
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};
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struct mv_usb_platform_data {
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unsigned int clknum;
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char **clkname;
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struct mv_usb_addon_irq *id; /* Only valid for OTG. ID pin change*/
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struct mv_usb_addon_irq *vbus; /* valid for OTG/UDC. VBUS change*/
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/* only valid for HCD. OTG or Host only*/
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unsigned int mode;
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/* This flag is used for that needs id pin checked by otg */
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unsigned int disable_otg_clock_gating:1;
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/* Force a_bus_req to be asserted */
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unsigned int otg_force_a_bus_req:1;
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int (*phy_init)(void __iomem *regbase);
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void (*phy_deinit)(void __iomem *regbase);
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int (*set_vbus)(unsigned int vbus);
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int (*private_init)(void __iomem *opregs, void __iomem *phyregs);
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};
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#ifndef CONFIG_HAVE_CLK
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/* Dummy stub for clk framework */
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#define clk_get(dev, id) NULL
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#define clk_put(clock) do {} while (0)
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#define clk_enable(clock) do {} while (0)
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#define clk_disable(clock) do {} while (0)
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#endif
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#endif
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