c3585aa91a
Kirill Shutemov found problems with the non-upstream IMG driver where the use of extra DRM encoder/connector types caused random crashes when the DRM layer tried to display their matching name. This removes the MIPI types matching the changes Pauli Nieminen made to the non upstream driver set. As Pauli points out: " MIPI (or DSI) is protocol specification on top of LVDS serial bus. That makes it resonable to call MIPI connectors and encoders LVDS." (and indeed they may also be HDMI convertors or similar when we want to report a more useful to end user result) Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
269 lines
7.9 KiB
C
269 lines
7.9 KiB
C
/*
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* Copyright © 2011 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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/* Medfield DSI controller registers */
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#define MIPIA_DEVICE_READY_REG 0xb000
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#define MIPIA_INTR_STAT_REG 0xb004
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#define MIPIA_INTR_EN_REG 0xb008
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#define MIPIA_DSI_FUNC_PRG_REG 0xb00c
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#define MIPIA_HS_TX_TIMEOUT_REG 0xb010
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#define MIPIA_LP_RX_TIMEOUT_REG 0xb014
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#define MIPIA_TURN_AROUND_TIMEOUT_REG 0xb018
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#define MIPIA_DEVICE_RESET_TIMER_REG 0xb01c
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#define MIPIA_DPI_RESOLUTION_REG 0xb020
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#define MIPIA_DBI_FIFO_THROTTLE_REG 0xb024
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#define MIPIA_HSYNC_COUNT_REG 0xb028
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#define MIPIA_HBP_COUNT_REG 0xb02c
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#define MIPIA_HFP_COUNT_REG 0xb030
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#define MIPIA_HACTIVE_COUNT_REG 0xb034
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#define MIPIA_VSYNC_COUNT_REG 0xb038
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#define MIPIA_VBP_COUNT_REG 0xb03c
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#define MIPIA_VFP_COUNT_REG 0xb040
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#define MIPIA_HIGH_LOW_SWITCH_COUNT_REG 0xb044
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#define MIPIA_DPI_CONTROL_REG 0xb048
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#define MIPIA_DPI_DATA_REG 0xb04c
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#define MIPIA_INIT_COUNT_REG 0xb050
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#define MIPIA_MAX_RETURN_PACK_SIZE_REG 0xb054
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#define MIPIA_VIDEO_MODE_FORMAT_REG 0xb058
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#define MIPIA_EOT_DISABLE_REG 0xb05c
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#define MIPIA_LP_BYTECLK_REG 0xb060
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#define MIPIA_LP_GEN_DATA_REG 0xb064
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#define MIPIA_HS_GEN_DATA_REG 0xb068
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#define MIPIA_LP_GEN_CTRL_REG 0xb06c
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#define MIPIA_HS_GEN_CTRL_REG 0xb070
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#define MIPIA_GEN_FIFO_STAT_REG 0xb074
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#define MIPIA_HS_LS_DBI_ENABLE_REG 0xb078
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#define MIPIA_DPHY_PARAM_REG 0xb080
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#define MIPIA_DBI_BW_CTRL_REG 0xb084
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#define MIPIA_CLK_LANE_SWITCH_TIME_CNT_REG 0xb088
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#define DSI_DEVICE_READY (0x1)
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#define DSI_POWER_STATE_ULPS_ENTER (0x2 << 1)
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#define DSI_POWER_STATE_ULPS_EXIT (0x1 << 1)
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#define DSI_POWER_STATE_ULPS_OFFSET (0x1)
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#define DSI_ONE_DATA_LANE (0x1)
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#define DSI_TWO_DATA_LANE (0x2)
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#define DSI_THREE_DATA_LANE (0X3)
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#define DSI_FOUR_DATA_LANE (0x4)
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#define DSI_DPI_VIRT_CHANNEL_OFFSET (0x3)
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#define DSI_DBI_VIRT_CHANNEL_OFFSET (0x5)
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#define DSI_DPI_COLOR_FORMAT_RGB565 (0x01 << 7)
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#define DSI_DPI_COLOR_FORMAT_RGB666 (0x02 << 7)
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#define DSI_DPI_COLOR_FORMAT_RGB666_UNPACK (0x03 << 7)
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#define DSI_DPI_COLOR_FORMAT_RGB888 (0x04 << 7)
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#define DSI_DBI_COLOR_FORMAT_OPTION2 (0x05 << 13)
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#define DSI_INTR_STATE_RXSOTERROR 1
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#define DSI_INTR_STATE_SPL_PKG_SENT (1 << 30)
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#define DSI_INTR_STATE_TE (1 << 31)
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#define DSI_HS_TX_TIMEOUT_MASK (0xffffff)
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#define DSI_LP_RX_TIMEOUT_MASK (0xffffff)
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#define DSI_TURN_AROUND_TIMEOUT_MASK (0x3f)
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#define DSI_RESET_TIMER_MASK (0xffff)
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#define DSI_DBI_FIFO_WM_HALF (0x0)
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#define DSI_DBI_FIFO_WM_QUARTER (0x1)
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#define DSI_DBI_FIFO_WM_LOW (0x2)
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#define DSI_DPI_TIMING_MASK (0xffff)
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#define DSI_INIT_TIMER_MASK (0xffff)
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#define DSI_DBI_RETURN_PACK_SIZE_MASK (0x3ff)
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#define DSI_LP_BYTECLK_MASK (0x0ffff)
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#define DSI_HS_CTRL_GEN_SHORT_W0 (0x03)
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#define DSI_HS_CTRL_GEN_SHORT_W1 (0x13)
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#define DSI_HS_CTRL_GEN_SHORT_W2 (0x23)
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#define DSI_HS_CTRL_GEN_R0 (0x04)
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#define DSI_HS_CTRL_GEN_R1 (0x14)
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#define DSI_HS_CTRL_GEN_R2 (0x24)
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#define DSI_HS_CTRL_GEN_LONG_W (0x29)
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#define DSI_HS_CTRL_MCS_SHORT_W0 (0x05)
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#define DSI_HS_CTRL_MCS_SHORT_W1 (0x15)
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#define DSI_HS_CTRL_MCS_R0 (0x06)
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#define DSI_HS_CTRL_MCS_LONG_W (0x39)
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#define DSI_HS_CTRL_VC_OFFSET (0x06)
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#define DSI_HS_CTRL_WC_OFFSET (0x08)
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#define DSI_FIFO_GEN_HS_DATA_FULL (1 << 0)
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#define DSI_FIFO_GEN_HS_DATA_HALF_EMPTY (1 << 1)
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#define DSI_FIFO_GEN_HS_DATA_EMPTY (1 << 2)
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#define DSI_FIFO_GEN_LP_DATA_FULL (1 << 8)
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#define DSI_FIFO_GEN_LP_DATA_HALF_EMPTY (1 << 9)
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#define DSI_FIFO_GEN_LP_DATA_EMPTY (1 << 10)
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#define DSI_FIFO_GEN_HS_CTRL_FULL (1 << 16)
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#define DSI_FIFO_GEN_HS_CTRL_HALF_EMPTY (1 << 17)
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#define DSI_FIFO_GEN_HS_CTRL_EMPTY (1 << 18)
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#define DSI_FIFO_GEN_LP_CTRL_FULL (1 << 24)
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#define DSI_FIFO_GEN_LP_CTRL_HALF_EMPTY (1 << 25)
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#define DSI_FIFO_GEN_LP_CTRL_EMPTY (1 << 26)
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#define DSI_FIFO_DBI_EMPTY (1 << 27)
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#define DSI_FIFO_DPI_EMPTY (1 << 28)
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#define DSI_DBI_HS_LP_SWITCH_MASK (0x1)
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#define DSI_HS_LP_SWITCH_COUNTER_OFFSET (0x0)
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#define DSI_LP_HS_SWITCH_COUNTER_OFFSET (0x16)
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#define DSI_DPI_CTRL_HS_SHUTDOWN (0x00000001)
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#define DSI_DPI_CTRL_HS_TURN_ON (0x00000002)
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/* Medfield DSI adapter registers */
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#define MIPIA_CONTROL_REG 0xb104
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#define MIPIA_DATA_ADD_REG 0xb108
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#define MIPIA_DATA_LEN_REG 0xb10c
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#define MIPIA_CMD_ADD_REG 0xb110
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#define MIPIA_CMD_LEN_REG 0xb114
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/*dsi power modes*/
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#define DSI_POWER_MODE_DISPLAY_ON (1 << 2)
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#define DSI_POWER_MODE_NORMAL_ON (1 << 3)
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#define DSI_POWER_MODE_SLEEP_OUT (1 << 4)
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#define DSI_POWER_MODE_PARTIAL_ON (1 << 5)
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#define DSI_POWER_MODE_IDLE_ON (1 << 6)
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enum {
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MDFLD_DSI_ENCODER_DBI = 0,
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MDFLD_DSI_ENCODER_DPI,
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};
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enum {
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MDFLD_DSI_VIDEO_NON_BURST_MODE_SYNC_PULSE = 1,
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MDFLD_DSI_VIDEO_NON_BURST_MODE_SYNC_EVENTS = 2,
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MDFLD_DSI_VIDEO_BURST_MODE = 3,
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};
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#define DSI_DPI_COMPLETE_LAST_LINE (1 << 2)
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#define DSI_DPI_DISABLE_BTA (1 << 3)
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/* Panel types */
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enum {
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TPO_CMD,
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TPO_VID,
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TMD_CMD,
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TMD_VID,
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PYR_CMD,
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PYR_VID,
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TPO,
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TMD,
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PYR,
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HDMI,
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GCT_DETECT
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};
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/* Junk that belongs elsewhere */
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#define TPO_PANEL_WIDTH 84
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#define TPO_PANEL_HEIGHT 46
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#define TMD_PANEL_WIDTH 39
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#define TMD_PANEL_HEIGHT 71
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#define PYR_PANEL_WIDTH 53
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#define PYR_PANEL_HEIGHT 95
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/* Panel interface */
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struct panel_info {
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u32 width_mm;
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u32 height_mm;
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};
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struct mdfld_dsi_dbi_output;
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struct mdfld_dsi_connector_state {
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u32 mipi_ctrl_reg;
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};
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struct mdfld_dsi_encoder_state {
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};
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struct mdfld_dsi_connector {
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/*
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* This is ugly, but I have to use connector in it! :-(
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* FIXME: use drm_connector instead.
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*/
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struct psb_intel_output base;
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int pipe;
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void *private;
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void *pkg_sender;
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/* Connection status */
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enum drm_connector_status status;
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};
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struct mdfld_dsi_encoder {
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struct drm_encoder base;
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void *private;
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};
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/*
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* DSI config, consists of one DSI connector, two DSI encoders.
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* DRM will pick up on DSI encoder basing on differents configs.
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*/
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struct mdfld_dsi_config {
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struct drm_device *dev;
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struct drm_display_mode *fixed_mode;
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struct drm_display_mode *mode;
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struct mdfld_dsi_connector *connector;
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struct mdfld_dsi_encoder *encoders[DRM_CONNECTOR_MAX_ENCODER];
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struct mdfld_dsi_encoder *encoder;
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int changed;
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int bpp;
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int type;
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int lane_count;
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/*Virtual channel number for this encoder*/
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int channel_num;
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/*video mode configure*/
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int video_mode;
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int dvr_ic_inited;
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};
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#define MDFLD_DSI_CONNECTOR(psb_output) \
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(container_of(psb_output, struct mdfld_dsi_connector, base))
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#define MDFLD_DSI_ENCODER(encoder) \
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(container_of(encoder, struct mdfld_dsi_encoder, base))
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struct panel_funcs {
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const struct drm_encoder_funcs *encoder_funcs;
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const struct drm_encoder_helper_funcs *encoder_helper_funcs;
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struct drm_display_mode *(*get_config_mode) (struct drm_device *);
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void (*update_fb) (struct mdfld_dsi_dbi_output *, int);
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int (*get_panel_info) (struct drm_device *, int, struct panel_info *);
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int (*reset)(int pipe);
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void (*drv_ic_init)(struct mdfld_dsi_config *dsi_config, int pipe);
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};
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