![Andrei Konovalov](/assets/img/avatar_default.png)
Add support for the video controller IP block included into Xilinx ML300 and ML403 reference designs. Signed-off-by: Andrei Konovalov <akonovalov@ru.mvista.com> Signed-off-by: Antonino Daplas <adaplas@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
382 lines
9.7 KiB
C
382 lines
9.7 KiB
C
/*
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* xilinxfb.c
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*
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* Xilinx TFT LCD frame buffer driver
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*
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* Author: MontaVista Software, Inc.
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* source@mvista.com
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*
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* 2002-2007 (c) MontaVista Software, Inc. This file is licensed under the
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* terms of the GNU General Public License version 2. This program is licensed
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* "as is" without any warranty of any kind, whether express or implied.
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*/
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/*
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* This driver was based on au1100fb.c by MontaVista rewritten for 2.6
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* by Embedded Alley Solutions <source@embeddedalley.com>, which in turn
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* was based on skeletonfb.c, Skeleton for a frame buffer device by
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* Geert Uytterhoeven.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/version.h>
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#include <linux/errno.h>
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#include <linux/string.h>
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#include <linux/mm.h>
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#include <linux/fb.h>
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#include <linux/init.h>
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#include <linux/dma-mapping.h>
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#include <linux/platform_device.h>
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#include <asm/io.h>
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#include <syslib/virtex_devices.h>
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#define DRIVER_NAME "xilinxfb"
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#define DRIVER_DESCRIPTION "Xilinx TFT LCD frame buffer driver"
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/*
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* Xilinx calls it "PLB TFT LCD Controller" though it can also be used for
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* the VGA port on the Xilinx ML40x board. This is a hardware display controller
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* for a 640x480 resolution TFT or VGA screen.
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*
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* The interface to the framebuffer is nice and simple. There are two
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* control registers. The first tells the LCD interface where in memory
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* the frame buffer is (only the 11 most significant bits are used, so
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* don't start thinking about scrolling). The second allows the LCD to
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* be turned on or off as well as rotated 180 degrees.
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*/
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#define NUM_REGS 2
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#define REG_FB_ADDR 0
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#define REG_CTRL 1
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#define REG_CTRL_ENABLE 0x0001
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#define REG_CTRL_ROTATE 0x0002
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/*
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* The hardware only handles a single mode: 640x480 24 bit true
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* color. Each pixel gets a word (32 bits) of memory. Within each word,
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* the 8 most significant bits are ignored, the next 8 bits are the red
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* level, the next 8 bits are the green level and the 8 least
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* significant bits are the blue level. Each row of the LCD uses 1024
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* words, but only the first 640 pixels are displayed with the other 384
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* words being ignored. There are 480 rows.
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*/
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#define BYTES_PER_PIXEL 4
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#define BITS_PER_PIXEL (BYTES_PER_PIXEL * 8)
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#define XRES 640
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#define YRES 480
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#define XRES_VIRTUAL 1024
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#define YRES_VIRTUAL YRES
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#define LINE_LENGTH (XRES_VIRTUAL * BYTES_PER_PIXEL)
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#define FB_SIZE (YRES_VIRTUAL * LINE_LENGTH)
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#define RED_SHIFT 16
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#define GREEN_SHIFT 8
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#define BLUE_SHIFT 0
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#define PALETTE_ENTRIES_NO 16 /* passed to fb_alloc_cmap() */
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/*
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* Here are the default fb_fix_screeninfo and fb_var_screeninfo structures
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*/
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static struct fb_fix_screeninfo xilinx_fb_fix __initdata = {
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.id = "Xilinx",
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.type = FB_TYPE_PACKED_PIXELS,
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.visual = FB_VISUAL_TRUECOLOR,
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.smem_len = FB_SIZE,
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.line_length = LINE_LENGTH,
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.accel = FB_ACCEL_NONE
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};
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static struct fb_var_screeninfo xilinx_fb_var __initdata = {
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.xres = XRES,
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.yres = YRES,
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.xres_virtual = XRES_VIRTUAL,
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.yres_virtual = YRES_VIRTUAL,
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.bits_per_pixel = BITS_PER_PIXEL,
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.red = { RED_SHIFT, 8, 0 },
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.green = { GREEN_SHIFT, 8, 0 },
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.blue = { BLUE_SHIFT, 8, 0 },
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.transp = { 0, 0, 0 },
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.activate = FB_ACTIVATE_NOW
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};
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struct xilinxfb_drvdata {
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struct fb_info info; /* FB driver info record */
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u32 regs_phys; /* phys. address of the control registers */
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u32 __iomem *regs; /* virt. address of the control registers */
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unsigned char __iomem *fb_virt; /* virt. address of the frame buffer */
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dma_addr_t fb_phys; /* phys. address of the frame buffer */
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u32 reg_ctrl_default;
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u32 pseudo_palette[PALETTE_ENTRIES_NO];
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/* Fake palette of 16 colors */
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};
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#define to_xilinxfb_drvdata(_info) \
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container_of(_info, struct xilinxfb_drvdata, info)
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/*
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* The LCD controller has DCR interface to its registers, but all
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* the boards and configurations the driver has been tested with
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* use opb2dcr bridge. So the registers are seen as memory mapped.
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* This macro is to make it simple to add the direct DCR access
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* when it's needed.
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*/
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#define xilinx_fb_out_be32(driverdata, offset, val) \
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out_be32(driverdata->regs + offset, val)
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static int
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xilinx_fb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue,
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unsigned transp, struct fb_info *fbi)
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{
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u32 *palette = fbi->pseudo_palette;
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if (regno >= PALETTE_ENTRIES_NO)
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return -EINVAL;
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if (fbi->var.grayscale) {
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/* Convert color to grayscale.
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* grayscale = 0.30*R + 0.59*G + 0.11*B */
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red = green = blue =
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(red * 77 + green * 151 + blue * 28 + 127) >> 8;
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}
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/* fbi->fix.visual is always FB_VISUAL_TRUECOLOR */
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/* We only handle 8 bits of each color. */
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red >>= 8;
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green >>= 8;
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blue >>= 8;
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palette[regno] = (red << RED_SHIFT) | (green << GREEN_SHIFT) |
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(blue << BLUE_SHIFT);
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return 0;
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}
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static int
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xilinx_fb_blank(int blank_mode, struct fb_info *fbi)
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{
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struct xilinxfb_drvdata *drvdata = to_xilinxfb_drvdata(fbi);
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switch (blank_mode) {
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case FB_BLANK_UNBLANK:
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/* turn on panel */
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xilinx_fb_out_be32(drvdata, REG_CTRL, drvdata->reg_ctrl_default);
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break;
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case FB_BLANK_NORMAL:
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case FB_BLANK_VSYNC_SUSPEND:
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case FB_BLANK_HSYNC_SUSPEND:
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case FB_BLANK_POWERDOWN:
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/* turn off panel */
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xilinx_fb_out_be32(drvdata, REG_CTRL, 0);
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default:
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break;
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}
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return 0; /* success */
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}
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static struct fb_ops xilinxfb_ops =
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{
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.owner = THIS_MODULE,
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.fb_setcolreg = xilinx_fb_setcolreg,
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.fb_blank = xilinx_fb_blank,
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.fb_fillrect = cfb_fillrect,
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.fb_copyarea = cfb_copyarea,
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.fb_imageblit = cfb_imageblit,
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};
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/* === The device driver === */
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static int
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xilinxfb_drv_probe(struct device *dev)
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{
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struct platform_device *pdev;
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struct xilinxfb_platform_data *pdata;
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struct xilinxfb_drvdata *drvdata;
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struct resource *regs_res;
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int retval;
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if (!dev)
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return -EINVAL;
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pdev = to_platform_device(dev);
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pdata = pdev->dev.platform_data;
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if (pdata == NULL) {
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printk(KERN_ERR "Couldn't find platform data.\n");
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return -EFAULT;
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}
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drvdata = kzalloc(sizeof(*drvdata), GFP_KERNEL);
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if (!drvdata) {
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printk(KERN_ERR "Couldn't allocate device private record\n");
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return -ENOMEM;
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}
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dev_set_drvdata(dev, drvdata);
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/* Map the control registers in */
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regs_res = platform_get_resource(pdev, IORESOURCE_IO, 0);
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if (!regs_res || (regs_res->end - regs_res->start + 1 < 8)) {
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printk(KERN_ERR "Couldn't get registers resource\n");
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retval = -EFAULT;
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goto failed1;
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}
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if (!request_mem_region(regs_res->start, 8, DRIVER_NAME)) {
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printk(KERN_ERR
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"Couldn't lock memory region at 0x%08X\n",
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regs_res->start);
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retval = -EBUSY;
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goto failed1;
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}
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drvdata->regs = (u32 __iomem*) ioremap(regs_res->start, 8);
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drvdata->regs_phys = regs_res->start;
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/* Allocate the framebuffer memory */
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drvdata->fb_virt = dma_alloc_coherent(dev, PAGE_ALIGN(FB_SIZE),
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&drvdata->fb_phys, GFP_KERNEL);
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if (!drvdata->fb_virt) {
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printk(KERN_ERR "Could not allocate frame buffer memory\n");
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retval = -ENOMEM;
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goto failed2;
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}
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/* Clear (turn to black) the framebuffer */
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memset_io((void *) drvdata->fb_virt, 0, FB_SIZE);
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/* Tell the hardware where the frame buffer is */
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xilinx_fb_out_be32(drvdata, REG_FB_ADDR, drvdata->fb_phys);
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/* Turn on the display */
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if (pdata->rotate_screen) {
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drvdata->reg_ctrl_default = REG_CTRL_ENABLE | REG_CTRL_ROTATE;
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} else {
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drvdata->reg_ctrl_default = REG_CTRL_ENABLE;
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}
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xilinx_fb_out_be32(drvdata, REG_CTRL, drvdata->reg_ctrl_default);
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/* Fill struct fb_info */
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drvdata->info.device = dev;
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drvdata->info.screen_base = drvdata->fb_virt;
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drvdata->info.fbops = &xilinxfb_ops;
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drvdata->info.fix = xilinx_fb_fix;
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drvdata->info.fix.smem_start = drvdata->fb_phys;
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drvdata->info.pseudo_palette = drvdata->pseudo_palette;
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if (fb_alloc_cmap(&drvdata->info.cmap, PALETTE_ENTRIES_NO, 0) < 0) {
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printk(KERN_ERR "Fail to allocate colormap (%d entries)\n",
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PALETTE_ENTRIES_NO);
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retval = -EFAULT;
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goto failed3;
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}
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drvdata->info.flags = FBINFO_DEFAULT;
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xilinx_fb_var.height = pdata->screen_height_mm;
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xilinx_fb_var.width = pdata->screen_width_mm;
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drvdata->info.var = xilinx_fb_var;
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/* Register new frame buffer */
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if (register_framebuffer(&drvdata->info) < 0) {
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printk(KERN_ERR "Could not register frame buffer\n");
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retval = -EINVAL;
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goto failed4;
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}
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return 0; /* success */
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failed4:
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fb_dealloc_cmap(&drvdata->info.cmap);
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failed3:
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dma_free_coherent(dev, PAGE_ALIGN(FB_SIZE), drvdata->fb_virt,
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drvdata->fb_phys);
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/* Turn off the display */
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xilinx_fb_out_be32(drvdata, REG_CTRL, 0);
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iounmap(drvdata->regs);
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failed2:
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release_mem_region(regs_res->start, 8);
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failed1:
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kfree(drvdata);
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dev_set_drvdata(dev, NULL);
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return retval;
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}
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static int
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xilinxfb_drv_remove(struct device *dev)
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{
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struct xilinxfb_drvdata *drvdata;
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if (!dev)
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return -ENODEV;
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drvdata = (struct xilinxfb_drvdata *) dev_get_drvdata(dev);
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#if !defined(CONFIG_FRAMEBUFFER_CONSOLE) && defined(CONFIG_LOGO)
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xilinx_fb_blank(VESA_POWERDOWN, &drvdata->info);
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#endif
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unregister_framebuffer(&drvdata->info);
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fb_dealloc_cmap(&drvdata->info.cmap);
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dma_free_coherent(dev, PAGE_ALIGN(FB_SIZE), drvdata->fb_virt,
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drvdata->fb_phys);
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/* Turn off the display */
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xilinx_fb_out_be32(drvdata, REG_CTRL, 0);
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iounmap(drvdata->regs);
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release_mem_region(drvdata->regs_phys, 8);
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kfree(drvdata);
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dev_set_drvdata(dev, NULL);
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return 0;
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}
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static struct device_driver xilinxfb_driver = {
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.name = DRIVER_NAME,
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.bus = &platform_bus_type,
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.probe = xilinxfb_drv_probe,
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.remove = xilinxfb_drv_remove
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};
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static int __init
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xilinxfb_init(void)
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{
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/*
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* No kernel boot options used,
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* so we just need to register the driver
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*/
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return driver_register(&xilinxfb_driver);
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}
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static void __exit
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xilinxfb_cleanup(void)
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{
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driver_unregister(&xilinxfb_driver);
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}
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module_init(xilinxfb_init);
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module_exit(xilinxfb_cleanup);
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MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
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MODULE_DESCRIPTION(DRIVER_DESCRIPTION);
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MODULE_LICENSE("GPL");
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