![Steven King](/assets/img/avatar_default.png)
Since Grant has added the coldfire-qspi driver to next-spi, here is the platform support for the parts that have qspi hardware. This sets up gpio to do the spi chip select using the default chip select pins; it should be trivial for boards that require different or additional spi chip selects to use other gpios as needed. Signed-off-by: Steven King <sfking@fdwdc.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
385 lines
8.6 KiB
C
385 lines
8.6 KiB
C
/***************************************************************************/
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/*
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* linux/arch/m68knommu/platform/527x/config.c
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*
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* Sub-architcture dependant initialization code for the Freescale
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* 5270/5271 CPUs.
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*
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* Copyright (C) 1999-2004, Greg Ungerer (gerg@snapgear.com)
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* Copyright (C) 2001-2004, SnapGear Inc. (www.snapgear.com)
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*/
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/***************************************************************************/
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#include <linux/kernel.h>
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#include <linux/param.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/spi/spi.h>
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#include <linux/gpio.h>
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#include <asm/machdep.h>
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#include <asm/coldfire.h>
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#include <asm/mcfsim.h>
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#include <asm/mcfuart.h>
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#include <asm/mcfqspi.h>
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/***************************************************************************/
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static struct mcf_platform_uart m527x_uart_platform[] = {
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{
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.mapbase = MCF_MBAR + MCFUART_BASE1,
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.irq = MCFINT_VECBASE + MCFINT_UART0,
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},
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{
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.mapbase = MCF_MBAR + MCFUART_BASE2,
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.irq = MCFINT_VECBASE + MCFINT_UART1,
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},
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{
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.mapbase = MCF_MBAR + MCFUART_BASE3,
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.irq = MCFINT_VECBASE + MCFINT_UART2,
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},
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{ },
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};
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static struct platform_device m527x_uart = {
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.name = "mcfuart",
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.id = 0,
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.dev.platform_data = m527x_uart_platform,
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};
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static struct resource m527x_fec0_resources[] = {
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{
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.start = MCF_MBAR + 0x1000,
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.end = MCF_MBAR + 0x1000 + 0x7ff,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = 64 + 23,
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.end = 64 + 23,
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = 64 + 27,
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.end = 64 + 27,
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = 64 + 29,
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.end = 64 + 29,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct resource m527x_fec1_resources[] = {
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{
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.start = MCF_MBAR + 0x1800,
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.end = MCF_MBAR + 0x1800 + 0x7ff,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = 128 + 23,
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.end = 128 + 23,
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = 128 + 27,
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.end = 128 + 27,
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = 128 + 29,
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.end = 128 + 29,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device m527x_fec[] = {
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{
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.name = "fec",
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.id = 0,
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.num_resources = ARRAY_SIZE(m527x_fec0_resources),
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.resource = m527x_fec0_resources,
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},
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{
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.name = "fec",
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.id = 1,
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.num_resources = ARRAY_SIZE(m527x_fec1_resources),
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.resource = m527x_fec1_resources,
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},
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};
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#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
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static struct resource m527x_qspi_resources[] = {
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{
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.start = MCFQSPI_IOBASE,
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.end = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = MCFINT_VECBASE + MCFINT_QSPI,
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.end = MCFINT_VECBASE + MCFINT_QSPI,
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.flags = IORESOURCE_IRQ,
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},
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};
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#if defined(CONFIG_M5271)
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#define MCFQSPI_CS0 91
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#define MCFQSPI_CS1 92
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#define MCFQSPI_CS2 99
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#define MCFQSPI_CS3 103
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#elif defined(CONFIG_M5275)
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#define MCFQSPI_CS0 59
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#define MCFQSPI_CS1 60
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#define MCFQSPI_CS2 61
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#define MCFQSPI_CS3 62
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#endif
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static int m527x_cs_setup(struct mcfqspi_cs_control *cs_control)
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{
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int status;
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status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0");
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if (status) {
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pr_debug("gpio_request for MCFQSPI_CS0 failed\n");
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goto fail0;
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}
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status = gpio_direction_output(MCFQSPI_CS0, 1);
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if (status) {
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pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n");
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goto fail1;
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}
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status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1");
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if (status) {
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pr_debug("gpio_request for MCFQSPI_CS1 failed\n");
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goto fail1;
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}
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status = gpio_direction_output(MCFQSPI_CS1, 1);
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if (status) {
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pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n");
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goto fail2;
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}
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status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2");
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if (status) {
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pr_debug("gpio_request for MCFQSPI_CS2 failed\n");
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goto fail2;
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}
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status = gpio_direction_output(MCFQSPI_CS2, 1);
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if (status) {
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pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n");
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goto fail3;
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}
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status = gpio_request(MCFQSPI_CS3, "MCFQSPI_CS3");
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if (status) {
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pr_debug("gpio_request for MCFQSPI_CS3 failed\n");
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goto fail3;
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}
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status = gpio_direction_output(MCFQSPI_CS3, 1);
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if (status) {
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pr_debug("gpio_direction_output for MCFQSPI_CS3 failed\n");
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goto fail4;
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}
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return 0;
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fail4:
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gpio_free(MCFQSPI_CS3);
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fail3:
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gpio_free(MCFQSPI_CS2);
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fail2:
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gpio_free(MCFQSPI_CS1);
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fail1:
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gpio_free(MCFQSPI_CS0);
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fail0:
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return status;
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}
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static void m527x_cs_teardown(struct mcfqspi_cs_control *cs_control)
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{
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gpio_free(MCFQSPI_CS3);
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gpio_free(MCFQSPI_CS2);
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gpio_free(MCFQSPI_CS1);
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gpio_free(MCFQSPI_CS0);
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}
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static void m527x_cs_select(struct mcfqspi_cs_control *cs_control,
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u8 chip_select, bool cs_high)
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{
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switch (chip_select) {
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case 0:
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gpio_set_value(MCFQSPI_CS0, cs_high);
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break;
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case 1:
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gpio_set_value(MCFQSPI_CS1, cs_high);
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break;
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case 2:
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gpio_set_value(MCFQSPI_CS2, cs_high);
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break;
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case 3:
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gpio_set_value(MCFQSPI_CS3, cs_high);
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break;
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}
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}
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static void m527x_cs_deselect(struct mcfqspi_cs_control *cs_control,
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u8 chip_select, bool cs_high)
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{
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switch (chip_select) {
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case 0:
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gpio_set_value(MCFQSPI_CS0, !cs_high);
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break;
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case 1:
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gpio_set_value(MCFQSPI_CS1, !cs_high);
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break;
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case 2:
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gpio_set_value(MCFQSPI_CS2, !cs_high);
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break;
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case 3:
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gpio_set_value(MCFQSPI_CS3, !cs_high);
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break;
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}
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}
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static struct mcfqspi_cs_control m527x_cs_control = {
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.setup = m527x_cs_setup,
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.teardown = m527x_cs_teardown,
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.select = m527x_cs_select,
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.deselect = m527x_cs_deselect,
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};
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static struct mcfqspi_platform_data m527x_qspi_data = {
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.bus_num = 0,
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.num_chipselect = 4,
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.cs_control = &m527x_cs_control,
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};
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static struct platform_device m527x_qspi = {
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.name = "mcfqspi",
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.id = 0,
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.num_resources = ARRAY_SIZE(m527x_qspi_resources),
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.resource = m527x_qspi_resources,
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.dev.platform_data = &m527x_qspi_data,
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};
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static void __init m527x_qspi_init(void)
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{
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#if defined(CONFIG_M5271)
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u16 par;
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/* setup QSPS pins for QSPI with gpio CS control */
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writeb(0x1f, MCFGPIO_PAR_QSPI);
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/* and CS2 & CS3 as gpio */
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par = readw(MCFGPIO_PAR_TIMER);
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par &= 0x3f3f;
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writew(par, MCFGPIO_PAR_TIMER);
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#elif defined(CONFIG_M5275)
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/* setup QSPS pins for QSPI with gpio CS control */
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writew(0x003e, MCFGPIO_PAR_QSPI);
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#endif
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}
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#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */
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static struct platform_device *m527x_devices[] __initdata = {
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&m527x_uart,
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&m527x_fec[0],
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#ifdef CONFIG_FEC2
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&m527x_fec[1],
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#endif
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#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
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&m527x_qspi,
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#endif
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};
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/***************************************************************************/
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static void __init m527x_uart_init_line(int line, int irq)
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{
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u16 sepmask;
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if ((line < 0) || (line > 2))
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return;
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/*
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* External Pin Mask Setting & Enable External Pin for Interface
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*/
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sepmask = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART);
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if (line == 0)
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sepmask |= UART0_ENABLE_MASK;
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else if (line == 1)
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sepmask |= UART1_ENABLE_MASK;
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else if (line == 2)
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sepmask |= UART2_ENABLE_MASK;
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writew(sepmask, MCF_IPSBAR + MCF_GPIO_PAR_UART);
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}
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static void __init m527x_uarts_init(void)
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{
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const int nrlines = ARRAY_SIZE(m527x_uart_platform);
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int line;
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for (line = 0; (line < nrlines); line++)
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m527x_uart_init_line(line, m527x_uart_platform[line].irq);
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}
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/***************************************************************************/
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static void __init m527x_fec_init(void)
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{
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u16 par;
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u8 v;
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/* Set multi-function pins to ethernet mode for fec0 */
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#if defined(CONFIG_M5271)
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v = readb(MCF_IPSBAR + 0x100047);
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writeb(v | 0xf0, MCF_IPSBAR + 0x100047);
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#else
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par = readw(MCF_IPSBAR + 0x100082);
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writew(par | 0xf00, MCF_IPSBAR + 0x100082);
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v = readb(MCF_IPSBAR + 0x100078);
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writeb(v | 0xc0, MCF_IPSBAR + 0x100078);
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#endif
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#ifdef CONFIG_FEC2
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/* Set multi-function pins to ethernet mode for fec1 */
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par = readw(MCF_IPSBAR + 0x100082);
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writew(par | 0xa0, MCF_IPSBAR + 0x100082);
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v = readb(MCF_IPSBAR + 0x100079);
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writeb(v | 0xc0, MCF_IPSBAR + 0x100079);
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#endif
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}
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/***************************************************************************/
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static void m527x_cpu_reset(void)
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{
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local_irq_disable();
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__raw_writeb(MCF_RCR_SWRESET, MCF_IPSBAR + MCF_RCR);
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}
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/***************************************************************************/
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void __init config_BSP(char *commandp, int size)
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{
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mach_reset = m527x_cpu_reset;
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m527x_uarts_init();
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m527x_fec_init();
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#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
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m527x_qspi_init();
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#endif
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}
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/***************************************************************************/
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static int __init init_BSP(void)
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{
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platform_add_devices(m527x_devices, ARRAY_SIZE(m527x_devices));
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return 0;
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}
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arch_initcall(init_BSP);
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/***************************************************************************/
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