![Pekka Enberg](/assets/img/avatar_default.png)
As this typedef is used everywhere in the driver, remove it in a separate patch. Signed-off-by: Pekka Enberg <penberg@cs.helsinki.fi> Acked-by: Pavel Machek <pavel@suse.cz> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
546 lines
15 KiB
C
546 lines
15 KiB
C
#ifndef __WINBOND_WBHAL_S_H
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#define __WINBOND_WBHAL_S_H
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#include <linux/types.h>
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#include <linux/if_ether.h> /* for ETH_ALEN */
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//[20040722 WK]
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#define HAL_LED_SET_MASK 0x001c //20060901 Extend
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#define HAL_LED_SET_SHIFT 2
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//supported RF type
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#define RF_MAXIM_2825 0
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#define RF_MAXIM_2827 1
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#define RF_MAXIM_2828 2
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#define RF_MAXIM_2829 3
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#define RF_MAXIM_V1 15
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#define RF_AIROHA_2230 16
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#define RF_AIROHA_7230 17
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#define RF_AIROHA_2230S 18 // 20060420 Add this
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// #define RF_RFMD_2959 32 // 20060626 Remove all about RFMD
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#define RF_WB_242 33
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#define RF_WB_242_1 34 // 20060619.5 Add
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#define RF_DECIDE_BY_INF 255
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//----------------------------------------------------------------
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// The follow define connect to upper layer
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// User must modify for connection between HAL and upper layer
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//----------------------------------------------------------------
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/////////////////////////////////////////////////////////////////////////////////////////////////////
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//================================================================================================
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// Common define
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//================================================================================================
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#define HAL_USB_MODE_BURST( _H ) (_H->SoftwareSet & 0x20 ) // Bit 5 20060901 Modify
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// Scan interval
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#define SCAN_MAX_CHNL_TIME (50)
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// For TxL2 Frame typr recognise
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#define FRAME_TYPE_802_3_DATA 0
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#define FRAME_TYPE_802_11_MANAGEMENT 1
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#define FRAME_TYPE_802_11_MANAGEMENT_CHALLENGE 2
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#define FRAME_TYPE_802_11_CONTROL 3
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#define FRAME_TYPE_802_11_DATA 4
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#define FRAME_TYPE_PROMISCUOUS 5
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// The follow definition is used for convert the frame--------------------
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#define DOT_11_SEQUENCE_OFFSET 22 //Sequence control offset
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#define DOT_3_TYPE_OFFSET 12
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#define DOT_11_MAC_HEADER_SIZE 24
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#define DOT_11_SNAP_SIZE 6
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#define DOT_11_TYPE_OFFSET 30 //The start offset of 802.11 Frame. Type encapsulatuin.
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#define DEFAULT_SIFSTIME 10
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#define DEFAULT_FRAGMENT_THRESHOLD 2346 // No fragment
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#define DEFAULT_MSDU_LIFE_TIME 0xffff
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#define LONG_PREAMBLE_PLUS_PLCPHEADER_TIME (144+48)
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#define SHORT_PREAMBLE_PLUS_PLCPHEADER_TIME (72+24)
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#define PREAMBLE_PLUS_SIGNAL_PLUS_SIGNALEXTENSION (16+4+6)
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#define Tsym 4
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// Frame Type of Bits (2, 3)---------------------------------------------
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#define MAC_TYPE_MANAGEMENT 0x00
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#define MAC_TYPE_CONTROL 0x04
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#define MAC_TYPE_DATA 0x08
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#define MASK_FRAGMENT_NUMBER 0x000F
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#define SEQUENCE_NUMBER_SHIFT 4
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#define HAL_WOL_TYPE_WAKEUP_FRAME 0x01
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#define HAL_WOL_TYPE_MAGIC_PACKET 0x02
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// 20040106 ADDED
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#define HAL_KEYTYPE_WEP40 0
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#define HAL_KEYTYPE_WEP104 1
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#define HAL_KEYTYPE_TKIP 2 // 128 bit key
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#define HAL_KEYTYPE_AES_CCMP 3 // 128 bit key
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// For VM state
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enum {
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VM_STOP = 0,
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VM_RUNNING,
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VM_COMPLETED
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};
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//-----------------------------------------------------
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// Normal Key table format
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//-----------------------------------------------------
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// The order of KEY index is MAPPING_KEY_START_INDEX > GROUP_KEY_START_INDEX
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#define MAX_KEY_TABLE 24 // 24 entry for storing key data
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#define GROUP_KEY_START_INDEX 4
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#define MAPPING_KEY_START_INDEX 8
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//--------------------------------------------------------
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// Descriptor
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//--------------------------------------------------------
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#define MAX_DESCRIPTOR_BUFFER_INDEX 8 // Have to multiple of 2
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//#define FLAG_ERROR_TX_MASK cpu_to_le32(0x000000bf) //20061009 marked by anson's endian
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#define FLAG_ERROR_TX_MASK 0x000000bf //20061009 anson's endian
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//#define FLAG_ERROR_RX_MASK 0x00000c3f
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//#define FLAG_ERROR_RX_MASK cpu_to_le32(0x0000083f) //20061009 marked by anson's endian
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//Don't care replay error,
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//it is handled by S/W
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#define FLAG_ERROR_RX_MASK 0x0000083f //20060926 anson's endian
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#define FLAG_BAND_RX_MASK 0x10000000 //Bit 28
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typedef struct _R00_DESCRIPTOR
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{
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union
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{
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u32 value;
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#ifdef _BIG_ENDIAN_ //20060926 anson's endian
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struct
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{
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u32 R00_packet_or_buffer_status:1;
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u32 R00_packet_in_fifo:1;
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u32 R00_RESERVED:2;
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u32 R00_receive_byte_count:12;
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u32 R00_receive_time_index:16;
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};
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#else
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struct
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{
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u32 R00_receive_time_index:16;
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u32 R00_receive_byte_count:12;
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u32 R00_RESERVED:2;
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u32 R00_packet_in_fifo:1;
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u32 R00_packet_or_buffer_status:1;
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};
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#endif
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};
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} R00_DESCRIPTOR, *PR00_DESCRIPTOR;
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typedef struct _T00_DESCRIPTOR
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{
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union
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{
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u32 value;
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#ifdef _BIG_ENDIAN_ //20061009 anson's endian
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struct
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{
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u32 T00_first_mpdu:1; // for hardware use
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u32 T00_last_mpdu:1; // for hardware use
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u32 T00_IsLastMpdu:1;// 0: not 1:Yes for software used
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u32 T00_IgnoreResult:1;// The same mechanism with T00 setting. 050111 Modify for TS
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u32 T00_RESERVED_ID:2;//3 bit ID reserved
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u32 T00_tx_packet_id:4;//930519.4.e 930810.3.c
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u32 T00_RESERVED:4;
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u32 T00_header_length:6;
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u32 T00_frame_length:12;
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};
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#else
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struct
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{
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u32 T00_frame_length:12;
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u32 T00_header_length:6;
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u32 T00_RESERVED:4;
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u32 T00_tx_packet_id:4;//930519.4.e 930810.3.c
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u32 T00_RESERVED_ID:2;//3 bit ID reserved
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u32 T00_IgnoreResult:1;// The same mechanism with T00 setting. 050111 Modify for TS
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u32 T00_IsLastMpdu:1;// 0: not 1:Yes for software used
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u32 T00_last_mpdu:1; // for hardware use
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u32 T00_first_mpdu:1; // for hardware use
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};
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#endif
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};
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} T00_DESCRIPTOR, *PT00_DESCRIPTOR;
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typedef struct _R01_DESCRIPTOR
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{
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union
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{
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u32 value;
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#ifdef _BIG_ENDIAN_ //20060926 add by anson's endian
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struct
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{
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u32 R01_RESERVED:3;
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u32 R01_mod_type:1;
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u32 R01_pre_type:1;
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u32 R01_data_rate:3;
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u32 R01_AGC_state:8;
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u32 R01_LNA_state:2;
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u32 R01_decryption_method:2;
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u32 R01_mic_error:1;
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u32 R01_replay:1;
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u32 R01_broadcast_frame:1;
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u32 R01_multicast_frame:1;
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u32 R01_directed_frame:1;
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u32 R01_receive_frame_antenna_selection:1;
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u32 R01_frame_receive_during_atim_window:1;
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u32 R01_protocol_version_error:1;
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u32 R01_authentication_frame_icv_error:1;
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u32 R01_null_key_to_authentication_frame:1;
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u32 R01_icv_error:1;
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u32 R01_crc_error:1;
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};
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#else
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struct
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{
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u32 R01_crc_error:1;
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u32 R01_icv_error:1;
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u32 R01_null_key_to_authentication_frame:1;
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u32 R01_authentication_frame_icv_error:1;
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u32 R01_protocol_version_error:1;
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u32 R01_frame_receive_during_atim_window:1;
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u32 R01_receive_frame_antenna_selection:1;
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u32 R01_directed_frame:1;
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u32 R01_multicast_frame:1;
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u32 R01_broadcast_frame:1;
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u32 R01_replay:1;
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u32 R01_mic_error:1;
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u32 R01_decryption_method:2;
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u32 R01_LNA_state:2;
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u32 R01_AGC_state:8;
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u32 R01_data_rate:3;
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u32 R01_pre_type:1;
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u32 R01_mod_type:1;
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u32 R01_RESERVED:3;
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};
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#endif
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};
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} R01_DESCRIPTOR, *PR01_DESCRIPTOR;
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typedef struct _T01_DESCRIPTOR
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{
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union
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{
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u32 value;
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#ifdef _BIG_ENDIAN_ //20061009 anson's endian
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struct
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{
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u32 T01_rts_cts_duration:16;
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u32 T01_fall_back_rate:3;
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u32 T01_add_rts:1;
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u32 T01_add_cts:1;
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u32 T01_modulation_type:1;
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u32 T01_plcp_header_length:1;
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u32 T01_transmit_rate:3;
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u32 T01_wep_id:2;
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u32 T01_add_challenge_text:1;
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u32 T01_inhibit_crc:1;
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u32 T01_loop_back_wep_mode:1;
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u32 T01_retry_abort_ebable:1;
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};
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#else
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struct
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{
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u32 T01_retry_abort_ebable:1;
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u32 T01_loop_back_wep_mode:1;
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u32 T01_inhibit_crc:1;
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u32 T01_add_challenge_text:1;
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u32 T01_wep_id:2;
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u32 T01_transmit_rate:3;
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u32 T01_plcp_header_length:1;
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u32 T01_modulation_type:1;
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u32 T01_add_cts:1;
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u32 T01_add_rts:1;
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u32 T01_fall_back_rate:3;
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u32 T01_rts_cts_duration:16;
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};
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#endif
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};
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} T01_DESCRIPTOR, *PT01_DESCRIPTOR;
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typedef struct _T02_DESCRIPTOR
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{
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union
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{
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u32 value;
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#ifdef _BIG_ENDIAN_ //20061009 add by anson's endian
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struct
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{
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u32 T02_IsLastMpdu:1;// The same mechanism with T00 setting
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u32 T02_IgnoreResult:1;// The same mechanism with T00 setting. 050111 Modify for TS
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u32 T02_RESERVED_ID:2;// The same mechanism with T00 setting
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u32 T02_Tx_PktID:4;
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u32 T02_MPDU_Cnt:4;
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u32 T02_RTS_Cnt:4;
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u32 T02_RESERVED:7;
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u32 T02_transmit_complete:1;
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u32 T02_transmit_abort_due_to_TBTT:1;
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u32 T02_effective_transmission_rate:1;
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u32 T02_transmit_without_encryption_due_to_wep_on_false:1;
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u32 T02_discard_due_to_null_wep_key:1;
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u32 T02_RESERVED_1:1;
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u32 T02_out_of_MaxTxMSDULiftTime:1;
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u32 T02_transmit_abort:1;
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u32 T02_transmit_fail:1;
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};
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#else
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struct
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{
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u32 T02_transmit_fail:1;
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u32 T02_transmit_abort:1;
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u32 T02_out_of_MaxTxMSDULiftTime:1;
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u32 T02_RESERVED_1:1;
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u32 T02_discard_due_to_null_wep_key:1;
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u32 T02_transmit_without_encryption_due_to_wep_on_false:1;
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u32 T02_effective_transmission_rate:1;
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u32 T02_transmit_abort_due_to_TBTT:1;
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u32 T02_transmit_complete:1;
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u32 T02_RESERVED:7;
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u32 T02_RTS_Cnt:4;
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u32 T02_MPDU_Cnt:4;
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u32 T02_Tx_PktID:4;
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u32 T02_RESERVED_ID:2;// The same mechanism with T00 setting
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u32 T02_IgnoreResult:1;// The same mechanism with T00 setting. 050111 Modify for TS
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u32 T02_IsLastMpdu:1;// The same mechanism with T00 setting
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};
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#endif
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};
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} T02_DESCRIPTOR, *PT02_DESCRIPTOR;
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typedef struct _DESCRIPTOR { // Skip length = 8 DWORD
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// ID for descriptor ---, The field doesn't be cleard in the operation of Descriptor definition
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u8 Descriptor_ID;
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//----------------------The above region doesn't be cleared by DESCRIPTOR_RESET------
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u8 RESERVED[3];
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u16 FragmentThreshold;
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u8 InternalUsed;//Only can be used by operation of descriptor definition
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u8 Type;// 0: 802.3 1:802.11 data frame 2:802.11 management frame
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u8 PreambleMode;// 0: short 1:long
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u8 TxRate;
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u8 FragmentCount;
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u8 EapFix; // For speed up key install
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// For R00 and T00 ----------------------------------------------
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union
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{
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R00_DESCRIPTOR R00;
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T00_DESCRIPTOR T00;
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};
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// For R01 and T01 ----------------------------------------------
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union
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{
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R01_DESCRIPTOR R01;
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T01_DESCRIPTOR T01;
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};
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// For R02 and T02 ----------------------------------------------
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union
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{
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u32 R02;
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T02_DESCRIPTOR T02;
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};
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// For R03 and T03 ----------------------------------------------
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// For software used
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union
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{
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u32 R03;
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u32 T03;
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struct
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{
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u8 buffer_number;
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u8 buffer_start_index;
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u16 buffer_total_size;
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};
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};
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// For storing the buffer
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u16 buffer_size[ MAX_DESCRIPTOR_BUFFER_INDEX ];
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void* buffer_address[ MAX_DESCRIPTOR_BUFFER_INDEX ];//931130.4.q
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} DESCRIPTOR, *PDESCRIPTOR;
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#define DEFAULT_NULL_PACKET_COUNT 180000 //20060828.1 Add. 180 seconds
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#define MAX_TXVGA_EEPROM 9 //How many word(u16) of EEPROM will be used for TxVGA
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#define MAX_RF_PARAMETER 32
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typedef struct _TXVGA_FOR_50 {
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u8 ChanNo;
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u8 TxVgaValue;
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} TXVGA_FOR_50;
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//=====================================================================
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// Device related include
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//=====================================================================
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#include "wbusb_s.h"
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#include "wb35reg_s.h"
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#include "wb35tx_s.h"
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#include "wb35rx_s.h"
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// For Hal using ==================================================================
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struct hw_data {
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// For compatible with 33
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u32 revision;
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u32 BB3c_cal; // The value for Tx calibration comes from EEPROM
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u32 BB54_cal; // The value for Rx calibration comes from EEPROM
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// For surprise remove
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u32 SurpriseRemove; // 0: Normal 1: Surprise remove
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u8 InitialResource;
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u8 IsKeyPreSet;
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u8 CalOneTime; // 20060630.1
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u8 VCO_trim;
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// For Fix 1'st DMA bug
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u32 FragCount;
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u32 DMAFix; //V1_DMA_FIX The variable can be removed if driver want to save mem space for V2.
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//===============================================
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// Definition for MAC address
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//===============================================
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u8 PermanentMacAddress[ETH_ALEN + 2]; // The Enthernet addr that are stored in EEPROM. + 2 to 8-byte alignment
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u8 CurrentMacAddress[ETH_ALEN + 2]; // The Enthernet addr that are in used. + 2 to 8-byte alignment
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//=====================================================================
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// Definition for 802.11
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//=====================================================================
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u8 *bssid_pointer; // Used by hal_get_bssid for return value
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u8 bssid[8];// Only 6 byte will be used. 8 byte is required for read buffer
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u8 ssid[32];// maximum ssid length is 32 byte
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u16 AID;
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u8 ssid_length;
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u8 Channel;
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u16 ListenInterval;
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u16 CapabilityInformation;
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u16 BeaconPeriod;
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u16 ProbeDelay;
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u8 bss_type;// 0: IBSS_NET or 1:ESS_NET
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u8 preamble;// 0: short preamble, 1: long preamble
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u8 slot_time_select;// 9 or 20 value
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u8 phy_type;// Phy select
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u32 phy_para[MAX_RF_PARAMETER];
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u32 phy_number;
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u32 CurrentRadioSw; // 20060320.2 0:On 1:Off
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u32 CurrentRadioHw; // 20060825 0:On 1:Off
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u8 *power_save_point; // Used by hal_get_power_save_mode for return value
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u8 cwmin;
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u8 desired_power_save;
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u8 dtim;// Is running dtim
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u8 mapping_key_replace_index;//In Key table, the next index be replaced 931130.4.r
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u16 MaxReceiveLifeTime;
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u16 FragmentThreshold;
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u16 FragmentThreshold_tmp;
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u16 cwmax;
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u8 Key_slot[MAX_KEY_TABLE][8]; //Ownership record for key slot. For Alignment
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u32 Key_content[MAX_KEY_TABLE][12]; // 10DW for each entry + 2 for burst command( Off and On valid bit)
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u8 CurrentDefaultKeyIndex;
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u32 CurrentDefaultKeyLength;
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//========================================================================
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// Variable for each module
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//========================================================================
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struct wb_usb WbUsb; // Need WbUsb.h
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struct wb35_reg reg; // Need Wb35Reg.h
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struct wb35_tx Wb35Tx; // Need Wb35Tx.h
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struct wb35_rx Wb35Rx; // Need Wb35Rx.h
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struct timer_list LEDTimer;// For LED
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u32 LEDpoint;// For LED
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u32 dto_tx_retry_count; // LA20040210_DTO kevin
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u32 dto_tx_frag_count; // LA20040210_DTO kevin
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u32 rx_ok_count[13]; // index=0: total rx ok
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//u32 rx_ok_bytes[13]; // index=0, total rx ok bytes
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u32 rx_err_count[13]; // index=0: total rx err
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//for Tx debug
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u32 tx_TBTT_start_count;
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u32 tx_ETR_count;
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u32 tx_WepOn_false_count;
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u32 tx_Null_key_count;
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u32 tx_retry_count[8];
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u8 PowerIndexFromEEPROM; // For 2412MHz
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u8 power_index;
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u8 IsWaitJoinComplete; // TRUE: set join request
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u8 band;
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u16 SoftwareSet;
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u16 Reserved_s;
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u32 IsInitOK; // 0: Driver starting 1: Driver init OK
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// For Phy calibration
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s32 iq_rsdl_gain_tx_d2;
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s32 iq_rsdl_phase_tx_d2;
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u32 txvga_setting_for_cal; // 20060703.1 Add
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|
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u8 TxVgaSettingInEEPROM[ (((MAX_TXVGA_EEPROM*2)+3) & ~0x03) ]; // 20060621 For backup EEPROM value
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u8 TxVgaFor24[16]; // Max is 14, 2 for alignment
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TXVGA_FOR_50 TxVgaFor50[36]; // 35 channels in 5G. 35x2 = 70 byte. 2 for alignments
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|
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u16 Scan_Interval;
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u16 RESERVED6;
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|
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// LED control
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|
u32 LED_control;
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// LED_control 4 byte: Gray_Led_1[3] Gray_Led_0[2] Led[1] Led[0]
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// Gray_Led
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// For Led gray setting
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// Led
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// 0: normal control, LED behavior will decide by EEPROM setting
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// 1: Turn off specific LED
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|
// 2: Always on specific LED
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// 3: slow blinking specific LED
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// 4: fast blinking specific LED
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// 5: WPS led control is set. Led0 is Red, Led1 id Green
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// Led[1] is parameter for WPS LED mode
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// // 1:InProgress 2: Error 3: Session overlap 4: Success 20061108 control
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|
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u32 LED_LinkOn; //Turn LED on control
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|
u32 LED_Scanning; // Let LED in scan process control
|
|
u32 LED_Blinking; // Temp variable for shining
|
|
u32 RxByteCountLast;
|
|
u32 TxByteCountLast;
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|
|
|
atomic_t SurpriseRemoveCount;
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|
|
|
// For global timer
|
|
u32 time_count;//TICK_TIME_100ms 1 = 100ms
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|
|
|
// For error recover
|
|
u32 HwStop;
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|
|
|
// 20060828.1 for avoid AP disconnect
|
|
u32 NullPacketCount;
|
|
|
|
};
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|
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#endif
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