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Originally written by Guenter Gebhardt <g.gebhardt@meilhaus.de> and Krzysztof Gantzke <k.gantzke@meilhaus.de> This is the drv/lnx/mod directory of ME-IDS 1.2.9 tarball with some files from drv/lnx/include. Signed-off-by: David Kiliani <mail@davidkiliani.de> Cc: Guenter Gebhardt <g.gebhardt@meilhaus.de> Cc: Krzysztof Gantzke <k.gantzke@meilhaus.de> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
54 lines
2.2 KiB
C
54 lines
2.2 KiB
C
/**
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* @file meplx_reg.h
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*
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* @brief PLX 9052 PCI bridge register definitions.
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* @note Copyright (C) 2007 Meilhaus Electronic GmbH (support@meilhaus.de)
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* @author Guenter Gebhardt
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*/
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/*
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* Copyright (C) 2007 Meilhaus Electronic GmbH (support@meilhaus.de)
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef _MEPLX_REG_H_
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#define _MEPLX_REG_H_
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#ifdef __KERNEL__
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#define PLX_INTCSR 0x4C /**< Interrupt control and status register. */
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#define PLX_INTCSR_LOCAL_INT1_EN 0x01 /**< If set, local interrupt 1 is enabled (r/w). */
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#define PLX_INTCSR_LOCAL_INT1_POL 0x02 /**< If set, local interrupt 1 polarity is active high (r/w). */
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#define PLX_INTCSR_LOCAL_INT1_STATE 0x04 /**< If set, local interrupt 1 is active (r/_). */
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#define PLX_INTCSR_LOCAL_INT2_EN 0x08 /**< If set, local interrupt 2 is enabled (r/w). */
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#define PLX_INTCSR_LOCAL_INT2_POL 0x10 /**< If set, local interrupt 2 polarity is active high (r/w). */
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#define PLX_INTCSR_LOCAL_INT2_STATE 0x20 /**< If set, local interrupt 2 is active (r/_). */
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#define PLX_INTCSR_PCI_INT_EN 0x40 /**< If set, PCI interrupt is enabled (r/w). */
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#define PLX_INTCSR_SOFT_INT 0x80 /**< If set, a software interrupt is generated (r/w). */
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#define PLX_ICR 0x50 /**< Initialization control register. */
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#define PLX_ICR_BIT_EEPROM_CLOCK_SET 0x01000000
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#define PLX_ICR_BIT_EEPROM_CHIP_SELECT 0x02000000
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#define PLX_ICR_BIT_EEPROM_WRITE 0x04000000
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#define PLX_ICR_BIT_EEPROM_READ 0x08000000
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#define PLX_ICR_BIT_EEPROM_VALID 0x10000000
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#define PLX_ICR_MASK_EEPROM 0x1F000000
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#define EEPROM_DELAY 1
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#endif
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#endif
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