Blackfin dual core BF561 processor can support SMP like features.
https://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:smp-like
In this patch, we provide SMP extend to Blackfin header files
and machine common code
Signed-off-by: Graf Yang <graf.yang@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
- Remove SSYNC()
- Use irq_to_gpio where applicable
- Remove gpio_edge_triggered bitfield, check irq_desc fields instead.
- Remove gpio_both_edge_triggeredb bitfield, check irq_desc fields
instead.
- Use BITMAP and bitops on gpio_enabled
- Preferably use 32-bit
- Looking at the disassembly this indeed saves quite a few instructions.
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
- remove SSYNC() left over from irq init split
- do not force SSYNC() when masking/unmasking IRQs in the SIC
as any order enforced by the hardware should already be enforced
by software
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
The whole story:
Before BF51x merged, all the MAX_BLACKFIN_GPIOS are integral multiple of GPIO_BANKSIZE (= 16).
But BF51x provides MAX_BLACKFIN_GPIOS = 40 which includes 3 banks and the 3rd bank has only 8
GPIO pins.
Therefore, gpio_bank() macros is correct when you try to find a GPIO in which bank (GPIO_35 is
in bank 2). But on BF51x gpio_bank(MAX_BLACKFIN_GPIOS) only gives out 2 banks instead of 3
banks for some static array initialization.
This patch add a new macros gpio_bank_n() and GPIO_BANK_NUM to do bank number caculating and
remain the gpio_bank() macros for positioning a gpio in which bank.
Signed-off-by: Bryan Wu <cooloney@kernel.org>
our kernel should be sane now, and we want to catch NULL bugs,
not ignore them
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
The original code defined _exception_stack but not alloc space for the exception
stack. In exception, this area is over written by exception stack. Common kernel
luckly boot up, but SMP kernel stuck.
Signed-off-by: Graf Yang <graf.yang@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
allow people to stick exception stack into L1 scratch
and make sure it gets placed into .bss sections rather than .data
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Make sure IFLUSH is not the last instruction in the hardware loop to avoid
infinite core stall.
The dcache/icache function that only gets used in writeback mode was putting
IFLUSH as the last instruction in the hardware loop ... we know from design
that this may often lead to inifite core stalling, so switch the FLUSH/IFLUSH
order.
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
The cache code I added flushes 1 line too little if the start address is
not aligned to the cache size. Cache align the start address so that when
we straddle cache aligns, we get the right count.
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/blackfin-2.6:
Blackfin arch: make sure cycles is marked as volatile so gcc doesnt reorder on us
Blackfin arch: disable CONFIG_HW_RANDOM and CONFIG_DAB in defconfig files
Blackfin arch: update cache flush prototypes with argument names to make them less mysterious
Blackfin arch: move bfin_addr_dcachable() and friends into the cacheflush header where it belongs
Blackfin arch: use the new bfin_addr_dcachable() function
Blackfin arch: fix bug - build kernel failed at head.S when reprogram clock on all platforms
Blackfin arch: unify/cleanup cache code
Blackfin arch: update AD7879 platform resources in board file
Blackfin arch: Zero out bss region in L1/L2 memory.
Blackfin arch: add read/write IO accessor functions to Blackfin
Blackfin arch: fix bug - some serial header files set RTS to an input when they should all be outputs
- to be correct wrt to end ranges
- to be optimal with a one-instruction hardware loop
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
As policy->governor is already set to CPUFREQ_DEFAULT_GOVERNOR in the
(always built-in) cpufreq core, we do not need to set it in the drivers.
This fixes the sparc64 allmodconfig build failure.
Also, remove a totally useles setting of ->policy in cpufreq-pxa3xx.c.
Signed-off-by: Dominik Brodowski <linux@dominikbrodowski.net>
Acked-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
The kernel does not properly clear the EBIU Error Master (EBIU_ERRMST) Register
on BF548, which causes the kernel to panic.
We need to make sure that we clear the EBIU_ERRMST (necessary on BF54x)
Signed-off-by: Robin Getz <rgetz@blackfin.uclinux.org>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
a global _sys_trace will cause the assembler to fail, it should be fixed in toolchain side firstly.
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Apply ANOMALY_05000283 & ANOMALY_05000315
Workaround also to the EXCEPTION path.
Cover evt_ivhw also with ANOMALY_05000315
The Workaround needs to be prior to accesses (either read or write) to
any system MMR.
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
- remove cheesy read_iloc() function
- move invalidate_entire_icache function to lock.S
- export proper prototypes for functions in lock.S
- only build lock.S when BFIN_ICACHE_LOCK is enabled
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
- Disable all bits in SIC_IWR unless we are going into a real (DPMC)
power saving mode. Any Interrupt can wake the core form it's idle state.
- Remove deep sleep mode as it is not going to be used anywhere:
We support sleep, sleep deeper and hibernate.
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
- Skip single step if global interrupt disable bit is set.
- Extend bernds' patch r4673 to skip single step in any interrupt entry
that interrupts the code which is under single stepping. Bernds' patch
only allow user space single stepping.
Singed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Skip single step if event priority of current instruction is higher than
that of the first instruction, from which gdb starts single step.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Graf Yang