Random read/write errors are a bad thing - so don't let anyone
(including the test bench) run on something we know is bad.
Signed-off-by: Robin Getz <rgetz@blackfin.uclinux.org>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Run IFLUSH twice to avoid loading wrong instruction
after invalidating icache and following sequence is met.
1) The one instruction address is cached in the icache.
2) This instruction in SDRAM is changed.
3) IFLASH[P0] is executed only once in lackfin_icache_flush_range().
4) This instruction is executed again, but not the changed new one.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
IMHO the setting should depend on ANOMALY_05000305 which is about the
availability of the bit, not ANOMALY_05000265 which only describes the
SPORT sensitivity to noise (checked for BF561 only, though).
If that's not true for other BF variants, maybe the definition of
ANOMALY_05000265 for BF561 should be changed to '(1)' instead.
Signed-off-by: Enrik Berkhan <Enrik.Berkhan@ge.com>
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
- unable to single step over emuexcpt instruction
- gdbproxy goes into infinite loop when doing gdb does "next" over
"emuexcpt"
Don't decrement PC after software breakpoint.
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
bss_l2 section is garbage when the data in this section is used by
_bfin_relocate_l1_mem, so move the zero out function ahead.
Signed-off-by: Graf Yang <graf.yang@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
base SIC_IWR# programming on whether the MMR exists
rather than having to maintain another list of processors
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
On BF561 EBIU_SDGCTL bit 31 controls the SDRAM external data
path width, typically set 0 for a 32-bit bus width. On other
Blackfin derivatives this bit should be set by default.
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
[Mike Frysinger <vapier.adi@gmail.com>:
- handle bf531/bf532/bf534/bf536 variants in ipipe.h
- cleanup IPIPE logic for bfin_set_irq_handler()
- cleanup ipipe asm code a bit and add missing ENDPROC()
- simplify IPIPE code in trap_c
- unify some of the IPIPE code and fix style
- simplify DO_IRQ_L1 handling with ipipe code
- revert IRQ_SW_INT# addition from ipipe merge
- remove duplicate get_{c,s}clk() prototypes
]
Signed-off-by: Yi Li <yi.li@analog.com>
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
This is a mixture ofcMichael McTernan's patch and the existing cplb-mpu code.
We ditch the old cplb-nompu implementation, which is a good example of
why a good algorithm in a HLL is preferrable to a bad algorithm written in
assembly. Rather than try to construct a table of all posible CPLBs and
search it, we just create a (smaller) table of memory regions and
their attributes. Some of the data structures are now unified for both
the mpu and nompu cases. A lot of needless complexity in cplbinit.c is
removed.
Further optimizations:
* compile cplbmgr.c with a lot of -ffixed-reg options, and omit saving
these registers on the stack when entering a CPLB exception.
* lose cli/nop/nop/sti sequences for some workarounds - these don't
* make
sense in an exception context
Additional code unification should be possible after this.
[Mike Frysinger <vapier.adi@gmail.com>:
- convert CPP if statements to C if statements
- remove redundant statements
- use a do...while loop rather than a for loop to get slightly better
optimization and to avoid gcc "may be used uninitialized" warnings ...
we know that the [id]cplb_nr_bounds variables will never be 0, so this
is OK
- the no-mpu code was the last user of MAX_MEM_SIZE and with that rewritten,
we can punt it
- add some BUG_ON() checks to make sure we dont overflow the small
cplb_bounds array
- add i/d cplb entries for the bootrom because there is functions/data in
there we want to access
- we do not need a NULL trailing entry as any time we access the bounds
arrays, we use the nr_bounds variable
]
Signed-off-by: Michael McTernan <mmcternan@airvana.com>
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bernd Schmidt <bernds_cb1@t-online.de>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
It should be 'lose', not 'loose'.
Signed-off-by: Nick Andrew <nick@nick-andrew.net>
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
- remove duplicated code and headers
- add option allowing arbitrary SDRAM/DDR Timing parameters.
- mark automatically calculated timings as EXPERIMENTAL
- fix comment header block
Related to BUGs:
- kernel boot up fails with CONFIG_BFIN_KERNEL_CLOCK item on.
- kernel does not boot if re-program clocks
[ Mike Frysinger <vapier.adi@gmail.com>
- fix comment header
- mark do_sync static
- document the DMA shutdown
- simplify SIC_IWR handling
- fix ANOMALY_05000265 handling to work as intended ]
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
[Mike Frysinger <vapier.adi@gmail.com>:
- use KERN_NOTICE when using gpios as both irq and non
rather than KERN_ERR
- embedded newlines in printk() does not fly]
Signed-off-by: Graf Yang <graf.yang@analog.com>
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
rename cache_lock() to bfin_cache_lock() to avoid namespace collision
with common code
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
arch/blackfin/mach-common/entry.S:465: Error: pcrel too far
BFD_RELOC_BFIN_10
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
rename irq_flags to bfin_irq_flags to avoid namespace
collision with common code
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
rewrite blackfin_invalidate_entire_dcache() in C for easier management,
better optimization, and so we take all SSYNC anomalies into account
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Blackfin dual core BF561 processor can support SMP like features.
https://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:smp-like
In this patch, we provide SMP extend to Blackfin header files
and machine common code
Signed-off-by: Graf Yang <graf.yang@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
- Remove SSYNC()
- Use irq_to_gpio where applicable
- Remove gpio_edge_triggered bitfield, check irq_desc fields instead.
- Remove gpio_both_edge_triggeredb bitfield, check irq_desc fields
instead.
- Use BITMAP and bitops on gpio_enabled
- Preferably use 32-bit
- Looking at the disassembly this indeed saves quite a few instructions.
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
- remove SSYNC() left over from irq init split
- do not force SSYNC() when masking/unmasking IRQs in the SIC
as any order enforced by the hardware should already be enforced
by software
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
The whole story:
Before BF51x merged, all the MAX_BLACKFIN_GPIOS are integral multiple of GPIO_BANKSIZE (= 16).
But BF51x provides MAX_BLACKFIN_GPIOS = 40 which includes 3 banks and the 3rd bank has only 8
GPIO pins.
Therefore, gpio_bank() macros is correct when you try to find a GPIO in which bank (GPIO_35 is
in bank 2). But on BF51x gpio_bank(MAX_BLACKFIN_GPIOS) only gives out 2 banks instead of 3
banks for some static array initialization.
This patch add a new macros gpio_bank_n() and GPIO_BANK_NUM to do bank number caculating and
remain the gpio_bank() macros for positioning a gpio in which bank.
Signed-off-by: Bryan Wu <cooloney@kernel.org>
our kernel should be sane now, and we want to catch NULL bugs,
not ignore them
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
The original code defined _exception_stack but not alloc space for the exception
stack. In exception, this area is over written by exception stack. Common kernel
luckly boot up, but SMP kernel stuck.
Signed-off-by: Graf Yang <graf.yang@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
allow people to stick exception stack into L1 scratch
and make sure it gets placed into .bss sections rather than .data
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Make sure IFLUSH is not the last instruction in the hardware loop to avoid
infinite core stall.
The dcache/icache function that only gets used in writeback mode was putting
IFLUSH as the last instruction in the hardware loop ... we know from design
that this may often lead to inifite core stalling, so switch the FLUSH/IFLUSH
order.
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
The cache code I added flushes 1 line too little if the start address is
not aligned to the cache size. Cache align the start address so that when
we straddle cache aligns, we get the right count.
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/blackfin-2.6:
Blackfin arch: make sure cycles is marked as volatile so gcc doesnt reorder on us
Blackfin arch: disable CONFIG_HW_RANDOM and CONFIG_DAB in defconfig files
Blackfin arch: update cache flush prototypes with argument names to make them less mysterious
Blackfin arch: move bfin_addr_dcachable() and friends into the cacheflush header where it belongs
Blackfin arch: use the new bfin_addr_dcachable() function
Blackfin arch: fix bug - build kernel failed at head.S when reprogram clock on all platforms
Blackfin arch: unify/cleanup cache code
Blackfin arch: update AD7879 platform resources in board file
Blackfin arch: Zero out bss region in L1/L2 memory.
Blackfin arch: add read/write IO accessor functions to Blackfin
Blackfin arch: fix bug - some serial header files set RTS to an input when they should all be outputs
- to be correct wrt to end ranges
- to be optimal with a one-instruction hardware loop
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
As policy->governor is already set to CPUFREQ_DEFAULT_GOVERNOR in the
(always built-in) cpufreq core, we do not need to set it in the drivers.
This fixes the sparc64 allmodconfig build failure.
Also, remove a totally useles setting of ->policy in cpufreq-pxa3xx.c.
Signed-off-by: Dominik Brodowski <linux@dominikbrodowski.net>
Acked-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
The kernel does not properly clear the EBIU Error Master (EBIU_ERRMST) Register
on BF548, which causes the kernel to panic.
We need to make sure that we clear the EBIU_ERRMST (necessary on BF54x)
Signed-off-by: Robin Getz <rgetz@blackfin.uclinux.org>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
a global _sys_trace will cause the assembler to fail, it should be fixed in toolchain side firstly.
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Apply ANOMALY_05000283 & ANOMALY_05000315
Workaround also to the EXCEPTION path.
Cover evt_ivhw also with ANOMALY_05000315
The Workaround needs to be prior to accesses (either read or write) to
any system MMR.
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
- remove cheesy read_iloc() function
- move invalidate_entire_icache function to lock.S
- export proper prototypes for functions in lock.S
- only build lock.S when BFIN_ICACHE_LOCK is enabled
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
- Disable all bits in SIC_IWR unless we are going into a real (DPMC)
power saving mode. Any Interrupt can wake the core form it's idle state.
- Remove deep sleep mode as it is not going to be used anywhere:
We support sleep, sleep deeper and hibernate.
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
- Skip single step if global interrupt disable bit is set.
- Extend bernds' patch r4673 to skip single step in any interrupt entry
that interrupts the code which is under single stepping. Bernds' patch
only allow user space single stepping.
Singed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Skip single step if event priority of current instruction is higher than
that of the first instruction, from which gdb starts single step.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Enable: PM_SUSPEND_MEM -> Blackfin Hibernate to SDRAM
This feature requires a special bootloader (u-boot)
supporting return from hibernate.
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
use kernel command line mem and max_mem bootargs to limit
availabe memory instead.
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
When transferring to IRQ5 from an exception, save SYSCFG in memory across the
transfer and clear the trace bit.
When we get a single step exception, check whether we can safely clear the
trace bit in SYSCFG. We can (and should) clear it after the first instruction
of the interrupt handler; the first insn saves SYSCFG to the stack in all
handlers.
Signed-off-by: Bernd Schmidt <bernds_cb1@t-online.de>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
In the double fault handler, set up the PT_RETI slot so that
we print out the correct return address in the dumping code.
Signed-off-by: Bernd Schmidt <bernds_cb1@t-online.de>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Remove the circular buffering mechanism for exceptions. Instead, point RETX
at a safe location from which to fetch three NOPs.
This safe location is now in the fixed code area, and also used for certain
anomaly workarounds, to ensure that user space can find a valid ICPLB when
things are built with CONFIG_MPU.
Also, save I/DCPLB_FAULT_ADDRESS when lowering to level 5, since the hardware
reg is valid only at exception level.
Signed-off-by: Bernd Schmidt <bernds_cb1@t-online.de>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
The irq setup code no longer calls gpio request and free.
This patch also changes the default gpio_free behavior on Blackfin.
A freed GPIO keeps it's last state, and is not defaulted back to
an input. This is also what all other architectures do.
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
detect the memory available in the system on the fly by default
rather than forcing people to set this manually in the kconfig
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
There were a couple of problems with the way the trace buffer state
is saved/restored in assembly. The DEBUG_HWTRACE_SAVE/RESTORE macros
save a value to the stack, which is not immediately obvious; the CPLB
exception code needed changes to load the correct value of the stack
pointer. The other problem is that the SAVE/RESTORE macros weren't
pushing and popping the value downwards on the stack, but rather moving
it _upwards_, which is of course completely broken.
We also need to make sure there's a matching DEBUG_HWTRACE_RESTORE in
the error case of the CPLB handler.
Signed-off-by: Bernd Schmidt <bernds_cb1@t-online.de>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
- Buttons on the BF533-STAMP board are not inverted
- Fix spurious GPIO Interrupt caused during set irq_type for edge triggered interrupts
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
