picoxcell: add the DTS for pc3x2 and pc3x3 devices
This describes the basic hierarchy of picoxcell pc3x3 devices including clocks and bus interconnect. Some onchip devices are currently omitted as there haven't been bindings created for them. v2: - change timer compatible strings to be more soc specific - split vic node into 2 devices Signed-off-by: Jamie Iles <jamie@jamieiles.com>
This commit is contained in:
Jamie Iles
parent
af75655c06
commit
fee7565679
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/*
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* Copyright (C) 2011 Picochip, Jamie Iles
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/include/ "skeleton.dtsi"
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/ {
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model = "Picochip picoXcell PC3X2";
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compatible = "picochip,pc3x2";
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,1176jz-s";
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clock-frequency = <400000000>;
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reg = <0>;
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d-cache-line-size = <32>;
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d-cache-size = <32768>;
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i-cache-line-size = <32>;
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i-cache-size = <32768>;
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};
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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pclk: clock@0 {
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compatible = "fixed-clock";
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clock-outputs = "bus", "pclk";
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clock-frequency = <200000000>;
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ref-clock = <&ref_clk>, "ref";
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};
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};
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paxi {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x80000000 0x400000>;
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emac: gem@30000 {
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compatible = "cadence,gem";
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reg = <0x30000 0x10000>;
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interrupts = <31>;
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};
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dmac1: dmac@40000 {
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compatible = "snps,dw-dmac";
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reg = <0x40000 0x10000>;
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interrupts = <25>;
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};
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dmac2: dmac@50000 {
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compatible = "snps,dw-dmac";
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reg = <0x50000 0x10000>;
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interrupts = <26>;
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};
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vic0: interrupt-controller@60000 {
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compatible = "arm,pl192-vic";
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interrupt-controller;
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reg = <0x60000 0x1000>;
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#interrupt-cells = <1>;
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};
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vic1: interrupt-controller@64000 {
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compatible = "arm,pl192-vic";
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interrupt-controller;
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reg = <0x64000 0x1000>;
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#interrupt-cells = <1>;
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};
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fuse: picoxcell-fuse@80000 {
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compatible = "picoxcell,fuse-pc3x2";
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reg = <0x80000 0x10000>;
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};
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ssi: picoxcell-spi@90000 {
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compatible = "picoxcell,spi";
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reg = <0x90000 0x10000>;
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interrupt-parent = <&vic0>;
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interrupts = <10>;
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};
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ipsec: spacc@100000 {
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compatible = "picochip,spacc-ipsec";
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reg = <0x100000 0x10000>;
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interrupt-parent = <&vic0>;
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interrupts = <24>;
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ref-clock = <&pclk>, "ref";
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};
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srtp: spacc@140000 {
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compatible = "picochip,spacc-srtp";
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reg = <0x140000 0x10000>;
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interrupt-parent = <&vic0>;
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interrupts = <23>;
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};
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l2_engine: spacc@180000 {
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compatible = "picochip,spacc-l2";
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reg = <0x180000 0x10000>;
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interrupt-parent = <&vic0>;
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interrupts = <22>;
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ref-clock = <&pclk>, "ref";
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};
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apb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x200000 0x80000>;
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rtc0: rtc@00000 {
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compatible = "picochip,pc3x2-rtc";
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clock-freq = <200000000>;
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reg = <0x00000 0xf>;
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interrupt-parent = <&vic1>;
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interrupts = <8>;
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};
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timer0: timer@10000 {
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compatible = "picochip,pc3x2-timer";
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interrupt-parent = <&vic0>;
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interrupts = <4>;
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clock-freq = <200000000>;
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reg = <0x10000 0x14>;
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};
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timer1: timer@10014 {
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compatible = "picochip,pc3x2-timer";
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interrupt-parent = <&vic0>;
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interrupts = <5>;
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clock-freq = <200000000>;
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reg = <0x10014 0x14>;
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};
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timer2: timer@10028 {
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compatible = "picochip,pc3x2-timer";
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interrupt-parent = <&vic0>;
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interrupts = <6>;
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clock-freq = <200000000>;
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reg = <0x10028 0x14>;
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};
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timer3: timer@1003c {
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compatible = "picochip,pc3x2-timer";
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interrupt-parent = <&vic0>;
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interrupts = <7>;
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clock-freq = <200000000>;
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reg = <0x1003c 0x14>;
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};
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gpio: gpio@20000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x20000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg-io-width = <4>;
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banka: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-bank";
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gpio-controller;
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#gpio-cells = <2>;
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gpio-generic,nr-gpio = <8>;
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regoffset-dat = <0x50>;
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regoffset-set = <0x00>;
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regoffset-dirout = <0x04>;
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};
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bankb: gpio-controller@1 {
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compatible = "snps,dw-apb-gpio-bank";
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gpio-controller;
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#gpio-cells = <2>;
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gpio-generic,nr-gpio = <8>;
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regoffset-dat = <0x54>;
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regoffset-set = <0x0c>;
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regoffset-dirout = <0x10>;
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};
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};
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uart0: uart@30000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x30000 0x1000>;
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interrupt-parent = <&vic1>;
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interrupts = <10>;
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clock-frequency = <3686400>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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uart1: uart@40000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x40000 0x1000>;
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interrupt-parent = <&vic1>;
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interrupts = <9>;
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clock-frequency = <3686400>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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wdog: watchdog@50000 {
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compatible = "snps,dw-apb-wdg";
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reg = <0x50000 0x10000>;
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interrupt-parent = <&vic0>;
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interrupts = <11>;
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bus-clock = <&pclk>, "bus";
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};
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};
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};
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rwid-axi {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges;
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ebi@50000000 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0 0x40000000 0x08000000
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1 0 0x48000000 0x08000000
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2 0 0x50000000 0x08000000
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3 0 0x58000000 0x08000000>;
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};
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axi2pico@c0000000 {
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compatible = "picochip,axi2pico-pc3x2";
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reg = <0xc0000000 0x10000>;
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interrupts = <13 14 15 16 17 18 19 20 21>;
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};
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};
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};
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@ -0,0 +1,365 @@
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/*
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* Copyright (C) 2011 Picochip, Jamie Iles
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/include/ "skeleton.dtsi"
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/ {
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model = "Picochip picoXcell PC3X3";
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compatible = "picochip,pc3x3";
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,1176jz-s";
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cpu-clock = <&arm_clk>, "cpu";
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reg = <0>;
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d-cache-line-size = <32>;
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d-cache-size = <32768>;
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i-cache-line-size = <32>;
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i-cache-size = <32768>;
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};
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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clkgate: clkgate@800a0048 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x800a0048 4>;
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compatible = "picochip,pc3x3-clk-gate";
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tzprot_clk: clock@0 {
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compatible = "picochip,pc3x3-gated-clk";
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clock-outputs = "bus";
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picochip,clk-disable-bit = <0>;
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clock-frequency = <200000000>;
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ref-clock = <&ref_clk>, "ref";
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};
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spi_clk: clock@1 {
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compatible = "picochip,pc3x3-gated-clk";
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clock-outputs = "bus";
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picochip,clk-disable-bit = <1>;
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clock-frequency = <200000000>;
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ref-clock = <&ref_clk>, "ref";
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};
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dmac0_clk: clock@2 {
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compatible = "picochip,pc3x3-gated-clk";
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clock-outputs = "bus";
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picochip,clk-disable-bit = <2>;
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clock-frequency = <200000000>;
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ref-clock = <&ref_clk>, "ref";
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};
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dmac1_clk: clock@3 {
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compatible = "picochip,pc3x3-gated-clk";
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clock-outputs = "bus";
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picochip,clk-disable-bit = <3>;
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clock-frequency = <200000000>;
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ref-clock = <&ref_clk>, "ref";
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};
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ebi_clk: clock@4 {
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compatible = "picochip,pc3x3-gated-clk";
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clock-outputs = "bus";
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picochip,clk-disable-bit = <4>;
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clock-frequency = <200000000>;
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ref-clock = <&ref_clk>, "ref";
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};
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ipsec_clk: clock@5 {
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compatible = "picochip,pc3x3-gated-clk";
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clock-outputs = "bus";
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picochip,clk-disable-bit = <5>;
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clock-frequency = <200000000>;
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ref-clock = <&ref_clk>, "ref";
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};
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l2_clk: clock@6 {
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compatible = "picochip,pc3x3-gated-clk";
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clock-outputs = "bus";
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picochip,clk-disable-bit = <6>;
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clock-frequency = <200000000>;
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ref-clock = <&ref_clk>, "ref";
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};
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trng_clk: clock@7 {
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compatible = "picochip,pc3x3-gated-clk";
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clock-outputs = "bus";
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picochip,clk-disable-bit = <7>;
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clock-frequency = <200000000>;
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ref-clock = <&ref_clk>, "ref";
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};
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fuse_clk: clock@8 {
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compatible = "picochip,pc3x3-gated-clk";
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clock-outputs = "bus";
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picochip,clk-disable-bit = <8>;
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clock-frequency = <200000000>;
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ref-clock = <&ref_clk>, "ref";
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};
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otp_clk: clock@9 {
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compatible = "picochip,pc3x3-gated-clk";
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clock-outputs = "bus";
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picochip,clk-disable-bit = <9>;
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clock-frequency = <200000000>;
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ref-clock = <&ref_clk>, "ref";
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};
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};
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arm_clk: clock@11 {
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compatible = "picochip,pc3x3-pll";
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reg = <0x800a0050 0x8>;
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picochip,min-freq = <140000000>;
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picochip,max-freq = <700000000>;
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ref-clock = <&ref_clk>, "ref";
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clock-outputs = "cpu";
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};
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pclk: clock@12 {
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compatible = "fixed-clock";
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clock-outputs = "bus", "pclk";
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clock-frequency = <200000000>;
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ref-clock = <&ref_clk>, "ref";
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};
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};
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paxi {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x80000000 0x400000>;
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emac: gem@30000 {
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compatible = "cadence,gem";
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reg = <0x30000 0x10000>;
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interrupt-parent = <&vic0>;
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interrupts = <31>;
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};
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dmac1: dmac@40000 {
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compatible = "snps,dw-dmac";
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reg = <0x40000 0x10000>;
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interrupt-parent = <&vic0>;
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interrupts = <25>;
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};
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dmac2: dmac@50000 {
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compatible = "snps,dw-dmac";
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reg = <0x50000 0x10000>;
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interrupt-parent = <&vic0>;
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interrupts = <26>;
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};
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vic0: interrupt-controller@60000 {
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compatible = "arm,pl192-vic";
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interrupt-controller;
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reg = <0x60000 0x1000>;
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#interrupt-cells = <1>;
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};
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vic1: interrupt-controller@64000 {
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compatible = "arm,pl192-vic";
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interrupt-controller;
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reg = <0x64000 0x1000>;
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#interrupt-cells = <1>;
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};
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fuse: picoxcell-fuse@80000 {
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compatible = "picoxcell,fuse-pc3x3";
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reg = <0x80000 0x10000>;
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};
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ssi: picoxcell-spi@90000 {
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compatible = "picoxcell,spi";
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reg = <0x90000 0x10000>;
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interrupt-parent = <&vic0>;
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interrupts = <10>;
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};
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ipsec: spacc@100000 {
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compatible = "picochip,spacc-ipsec";
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reg = <0x100000 0x10000>;
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interrupt-parent = <&vic0>;
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interrupts = <24>;
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ref-clock = <&ipsec_clk>, "ref";
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};
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srtp: spacc@140000 {
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compatible = "picochip,spacc-srtp";
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reg = <0x140000 0x10000>;
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interrupt-parent = <&vic0>;
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interrupts = <23>;
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};
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l2_engine: spacc@180000 {
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compatible = "picochip,spacc-l2";
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reg = <0x180000 0x10000>;
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interrupt-parent = <&vic0>;
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interrupts = <22>;
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ref-clock = <&l2_clk>, "ref";
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};
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apb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x200000 0x80000>;
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rtc0: rtc@00000 {
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compatible = "picochip,pc3x2-rtc";
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clock-freq = <200000000>;
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reg = <0x00000 0xf>;
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interrupt-parent = <&vic0>;
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interrupts = <8>;
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};
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timer0: timer@10000 {
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compatible = "picochip,pc3x2-timer";
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interrupt-parent = <&vic0>;
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interrupts = <4>;
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clock-freq = <200000000>;
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reg = <0x10000 0x14>;
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};
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timer1: timer@10014 {
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compatible = "picochip,pc3x2-timer";
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interrupt-parent = <&vic0>;
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interrupts = <5>;
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clock-freq = <200000000>;
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reg = <0x10014 0x14>;
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};
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gpio: gpio@20000 {
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compatible = "snps,dw-apb-gpio";
|
||||
reg = <0x20000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-io-width = <4>;
|
||||
|
||||
banka: gpio-controller@0 {
|
||||
compatible = "snps,dw-apb-gpio-bank";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-generic,nr-gpio = <8>;
|
||||
|
||||
regoffset-dat = <0x50>;
|
||||
regoffset-set = <0x00>;
|
||||
regoffset-dirout = <0x04>;
|
||||
};
|
||||
|
||||
bankb: gpio-controller@1 {
|
||||
compatible = "snps,dw-apb-gpio-bank";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-generic,nr-gpio = <16>;
|
||||
|
||||
regoffset-dat = <0x54>;
|
||||
regoffset-set = <0x0c>;
|
||||
regoffset-dirout = <0x10>;
|
||||
};
|
||||
|
||||
bankd: gpio-controller@2 {
|
||||
compatible = "snps,dw-apb-gpio-bank";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-generic,nr-gpio = <30>;
|
||||
|
||||
regoffset-dat = <0x5c>;
|
||||
regoffset-set = <0x24>;
|
||||
regoffset-dirout = <0x28>;
|
||||
};
|
||||
};
|
||||
|
||||
uart0: uart@30000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x30000 0x1000>;
|
||||
interrupt-parent = <&vic1>;
|
||||
interrupts = <10>;
|
||||
clock-frequency = <3686400>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
};
|
||||
|
||||
uart1: uart@40000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x40000 0x1000>;
|
||||
interrupt-parent = <&vic1>;
|
||||
interrupts = <9>;
|
||||
clock-frequency = <3686400>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
};
|
||||
|
||||
wdog: watchdog@50000 {
|
||||
compatible = "snps,dw-apb-wdg";
|
||||
reg = <0x50000 0x10000>;
|
||||
interrupt-parent = <&vic0>;
|
||||
interrupts = <11>;
|
||||
bus-clock = <&pclk>, "bus";
|
||||
};
|
||||
|
||||
timer2: timer@60000 {
|
||||
compatible = "picochip,pc3x2-timer";
|
||||
interrupt-parent = <&vic0>;
|
||||
interrupts = <6>;
|
||||
clock-freq = <200000000>;
|
||||
reg = <0x60000 0x14>;
|
||||
};
|
||||
|
||||
timer3: timer@60014 {
|
||||
compatible = "picochip,pc3x2-timer";
|
||||
interrupt-parent = <&vic0>;
|
||||
interrupts = <7>;
|
||||
clock-freq = <200000000>;
|
||||
reg = <0x60014 0x14>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
rwid-axi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
|
||||
ebi@50000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0x40000000 0x08000000
|
||||
1 0 0x48000000 0x08000000
|
||||
2 0 0x50000000 0x08000000
|
||||
3 0 0x58000000 0x08000000>;
|
||||
};
|
||||
|
||||
axi2pico@c0000000 {
|
||||
compatible = "picochip,axi2pico-pc3x3";
|
||||
reg = <0xc0000000 0x10000>;
|
||||
interrupt-parent = <&vic0>;
|
||||
interrupts = <13 14 15 16 17 18 19 20 21>;
|
||||
};
|
||||
|
||||
otp@ffff8000 {
|
||||
compatible = "picochip,otp-pc3x3";
|
||||
reg = <0xffff8000 0x8000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
Reference in New Issue