sh: prepare the DMA driver for slave functionality
Slave DMA functionality uses scatter-gather arrays for data transfers, whereas memcpy just uses a single data buffer. This patch converts the current memcpy implementation in shdma.c to use scatter-gather, making it just a special case with one SG-element. This allows us to isolate descriptor list manipulations and locking into one function, thus reducing error chances. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Acked-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Guennadi Liakhovetski
Paul Mundt
parent
6339204ecc
commit
fc4618575f
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@ -53,12 +53,12 @@ static void sh_dmae_chan_ld_cleanup(struct sh_dmae_chan *sh_chan, bool all);
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#define SH_DMAC_CHAN_BASE(id) (dma_base_addr[id])
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static void sh_dmae_writel(struct sh_dmae_chan *sh_dc, u32 data, u32 reg)
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{
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ctrl_outl(data, (SH_DMAC_CHAN_BASE(sh_dc->id) + reg));
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ctrl_outl(data, SH_DMAC_CHAN_BASE(sh_dc->id) + reg);
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}
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static u32 sh_dmae_readl(struct sh_dmae_chan *sh_dc, u32 reg)
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{
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return ctrl_inl((SH_DMAC_CHAN_BASE(sh_dc->id) + reg));
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return ctrl_inl(SH_DMAC_CHAN_BASE(sh_dc->id) + reg);
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}
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static void dmae_init(struct sh_dmae_chan *sh_chan)
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@ -95,14 +95,14 @@ static int sh_dmae_rst(int id)
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return 0;
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}
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static int dmae_is_busy(struct sh_dmae_chan *sh_chan)
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static bool dmae_is_busy(struct sh_dmae_chan *sh_chan)
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{
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u32 chcr = sh_dmae_readl(sh_chan, CHCR);
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if (chcr & CHCR_DE) {
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if (!(chcr & CHCR_TE))
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return -EBUSY; /* working */
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}
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return 0; /* waiting */
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if ((chcr & (CHCR_DE | CHCR_TE)) == CHCR_DE)
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return true; /* working */
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return false; /* waiting */
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}
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static inline unsigned int calc_xmit_shift(struct sh_dmae_chan *sh_chan)
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@ -136,10 +136,9 @@ static void dmae_halt(struct sh_dmae_chan *sh_chan)
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static int dmae_set_chcr(struct sh_dmae_chan *sh_chan, u32 val)
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{
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int ret = dmae_is_busy(sh_chan);
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/* When DMA was working, can not set data to CHCR */
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if (ret)
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return ret;
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if (dmae_is_busy(sh_chan))
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return -EBUSY;
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sh_dmae_writel(sh_chan, val, CHCR);
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return 0;
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@ -153,9 +152,9 @@ static int dmae_set_dmars(struct sh_dmae_chan *sh_chan, u16 val)
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{
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u32 addr;
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int shift = 0;
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int ret = dmae_is_busy(sh_chan);
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if (ret)
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return ret;
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if (dmae_is_busy(sh_chan))
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return -EBUSY;
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if (sh_chan->id & DMARS_CHAN_MSK)
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shift = DMARS_SHIFT;
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@ -301,23 +300,95 @@ static void sh_dmae_free_chan_resources(struct dma_chan *chan)
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kfree(desc);
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}
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static struct dma_async_tx_descriptor *sh_dmae_prep_memcpy(
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struct dma_chan *chan, dma_addr_t dma_dest, dma_addr_t dma_src,
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size_t len, unsigned long flags)
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/*
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* sh_dmae_add_desc - get, set up and return one transfer descriptor
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* @sh_chan: DMA channel
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* @flags: DMA transfer flags
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* @dest: destination DMA address, incremented when direction equals
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* DMA_FROM_DEVICE or DMA_BIDIRECTIONAL
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* @src: source DMA address, incremented when direction equals
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* DMA_TO_DEVICE or DMA_BIDIRECTIONAL
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* @len: DMA transfer length
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* @first: if NULL, set to the current descriptor and cookie set to -EBUSY
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* @direction: needed for slave DMA to decide which address to keep constant,
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* equals DMA_BIDIRECTIONAL for MEMCPY
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* Returns 0 or an error
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* Locks: called with desc_lock held
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*/
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static struct sh_desc *sh_dmae_add_desc(struct sh_dmae_chan *sh_chan,
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unsigned long flags, dma_addr_t *dest, dma_addr_t *src, size_t *len,
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struct sh_desc **first, enum dma_data_direction direction)
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{
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struct sh_dmae_chan *sh_chan;
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struct sh_desc *first = NULL, *prev = NULL, *new;
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struct sh_desc *new;
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size_t copy_size;
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if (!*len)
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return NULL;
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/* Allocate the link descriptor from the free list */
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new = sh_dmae_get_desc(sh_chan);
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if (!new) {
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dev_err(sh_chan->dev, "No free link descriptor available\n");
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return NULL;
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}
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copy_size = min(*len, (size_t)SH_DMA_TCR_MAX + 1);
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new->hw.sar = *src;
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new->hw.dar = *dest;
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new->hw.tcr = copy_size;
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if (!*first) {
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/* First desc */
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new->async_tx.cookie = -EBUSY;
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*first = new;
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} else {
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/* Other desc - invisible to the user */
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new->async_tx.cookie = -EINVAL;
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}
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dev_dbg(sh_chan->dev, "chaining (%u/%u)@%x -> %x with %p, cookie %d\n",
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copy_size, *len, *src, *dest, &new->async_tx,
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new->async_tx.cookie);
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new->mark = DESC_PREPARED;
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new->async_tx.flags = flags;
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*len -= copy_size;
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if (direction == DMA_BIDIRECTIONAL || direction == DMA_TO_DEVICE)
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*src += copy_size;
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if (direction == DMA_BIDIRECTIONAL || direction == DMA_FROM_DEVICE)
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*dest += copy_size;
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return new;
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}
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/*
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* sh_dmae_prep_sg - prepare transfer descriptors from an SG list
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*
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* Common routine for public (MEMCPY) and slave DMA. The MEMCPY case is also
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* converted to scatter-gather to guarantee consistent locking and a correct
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* list manipulation. For slave DMA direction carries the usual meaning, and,
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* logically, the SG list is RAM and the addr variable contains slave address,
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* e.g., the FIFO I/O register. For MEMCPY direction equals DMA_BIDIRECTIONAL
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* and the SG list contains only one element and points at the source buffer.
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*/
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static struct dma_async_tx_descriptor *sh_dmae_prep_sg(struct sh_dmae_chan *sh_chan,
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struct scatterlist *sgl, unsigned int sg_len, dma_addr_t *addr,
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enum dma_data_direction direction, unsigned long flags)
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{
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struct scatterlist *sg;
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struct sh_desc *first = NULL, *new = NULL /* compiler... */;
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LIST_HEAD(tx_list);
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int chunks = (len + SH_DMA_TCR_MAX) / (SH_DMA_TCR_MAX + 1);
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int chunks = 0;
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int i;
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if (!chan)
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if (!sg_len)
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return NULL;
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if (!len)
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return NULL;
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sh_chan = to_sh_chan(chan);
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for_each_sg(sgl, sg, sg_len, i)
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chunks += (sg_dma_len(sg) + SH_DMA_TCR_MAX) /
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(SH_DMA_TCR_MAX + 1);
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/* Have to lock the whole loop to protect against concurrent release */
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spin_lock_bh(&sh_chan->desc_lock);
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@ -333,49 +404,32 @@ static struct dma_async_tx_descriptor *sh_dmae_prep_memcpy(
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* only during this function, then they are immediately spliced
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* back onto the free list in form of a chain
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*/
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do {
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/* Allocate the link descriptor from the free list */
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new = sh_dmae_get_desc(sh_chan);
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if (!new) {
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dev_err(sh_chan->dev,
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"No free memory for link descriptor\n");
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list_for_each_entry(new, &tx_list, node)
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new->mark = DESC_IDLE;
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list_splice(&tx_list, &sh_chan->ld_free);
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spin_unlock_bh(&sh_chan->desc_lock);
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return NULL;
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}
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for_each_sg(sgl, sg, sg_len, i) {
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dma_addr_t sg_addr = sg_dma_address(sg);
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size_t len = sg_dma_len(sg);
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copy_size = min(len, (size_t)SH_DMA_TCR_MAX + 1);
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if (!len)
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goto err_get_desc;
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new->hw.sar = dma_src;
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new->hw.dar = dma_dest;
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new->hw.tcr = copy_size;
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if (!first) {
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/* First desc */
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new->async_tx.cookie = -EBUSY;
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first = new;
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} else {
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/* Other desc - invisible to the user */
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new->async_tx.cookie = -EINVAL;
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}
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do {
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dev_dbg(sh_chan->dev, "Add SG #%d@%p[%d], dma %llx\n",
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i, sg, len, (unsigned long long)sg_addr);
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dev_dbg(sh_chan->dev,
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"chaining %u of %u with %p, dst %x, cookie %d\n",
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copy_size, len, &new->async_tx, dma_dest,
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new->async_tx.cookie);
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if (direction == DMA_FROM_DEVICE)
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new = sh_dmae_add_desc(sh_chan, flags,
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&sg_addr, addr, &len, &first,
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direction);
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else
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new = sh_dmae_add_desc(sh_chan, flags,
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addr, &sg_addr, &len, &first,
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direction);
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if (!new)
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goto err_get_desc;
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new->mark = DESC_PREPARED;
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new->async_tx.flags = flags;
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new->chunks = chunks--;
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prev = new;
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len -= copy_size;
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dma_src += copy_size;
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dma_dest += copy_size;
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/* Insert the link descriptor to the LD ring */
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list_add_tail(&new->node, &tx_list);
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} while (len);
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new->chunks = chunks--;
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list_add_tail(&new->node, &tx_list);
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} while (len);
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}
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if (new != first)
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new->async_tx.cookie = -ENOSPC;
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@ -386,6 +440,37 @@ static struct dma_async_tx_descriptor *sh_dmae_prep_memcpy(
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spin_unlock_bh(&sh_chan->desc_lock);
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return &first->async_tx;
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err_get_desc:
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list_for_each_entry(new, &tx_list, node)
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new->mark = DESC_IDLE;
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list_splice(&tx_list, &sh_chan->ld_free);
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spin_unlock_bh(&sh_chan->desc_lock);
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return NULL;
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}
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static struct dma_async_tx_descriptor *sh_dmae_prep_memcpy(
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struct dma_chan *chan, dma_addr_t dma_dest, dma_addr_t dma_src,
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size_t len, unsigned long flags)
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{
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struct sh_dmae_chan *sh_chan;
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struct scatterlist sg;
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if (!chan || !len)
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return NULL;
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sh_chan = to_sh_chan(chan);
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sg_init_table(&sg, 1);
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sg_set_page(&sg, pfn_to_page(PFN_DOWN(dma_src)), len,
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offset_in_page(dma_src));
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sg_dma_address(&sg) = dma_src;
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sg_dma_len(&sg) = len;
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return sh_dmae_prep_sg(sh_chan, &sg, 1, &dma_dest, DMA_BIDIRECTIONAL,
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flags);
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}
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static dma_async_tx_callback __ld_cleanup(struct sh_dmae_chan *sh_chan, bool all)
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@ -559,7 +644,7 @@ static irqreturn_t sh_dmae_err(int irq, void *data)
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/* IRQ Multi */
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if (shdev->pdata.mode & SHDMA_MIX_IRQ) {
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int cnt = 0;
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int __maybe_unused cnt = 0;
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switch (irq) {
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#if defined(DMTE6_IRQ) && defined(DMAE1_IRQ)
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case DMTE6_IRQ:
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