Merge master.kernel.org:/pub/scm/linux/kernel/git/lethal/sh-2.6
* master.kernel.org:/pub/scm/linux/kernel/git/lethal/sh-2.6: serial: Fix sh-sci break interrupt/sysrq handling. sh: Fix bogus regs pointer in do_IRQ(). sh: Fix SH-3 cache entry_mask and way_size calculation. sh: Convert struct ioctls to static defines. sh: Define missing __NR_readahead. sh: Fix PCI BAR address-space wraparound.
This commit is contained in:
Linus Torvalds
commit
fbeb1f1922
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@ -214,6 +214,12 @@ retry:
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continue;
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}
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if (bar_value < *lower_limit || (bar_value + bar_size) >= *upper_limit) {
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DBG(" unavailable -- skipping, value %x size %x\n",
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bar_value, bar_size);
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continue;
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}
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#ifdef CONFIG_PCI_AUTO_UPDATE_RESOURCES
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/* Write it out and update our limit */
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early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
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@ -3,7 +3,7 @@
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*
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* CPU init code
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*
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* Copyright (C) 2002 - 2006 Paul Mundt
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* Copyright (C) 2002 - 2007 Paul Mundt
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* Copyright (C) 2003 Richard Curnow
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*
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* This file is subject to the terms and conditions of the GNU General Public
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@ -48,8 +48,19 @@ static void __init cache_init(void)
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{
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unsigned long ccr, flags;
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if (current_cpu_data.type == CPU_SH_NONE)
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panic("Unknown CPU");
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/* First setup the rest of the I-cache info */
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current_cpu_data.icache.entry_mask = current_cpu_data.icache.way_incr -
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current_cpu_data.icache.linesz;
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current_cpu_data.icache.way_size = current_cpu_data.icache.sets *
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current_cpu_data.icache.linesz;
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/* And the D-cache too */
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current_cpu_data.dcache.entry_mask = current_cpu_data.dcache.way_incr -
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current_cpu_data.dcache.linesz;
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current_cpu_data.dcache.way_size = current_cpu_data.dcache.sets *
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current_cpu_data.dcache.linesz;
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jump_to_P2();
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ccr = ctrl_inl(CCR);
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@ -200,6 +211,9 @@ asmlinkage void __init sh_cpu_init(void)
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/* First, probe the CPU */
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detect_cpu_and_cache_system();
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if (current_cpu_data.type == CPU_SH_NONE)
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panic("Unknown CPU");
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/* Init the cache */
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cache_init();
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@ -165,6 +165,7 @@ ENTRY(exception_handler)
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interrupt_entry:
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mov r9,r4
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mov r15,r5
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mov.l 6f,r9
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mov.l 7f,r8
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jmp @r8
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@ -514,13 +514,16 @@ skip_save:
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interrupt_exception:
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mov.l 1f, r9
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mov.l 2f, r4
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mov.l @r4, r4
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jmp @r9
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nop
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mov r15, r5
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rts
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nop
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.align 2
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1: .long do_IRQ
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2: .long INTEVT
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.align 2
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ENTRY(exception_none)
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@ -195,13 +195,6 @@ int __init detect_cpu_and_cache_system(void)
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}
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/* Setup the rest of the I-cache info */
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current_cpu_data.icache.entry_mask = current_cpu_data.icache.way_incr -
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current_cpu_data.icache.linesz;
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current_cpu_data.icache.way_size = current_cpu_data.icache.sets *
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current_cpu_data.icache.linesz;
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/* And the rest of the D-cache */
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if (current_cpu_data.dcache.ways > 1) {
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size = sizes[(cvr >> 16) & 0xf];
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@ -209,12 +202,6 @@ int __init detect_cpu_and_cache_system(void)
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current_cpu_data.dcache.sets = (size >> 6);
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}
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current_cpu_data.dcache.entry_mask = current_cpu_data.dcache.way_incr -
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current_cpu_data.dcache.linesz;
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current_cpu_data.dcache.way_size = current_cpu_data.dcache.sets *
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current_cpu_data.dcache.linesz;
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/*
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* Setup the L2 cache desc
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*
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@ -11,7 +11,6 @@
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#include <linux/module.h>
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#include <linux/kernel_stat.h>
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#include <linux/seq_file.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <asm/processor.h>
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#include <asm/uaccess.h>
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@ -82,13 +81,9 @@ static union irq_ctx *hardirq_ctx[NR_CPUS] __read_mostly;
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static union irq_ctx *softirq_ctx[NR_CPUS] __read_mostly;
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#endif
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asmlinkage int do_IRQ(unsigned long r4, unsigned long r5,
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unsigned long r6, unsigned long r7,
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struct pt_regs __regs)
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asmlinkage int do_IRQ(unsigned int irq, struct pt_regs *regs)
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{
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struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
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struct pt_regs *old_regs = set_irq_regs(regs);
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int irq;
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#ifdef CONFIG_4KSTACKS
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union irq_ctx *curctx, *irqctx;
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#endif
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@ -111,13 +106,7 @@ asmlinkage int do_IRQ(unsigned long r4, unsigned long r5,
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}
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#endif
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#ifdef CONFIG_CPU_HAS_INTEVT
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irq = evt2irq(ctrl_inl(INTEVT));
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#else
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irq = r4;
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#endif
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irq = irq_demux(irq);
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irq = irq_demux(evt2irq(irq));
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#ifdef CONFIG_4KSTACKS
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curctx = (union irq_ctx *)current_thread_info();
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@ -17,6 +17,9 @@
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
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#define SUPPORT_SYSRQ
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#endif
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#undef DEBUG
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@ -49,11 +52,6 @@
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#endif
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#include <asm/sci.h>
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#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
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#define SUPPORT_SYSRQ
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#endif
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#include "sh-sci.h"
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struct sci_port {
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@ -645,6 +643,9 @@ static inline int sci_handle_breaks(struct uart_port *port)
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struct tty_struct *tty = port->info->tty;
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struct sci_port *s = &sci_ports[port->line];
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if (uart_handle_break(port))
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return 0;
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if (!s->break_flag && status & SCxSR_BRK(port)) {
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#if defined(CONFIG_CPU_SH3)
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/* Debounce break */
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@ -16,17 +16,17 @@
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#define TCSETSW 0x5403
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#define TCSETSF 0x5404
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#define TCGETA _IOR('t', 23, struct termio)
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#define TCSETA _IOW('t', 24, struct termio)
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#define TCSETAW _IOW('t', 25, struct termio)
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#define TCSETAF _IOW('t', 28, struct termio)
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#define TCGETA 0x80127417 /* _IOR('t', 23, struct termio) */
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#define TCSETA 0x40127418 /* _IOW('t', 24, struct termio) */
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#define TCSETAW 0x40127419 /* _IOW('t', 25, struct termio) */
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#define TCSETAF 0x4012741C /* _IOW('t', 28, struct termio) */
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#define TCSBRK _IO('t', 29)
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#define TCXONC _IO('t', 30)
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#define TCFLSH _IO('t', 31)
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#define TIOCSWINSZ _IOW('t', 103, struct winsize)
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#define TIOCGWINSZ _IOR('t', 104, struct winsize)
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#define TIOCSWINSZ 0x40087467 /* _IOW('t', 103, struct winsize) */
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#define TIOCGWINSZ 0x80087468 /* _IOR('t', 104, struct winsize) */
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#define TIOCSTART _IO('t', 110) /* start output, like ^Q */
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#define TIOCSTOP _IO('t', 111) /* stop output, like ^S */
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#define TIOCOUTQ _IOR('t', 115, int) /* output queue size */
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@ -59,8 +59,8 @@
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#define TIOCSSOFTCAR _IOW('T', 26, unsigned int) /* 0x541A */
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#define TIOCLINUX _IOW('T', 28, char) /* 0x541C */
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#define TIOCCONS _IO('T', 29) /* 0x541D */
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#define TIOCGSERIAL _IOR('T', 30, struct serial_struct) /* 0x541E */
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#define TIOCSSERIAL _IOW('T', 31, struct serial_struct) /* 0x541F */
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#define TIOCGSERIAL 0x803C541E /* _IOR('T', 30, struct serial_struct) 0x541E */
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#define TIOCSSERIAL 0x403C541F /* _IOW('T', 31, struct serial_struct) 0x541F */
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#define TIOCPKT _IOW('T', 32, int) /* 0x5420 */
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# define TIOCPKT_DATA 0
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# define TIOCPKT_FLUSHREAD 1
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@ -86,12 +86,12 @@
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#define TIOCSERSWILD _IOW('T', 85, int) /* 0x5455 */
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#define TIOCGLCKTRMIOS 0x5456
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#define TIOCSLCKTRMIOS 0x5457
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#define TIOCSERGSTRUCT _IOR('T', 88, struct async_struct) /* 0x5458 */ /* For debugging only */
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#define TIOCSERGSTRUCT 0x80d85458 /* _IOR('T', 88, struct async_struct) 0x5458 */ /* For debugging only */
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#define TIOCSERGETLSR _IOR('T', 89, unsigned int) /* 0x5459 */ /* Get line status register */
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/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
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# define TIOCSER_TEMT 0x01 /* Transmitter physically empty */
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#define TIOCSERGETMULTI _IOR('T', 90, struct serial_multiport_struct) /* 0x545A */ /* Get multiport config */
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#define TIOCSERSETMULTI _IOW('T', 91, struct serial_multiport_struct) /* 0x545B */ /* Set multiport config */
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#define TIOCSERGETMULTI 0x80A8545A /* _IOR('T', 90, struct serial_multiport_struct) 0x545A */ /* Get multiport config */
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#define TIOCSERSETMULTI 0x40A8545B /* _IOW('T', 91, struct serial_multiport_struct) 0x545B */ /* Set multiport config */
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#define TIOCMIWAIT _IO('T', 92) /* 0x545C */ /* wait for a change on serial input line(s) */
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#define TIOCGICOUNT 0x545D /* read serial port inline interrupt counts */
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@ -94,8 +94,13 @@
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/*
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* Convert back and forth between INTEVT and IRQ values.
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*/
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#ifdef CONFIG_CPU_HAS_INTEVT
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#define evt2irq(evt) (((evt) >> 5) - 16)
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#define irq2evt(irq) (((irq) + 16) << 5)
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#else
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#define evt2irq(evt) (evt)
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#define irq2evt(irq) (irq)
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#endif
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/*
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* Simple Mask Register Support
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@ -233,6 +233,7 @@
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#define __NR_fcntl64 221
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/* 223 is unused */
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#define __NR_gettid 224
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#define __NR_readahead 225
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#define __NR_setxattr 226
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#define __NR_lsetxattr 227
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#define __NR_fsetxattr 228
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