x86: coding style fixes to arch/x86/kernel/cpu/amd.c
Before: total: 42 errors, 26 warnings, 350 lines checked After: total: 0 errors, 26 warnings, 352 lines checked No code changed: arch/x86/kernel/cpu/amd.o: text data bss dec hex filename 1936 328 0 2264 8d8 amd.o.before 1936 328 0 2264 8d8 amd.o.after md5: 873430a88faaf31bb4bbfe3a2a691e45 amd.o.before.asm 873430a88faaf31bb4bbfe3a2a691e45 amd.o.after.asm Signed-off-by: Paolo Ciarrocchi <paolo.ciarrocchi@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Paolo Ciarrocchi
Ingo Molnar
parent
f975182719
commit
fb87a298fb
1 changed files with 48 additions and 46 deletions
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@ -20,7 +20,7 @@
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* the chip setting when fixing the bug but they also tweaked some
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* performance at the same time..
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*/
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extern void vide(void);
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__asm__(".align 4\nvide: ret");
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@ -81,7 +81,8 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
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#ifdef CONFIG_SMP
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unsigned long long value;
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/* Disable TLB flush filter by setting HWCR.FFDIS on K8
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/*
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* Disable TLB flush filter by setting HWCR.FFDIS on K8
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* bit 6 of msr C001_0015
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*
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* Errata 63 for SH-B3 steppings
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@ -102,15 +103,16 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
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* no bus pipeline)
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*/
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/* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
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3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
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/*
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* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
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* DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
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*/
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clear_bit(0*32+31, c->x86_capability);
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r = get_model_name(c);
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switch(c->x86)
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{
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case 4:
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switch (c->x86) {
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case 4:
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/*
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* General Systems BIOSen alias the cpu frequency registers
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* of the Elan at 0x000df000. Unfortuantly, one of the Linux
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@ -120,61 +122,60 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
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#define CBAR (0xfffc) /* Configuration Base Address (32-bit) */
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#define CBAR_ENB (0x80000000)
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#define CBAR_KEY (0X000000CB)
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if (c->x86_model==9 || c->x86_model == 10) {
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if (c->x86_model == 9 || c->x86_model == 10) {
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if (inl (CBAR) & CBAR_ENB)
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outl (0 | CBAR_KEY, CBAR);
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}
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break;
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case 5:
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if( c->x86_model < 6 )
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{
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case 5:
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if (c->x86_model < 6) {
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/* Based on AMD doc 20734R - June 2000 */
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if ( c->x86_model == 0 ) {
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if (c->x86_model == 0) {
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clear_bit(X86_FEATURE_APIC, c->x86_capability);
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set_bit(X86_FEATURE_PGE, c->x86_capability);
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}
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break;
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}
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if ( c->x86_model == 6 && c->x86_mask == 1 ) {
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if (c->x86_model == 6 && c->x86_mask == 1) {
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const int K6_BUG_LOOP = 1000000;
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int n;
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void (*f_vide)(void);
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unsigned long d, d2;
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printk(KERN_INFO "AMD K6 stepping B detected - ");
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/*
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* It looks like AMD fixed the 2.6.2 bug and improved indirect
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* It looks like AMD fixed the 2.6.2 bug and improved indirect
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* calls at the same time.
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*/
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n = K6_BUG_LOOP;
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f_vide = vide;
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rdtscl(d);
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while (n--)
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while (n--)
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f_vide();
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rdtscl(d2);
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d = d2-d;
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if (d > 20*K6_BUG_LOOP)
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if (d > 20*K6_BUG_LOOP)
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printk("system stability may be impaired when more than 32 MB are used.\n");
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else
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else
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printk("probably OK (after B9730xxxx).\n");
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printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n");
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}
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/* K6 with old style WHCR */
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if (c->x86_model < 8 ||
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(c->x86_model== 8 && c->x86_mask < 8)) {
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(c->x86_model == 8 && c->x86_mask < 8)) {
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/* We can only write allocate on the low 508Mb */
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if(mbytes>508)
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mbytes=508;
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if (mbytes > 508)
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mbytes = 508;
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rdmsr(MSR_K6_WHCR, l, h);
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if ((l&0x0000FFFF)==0) {
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if ((l&0x0000FFFF) == 0) {
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unsigned long flags;
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l=(1<<0)|((mbytes/4)<<1);
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l = (1<<0)|((mbytes/4)<<1);
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local_irq_save(flags);
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wbinvd();
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wrmsr(MSR_K6_WHCR, l, h);
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@ -185,17 +186,17 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
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break;
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}
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if ((c->x86_model == 8 && c->x86_mask >7) ||
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if ((c->x86_model == 8 && c->x86_mask > 7) ||
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c->x86_model == 9 || c->x86_model == 13) {
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/* The more serious chips .. */
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if(mbytes>4092)
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mbytes=4092;
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if (mbytes > 4092)
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mbytes = 4092;
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rdmsr(MSR_K6_WHCR, l, h);
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if ((l&0xFFFF0000)==0) {
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if ((l&0xFFFF0000) == 0) {
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unsigned long flags;
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l=((mbytes>>2)<<22)|(1<<16);
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l = ((mbytes>>2)<<22)|(1<<16);
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local_irq_save(flags);
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wbinvd();
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wrmsr(MSR_K6_WHCR, l, h);
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@ -217,10 +218,11 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
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break;
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}
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break;
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case 6: /* An Athlon/Duron */
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/* Bit 15 of Athlon specific MSR 15, needs to be 0
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* to enable SSE on Palomino/Morgan/Barton CPU's.
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case 6: /* An Athlon/Duron */
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/*
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* Bit 15 of Athlon specific MSR 15, needs to be 0
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* to enable SSE on Palomino/Morgan/Barton CPU's.
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* If the BIOS didn't enable it already, enable it here.
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*/
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if (c->x86_model >= 6 && c->x86_model <= 10) {
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@ -233,11 +235,12 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
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}
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}
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/* It's been determined by AMD that Athlons since model 8 stepping 1
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/*
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* It's been determined by AMD that Athlons since model 8 stepping 1
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* are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
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* As per AMD technical note 27212 0.2
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*/
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if ((c->x86_model == 8 && c->x86_mask>=1) || (c->x86_model > 8)) {
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if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) {
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rdmsr(MSR_K7_CLK_CTL, l, h);
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if ((l & 0xfff00000) != 0x20000000) {
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printk ("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", l,
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@ -256,7 +259,7 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
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set_bit(X86_FEATURE_K8, c->x86_capability);
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break;
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case 6:
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set_bit(X86_FEATURE_K7, c->x86_capability);
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set_bit(X86_FEATURE_K7, c->x86_capability);
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break;
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}
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if (c->x86 >= 6)
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@ -264,9 +267,8 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
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display_cacheinfo(c);
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if (cpuid_eax(0x80000000) >= 0x80000008) {
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if (cpuid_eax(0x80000000) >= 0x80000008)
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c->x86_max_cores = (cpuid_ecx(0x80000008) & 0xff) + 1;
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}
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#ifdef CONFIG_X86_HT
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/*
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@ -308,14 +310,14 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
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set_bit(X86_FEATURE_MFENCE_RDTSC, c->x86_capability);
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}
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static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 * c, unsigned int size)
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static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
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{
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/* AMD errata T13 (order #21922) */
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if ((c->x86 == 6)) {
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if (c->x86_model == 3 && c->x86_mask == 0) /* Duron Rev A0 */
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size = 64;
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if (c->x86_model == 4 &&
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(c->x86_mask==0 || c->x86_mask==1)) /* Tbird rev A1/A2 */
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(c->x86_mask == 0 || c->x86_mask == 1)) /* Tbird rev A1/A2 */
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size = 256;
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}
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return size;
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@ -323,16 +325,16 @@ static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 * c, unsigned in
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static struct cpu_dev amd_cpu_dev __cpuinitdata = {
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.c_vendor = "AMD",
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.c_ident = { "AuthenticAMD" },
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.c_ident = { "AuthenticAMD" },
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.c_models = {
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{ .vendor = X86_VENDOR_AMD, .family = 4, .model_names =
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{
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[3] = "486 DX/2",
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[7] = "486 DX/2-WB",
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[8] = "486 DX/4",
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[9] = "486 DX/4-WB",
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[8] = "486 DX/4",
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[9] = "486 DX/4-WB",
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[14] = "Am5x86-WT",
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[15] = "Am5x86-WB"
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[15] = "Am5x86-WB"
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}
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},
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},
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