Merge branch 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6
* 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: drm/radeon/nouveau: fix build regression on alpha due to Xen changes. drm/radeon/kms: fix cayman acceleration drm/radeon: fix cayman struct accessors.
This commit is contained in:
commit
fad632092a
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@ -42,7 +42,8 @@ nouveau_sgdma_populate(struct ttm_backend *be, unsigned long num_pages,
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nvbe->nr_pages = 0;
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nvbe->nr_pages = 0;
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while (num_pages--) {
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while (num_pages--) {
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if (dma_addrs[nvbe->nr_pages] != DMA_ERROR_CODE) {
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/* this code path isn't called and is incorrect anyways */
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if (0) { /*dma_addrs[nvbe->nr_pages] != DMA_ERROR_CODE)*/
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nvbe->pages[nvbe->nr_pages] =
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nvbe->pages[nvbe->nr_pages] =
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dma_addrs[nvbe->nr_pages];
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dma_addrs[nvbe->nr_pages];
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nvbe->ttm_alloced[nvbe->nr_pages] = true;
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nvbe->ttm_alloced[nvbe->nr_pages] = true;
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@ -674,7 +674,7 @@ static void cayman_gpu_init(struct radeon_device *rdev)
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cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE);
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cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE);
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cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG);
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cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG);
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cgts_tcc_disable = RREG32(CGTS_TCC_DISABLE);
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cgts_tcc_disable = 0xff000000;
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gc_user_rb_backend_disable = RREG32(GC_USER_RB_BACKEND_DISABLE);
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gc_user_rb_backend_disable = RREG32(GC_USER_RB_BACKEND_DISABLE);
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gc_user_shader_pipe_config = RREG32(GC_USER_SHADER_PIPE_CONFIG);
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gc_user_shader_pipe_config = RREG32(GC_USER_SHADER_PIPE_CONFIG);
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cgts_user_tcc_disable = RREG32(CGTS_USER_TCC_DISABLE);
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cgts_user_tcc_disable = RREG32(CGTS_USER_TCC_DISABLE);
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@ -871,7 +871,7 @@ static void cayman_gpu_init(struct radeon_device *rdev)
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smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
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smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
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smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
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smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
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smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
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smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.cayman.sx_num_of_sets);
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WREG32(SMX_DC_CTL0, smx_dc_ctl0);
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WREG32(SMX_DC_CTL0, smx_dc_ctl0);
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WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE);
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WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE);
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@ -887,20 +887,20 @@ static void cayman_gpu_init(struct radeon_device *rdev)
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WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO);
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WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO);
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WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
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WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1) |
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POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
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POSITION_BUFFER_SIZE((rdev->config.cayman.sx_max_export_pos_size / 4) - 1) |
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SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
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SMX_BUFFER_SIZE((rdev->config.cayman.sx_max_export_smx_size / 4) - 1)));
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WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
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WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) |
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SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
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SC_HIZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_hiz_tile_fifo_size) |
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SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
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SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_earlyz_tile_fifo_size)));
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WREG32(VGT_NUM_INSTANCES, 1);
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WREG32(VGT_NUM_INSTANCES, 1);
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WREG32(CP_PERFMON_CNTL, 0);
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WREG32(CP_PERFMON_CNTL, 0);
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WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
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WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) |
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FETCH_FIFO_HIWATER(0x4) |
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FETCH_FIFO_HIWATER(0x4) |
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DONE_FIFO_HIWATER(0xe0) |
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DONE_FIFO_HIWATER(0xe0) |
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ALU_UPDATE_FIFO_HIWATER(0x8)));
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ALU_UPDATE_FIFO_HIWATER(0x8)));
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@ -181,9 +181,9 @@ int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
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p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
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p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
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for (i = 0; i < pages; i++, p++) {
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for (i = 0; i < pages; i++, p++) {
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/* On TTM path, we only use the DMA API if TTM_PAGE_FLAG_DMA32
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/* we reverted the patch using dma_addr in TTM for now but this
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* is requested. */
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* code stops building on alpha so just comment it out for now */
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if (dma_addr[i] != DMA_ERROR_CODE) {
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if (0) { /*dma_addr[i] != DMA_ERROR_CODE) */
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rdev->gart.ttm_alloced[p] = true;
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rdev->gart.ttm_alloced[p] = true;
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rdev->gart.pages_addr[p] = dma_addr[i];
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rdev->gart.pages_addr[p] = dma_addr[i];
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} else {
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} else {
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