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microblaze: Checking DTS against PVR for write-back cache 

WB cache has special flag in PVR. There is added checking mechanism
for PVR and DTS.

Signed-off-by: Michal Simek <monstr@monstr.eu>
This commit is contained in:
Michal Simek 2009-10-21 12:29:46 +02:00
parent d4f182700b
commit f6e1f1b480
2 changed files with 29 additions and 12 deletions
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30
arch/microblaze/include/asm/pvr.h
View File

@ -76,20 +76,23 @@ struct pvr_s {
#define PVR3_FSL_LINKS_MASK 0x00000380
/* ICache config PVR masks */
#define PVR4_USE_ICACHE_MASK 0x80000000
#define PVR4_ICACHE_ADDR_TAG_BITS_MASK 0x7C000000
#define PVR4_ICACHE_USE_FSL_MASK 0x02000000
#define PVR4_ICACHE_ALLOW_WR_MASK 0x01000000
#define PVR4_ICACHE_LINE_LEN_MASK 0x00E00000
#define PVR4_ICACHE_BYTE_SIZE_MASK 0x001F0000
#define PVR4_USE_ICACHE_MASK 0x80000000 /* ICU */
#define PVR4_ICACHE_ADDR_TAG_BITS_MASK 0x7C000000 /* ICTS */
#define PVR4_ICACHE_ALLOW_WR_MASK 0x01000000 /* ICW */
#define PVR4_ICACHE_LINE_LEN_MASK 0x00E00000 /* ICLL */
#define PVR4_ICACHE_BYTE_SIZE_MASK 0x001F0000 /* ICBS */
#define PVR4_ICACHE_ALWAYS_USED 0x00008000 /* IAU */
#define PVR4_ICACHE_INTERFACE 0x00002000 /* ICI */
/* DCache config PVR masks */
#define PVR5_USE_DCACHE_MASK 0x80000000
#define PVR5_DCACHE_ADDR_TAG_BITS_MASK 0x7C000000
#define PVR5_DCACHE_USE_FSL_MASK 0x02000000
#define PVR5_DCACHE_ALLOW_WR_MASK 0x01000000
#define PVR5_DCACHE_LINE_LEN_MASK 0x00E00000
#define PVR5_DCACHE_BYTE_SIZE_MASK 0x001F0000
#define PVR5_USE_DCACHE_MASK 0x80000000 /* DCU */
#define PVR5_DCACHE_ADDR_TAG_BITS_MASK 0x7C000000 /* DCTS */
#define PVR5_DCACHE_ALLOW_WR_MASK 0x01000000 /* DCW */
#define PVR5_DCACHE_LINE_LEN_MASK 0x00E00000 /* DCLL */
#define PVR5_DCACHE_BYTE_SIZE_MASK 0x001F0000 /* DCBS */
#define PVR5_DCACHE_ALWAYS_USED 0x00008000 /* DAU */
#define PVR5_DCACHE_USE_WRITEBACK 0x00004000 /* DWB */
#define PVR5_DCACHE_INTERFACE 0x00002000 /* DCI */
/* ICache base address PVR mask */
#define PVR6_ICACHE_BASEADDR_MASK 0xFFFFFFFF
@ -178,11 +181,14 @@ struct pvr_s {
((pvr.pvr[5] & PVR5_DCACHE_ADDR_TAG_BITS_MASK) >> 26)
#define PVR_DCACHE_USE_FSL(pvr) (pvr.pvr[5] & PVR5_DCACHE_USE_FSL_MASK)
#define PVR_DCACHE_ALLOW_WR(pvr) (pvr.pvr[5] & PVR5_DCACHE_ALLOW_WR_MASK)
/* FIXME two shifts on one line needs any comment */
#define PVR_DCACHE_LINE_LEN(pvr) \
(1 << ((pvr.pvr[5] & PVR5_DCACHE_LINE_LEN_MASK) >> 21))
#define PVR_DCACHE_BYTE_SIZE(pvr) \
(1 << ((pvr.pvr[5] & PVR5_DCACHE_BYTE_SIZE_MASK) >> 16))
#define PVR_DCACHE_USE_WRITEBACK(pvr) \
((pvr.pvr[5] & PVR5_DCACHE_USE_WRITEBACK) >> 14)
#define PVR_ICACHE_BASEADDR(pvr) (pvr.pvr[6] & PVR6_ICACHE_BASEADDR_MASK)
#define PVR_ICACHE_HIGHADDR(pvr) (pvr.pvr[7] & PVR7_ICACHE_HIGHADDR_MASK)

11
arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c
View File

@ -21,8 +21,14 @@
*/
#define CI(c, p) { ci->c = PVR_##p(pvr); }
#if defined(CONFIG_EARLY_PRINTK) && defined(CONFIG_SERIAL_UARTLITE_CONSOLE)
#define err_printk(x) \
early_printk("ERROR: Microblaze " x "-different for PVR and DTS\n");
#else
#define err_printk(x) \
printk(KERN_INFO "ERROR: Microblaze " x "-different for PVR and DTS\n");
#endif
void set_cpuinfo_pvr_full(struct cpuinfo *ci, struct device_node *cpu)
{
@ -83,6 +89,11 @@ void set_cpuinfo_pvr_full(struct cpuinfo *ci, struct device_node *cpu)
CI(dcache_base, DCACHE_BASEADDR);
CI(dcache_high, DCACHE_HIGHADDR);
temp = PVR_DCACHE_USE_WRITEBACK(pvr);
if (ci->dcache_wb != temp)
err_printk("DCACHE WB");
ci->dcache_wb = temp;
CI(use_dopb, D_OPB);
CI(use_iopb, I_OPB);
CI(use_dlmb, D_LMB);