MIPS: Cavium: Add EDAC support.
Drivers for EDAC on Cavium. Supported subsystems are: o CPU primary caches. These are parity protected only, so only error reporting. o Second level cache - ECC protected, provides SECDED. o Memory: ECC / SECDEC if used with suitable DRAM modules. The driver will will only initialize if ECC is enabled on a system so is safe to run on non-ECC memory. o PCI: Parity error reporting Since it is very hard to test this sort of code the implementation is very conservative and uses polling where possible for now. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Reviewed-by: Borislav Petkov <borislav.petkov@amd.com>
This commit is contained in:
Ralf Baechle
parent
aa1762f49c
commit
f65aad4177
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@ -2722,6 +2722,15 @@ W: bluesmoke.sourceforge.net
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S: Maintained
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F: drivers/edac/amd64_edac*
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EDAC-CAVIUM
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M: Ralf Baechle <ralf@linux-mips.org>
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M: David Daney <david.daney@cavium.com>
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L: linux-edac@vger.kernel.org
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L: linux-mips@linux-mips.org
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W: bluesmoke.sourceforge.net
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S: Supported
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F: drivers/edac/octeon_edac*
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EDAC-E752X
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M: Mark Gross <mark.gross@intel.com>
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M: Doug Thompson <dougthompson@xmission.com>
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@ -774,6 +774,7 @@ config CAVIUM_OCTEON_REFERENCE_BOARD
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select DMA_COHERENT
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select SYS_SUPPORTS_64BIT_KERNEL
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select SYS_SUPPORTS_BIG_ENDIAN
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select EDAC_SUPPORT
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select SYS_SUPPORTS_HOTPLUG_CPU
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select SYS_HAS_EARLY_PRINTK
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select SYS_HAS_CPU_CAVIUM_OCTEON
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@ -4,9 +4,11 @@
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* for more details.
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*
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* Copyright (C) 2004-2007 Cavium Networks
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* Copyright (C) 2008 Wind River Systems
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* Copyright (C) 2008, 2009 Wind River Systems
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* written by Ralf Baechle <ralf@linux-mips.org>
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/console.h>
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#include <linux/delay.h>
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#include <linux/export.h>
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@ -821,3 +823,29 @@ void __init device_tree_init(void)
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}
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unflatten_device_tree();
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}
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static char *edac_device_names[] = {
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"co_l2c_edac",
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"co_lmc_edac",
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"co_pc_edac",
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};
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static int __init edac_devinit(void)
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{
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struct platform_device *dev;
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int i, err = 0;
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char *name;
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for (i = 0; i < ARRAY_SIZE(edac_device_names); i++) {
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name = edac_device_names[i];
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dev = platform_device_register_simple(name, -1, NULL, 0);
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if (IS_ERR(dev)) {
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pr_err("Registation of %s failed!\n", name);
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err = PTR_ERR(dev);
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}
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}
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return err;
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}
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device_initcall(edac_devinit);
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@ -5,6 +5,7 @@
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*
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* Copyright (C) 2005-2007 Cavium Networks
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*/
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#include <linux/export.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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@ -28,6 +29,7 @@
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#include <asm/octeon/octeon.h>
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unsigned long long cache_err_dcache[NR_CPUS];
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EXPORT_SYMBOL_GPL(cache_err_dcache);
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/**
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* Octeon automatically flushes the dcache on tlb changes, so
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@ -288,42 +290,42 @@ void __cpuinit octeon_cache_init(void)
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* Handle a cache error exception
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*/
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static void cache_parity_error_octeon(int non_recoverable)
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static RAW_NOTIFIER_HEAD(co_cache_error_chain);
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int register_co_cache_error_notifier(struct notifier_block *nb)
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{
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unsigned long coreid = cvmx_get_core_num();
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uint64_t icache_err = read_octeon_c0_icacheerr();
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return raw_notifier_chain_register(&co_cache_error_chain, nb);
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}
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EXPORT_SYMBOL_GPL(register_co_cache_error_notifier);
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pr_err("Cache error exception:\n");
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pr_err("cp0_errorepc == %lx\n", read_c0_errorepc());
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if (icache_err & 1) {
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pr_err("CacheErr (Icache) == %llx\n",
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(unsigned long long)icache_err);
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write_octeon_c0_icacheerr(0);
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}
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if (cache_err_dcache[coreid] & 1) {
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pr_err("CacheErr (Dcache) == %llx\n",
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(unsigned long long)cache_err_dcache[coreid]);
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cache_err_dcache[coreid] = 0;
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}
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int unregister_co_cache_error_notifier(struct notifier_block *nb)
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{
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return raw_notifier_chain_unregister(&co_cache_error_chain, nb);
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}
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EXPORT_SYMBOL_GPL(unregister_co_cache_error_notifier);
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if (non_recoverable)
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panic("Can't handle cache error: nested exception");
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static inline int co_cache_error_call_notifiers(unsigned long val)
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{
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return raw_notifier_call_chain(&co_cache_error_chain, val, NULL);
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}
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/**
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* Called when the the exception is recoverable
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*/
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asmlinkage void cache_parity_error_octeon_recoverable(void)
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{
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cache_parity_error_octeon(0);
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co_cache_error_call_notifiers(0);
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}
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/**
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* Called when the the exception is not recoverable
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*
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* The issue not that the cache error exception itself was non-recoverable
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* but that due to nesting of exception may have lost some state so can't
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* continue.
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*/
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asmlinkage void cache_parity_error_octeon_non_recoverable(void)
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{
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cache_parity_error_octeon(1);
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co_cache_error_call_notifiers(1);
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panic("Can't handle cache error: nested exception");
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}
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@ -11,6 +11,7 @@
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#include <linux/interrupt.h>
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#include <linux/time.h>
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#include <linux/delay.h>
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#include <linux/platform_device.h>
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#include <linux/swiotlb.h>
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#include <asm/time.h>
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@ -704,6 +705,9 @@ static int __init octeon_pci_setup(void)
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*/
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cvmx_write_csr(CVMX_NPI_PCI_INT_SUM2, -1);
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if (IS_ERR(platform_device_register_simple("co_pci_edac", 0, NULL, 0)))
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pr_err("Registation of co_pci_edac failed!\n");
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octeon_pci_dma_init();
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return 0;
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@ -7,7 +7,7 @@
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menuconfig EDAC
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bool "EDAC (Error Detection And Correction) reporting"
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depends on HAS_IOMEM
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depends on X86 || PPC || TILE || ARM
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depends on X86 || PPC || TILE || ARM || EDAC_SUPPORT
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help
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EDAC is designed to report errors in the core system.
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These are low-level errors that are reported in the CPU or
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@ -27,6 +27,9 @@ menuconfig EDAC
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There is also a mailing list for the EDAC project, which can
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be found via the sourceforge page.
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config EDAC_SUPPORT
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bool
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if EDAC
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comment "Reporting subsystems"
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@ -316,4 +319,32 @@ config EDAC_HIGHBANK_L2
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Support for error detection and correction on the
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Calxeda Highbank memory controller.
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config EDAC_OCTEON_PC
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tristate "Cavium Octeon Primary Caches"
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depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON
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help
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Support for error detection and correction on the primary caches of
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the cnMIPS cores of Cavium Octeon family SOCs.
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config EDAC_OCTEON_L2C
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tristate "Cavium Octeon Secondary Caches (L2C)"
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depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON
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help
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Support for error detection and correction on the
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Cavium Octeon family of SOCs.
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config EDAC_OCTEON_LMC
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tristate "Cavium Octeon DRAM Memory Controller (LMC)"
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depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON
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help
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Support for error detection and correction on the
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Cavium Octeon family of SOCs.
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config EDAC_OCTEON_PCI
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tristate "Cavium Octeon PCI Controller"
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depends on EDAC_MM_EDAC && PCI && CPU_CAVIUM_OCTEON
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help
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Support for error detection and correction on the
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Cavium Octeon family of SOCs.
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endif # EDAC
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@ -58,3 +58,8 @@ obj-$(CONFIG_EDAC_TILE) += tile_edac.o
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obj-$(CONFIG_EDAC_HIGHBANK_MC) += highbank_mc_edac.o
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obj-$(CONFIG_EDAC_HIGHBANK_L2) += highbank_l2_edac.o
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obj-$(CONFIG_EDAC_OCTEON_PC) += octeon_edac-pc.o
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obj-$(CONFIG_EDAC_OCTEON_L2C) += octeon_edac-l2c.o
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obj-$(CONFIG_EDAC_OCTEON_LMC) += octeon_edac-lmc.o
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obj-$(CONFIG_EDAC_OCTEON_PCI) += octeon_edac-pci.o
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@ -0,0 +1,118 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2009 Wind River Systems,
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* written by Ralf Baechle <ralf@linux-mips.org>
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/edac.h>
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#include <asm/octeon/cvmx.h>
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#include "edac_core.h"
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#include "edac_module.h"
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#define EDAC_MOD_STR "octeon-l2c"
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static void co_l2c_poll(struct edac_device_ctl_info *l2c)
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{
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union cvmx_l2t_err l2t_err;
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l2t_err.u64 = cvmx_read_csr(CVMX_L2T_ERR);
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if (l2t_err.s.sec_err) {
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edac_device_handle_ce(l2c, 0, 0,
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"Single bit error (corrected)");
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l2t_err.s.sec_err = 1; /* Reset */
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cvmx_write_csr(CVMX_L2T_ERR, l2t_err.u64);
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}
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if (l2t_err.s.ded_err) {
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edac_device_handle_ue(l2c, 0, 0,
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"Double bit error (corrected)");
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l2t_err.s.ded_err = 1; /* Reset */
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cvmx_write_csr(CVMX_L2T_ERR, l2t_err.u64);
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}
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}
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static int __devinit co_l2c_probe(struct platform_device *pdev)
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{
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struct edac_device_ctl_info *l2c;
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union cvmx_l2t_err l2t_err;
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int res = 0;
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l2c = edac_device_alloc_ctl_info(0, "l2c", 1, NULL, 0, 0,
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NULL, 0, edac_device_alloc_index());
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if (!l2c)
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return -ENOMEM;
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l2c->dev = &pdev->dev;
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platform_set_drvdata(pdev, l2c);
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l2c->dev_name = dev_name(&pdev->dev);
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l2c->mod_name = "octeon-l2c";
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l2c->ctl_name = "octeon_l2c_err";
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l2c->edac_check = co_l2c_poll;
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if (edac_device_add_device(l2c) > 0) {
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pr_err("%s: edac_device_add_device() failed\n", __func__);
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goto err;
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}
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l2t_err.u64 = cvmx_read_csr(CVMX_L2T_ERR);
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l2t_err.s.sec_intena = 0; /* We poll */
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l2t_err.s.ded_intena = 0;
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l2t_err.s.sec_err = 1; /* Clear, just in case */
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l2t_err.s.ded_err = 1;
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cvmx_write_csr(CVMX_L2T_ERR, l2t_err.u64);
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return 0;
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err:
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edac_device_free_ctl_info(l2c);
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return res;
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}
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static int co_l2c_remove(struct platform_device *pdev)
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{
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struct edac_device_ctl_info *l2c = platform_get_drvdata(pdev);
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edac_device_del_device(&pdev->dev);
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edac_device_free_ctl_info(l2c);
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return 0;
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}
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static struct platform_driver co_l2c_driver = {
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.probe = co_l2c_probe,
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.remove = co_l2c_remove,
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.driver = {
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.name = "co_l2c_edac",
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}
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};
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static int __init co_edac_init(void)
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{
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int ret;
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ret = platform_driver_register(&co_l2c_driver);
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if (ret)
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pr_warning(EDAC_MOD_STR " EDAC failed to register\n");
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return ret;
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}
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static void __exit co_edac_exit(void)
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{
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platform_driver_unregister(&co_l2c_driver);
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}
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module_init(co_edac_init);
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module_exit(co_edac_exit);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
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@ -0,0 +1,150 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2009 Wind River Systems,
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* written by Ralf Baechle <ralf@linux-mips.org>
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/edac.h>
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#include <asm/octeon/cvmx.h>
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#include "edac_core.h"
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#include "edac_module.h"
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#include "octeon_edac-lmc.h"
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#define EDAC_MOD_STR "octeon"
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static struct mem_ctl_info *mc_cavium;
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static void *lmc_base;
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static void co_lmc_poll(struct mem_ctl_info *mci)
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{
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union lmc_mem_cfg0 cfg0;
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union lmc_fadr fadr;
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char msg[64];
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fadr.u64 = readq(lmc_base + LMC_FADR);
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cfg0.u64 = readq(lmc_base + LMC_MEM_CFG0);
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snprintf(msg, sizeof(msg), "DIMM %d rank %d bank %d row %d col %d",
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fadr.fdimm, fadr.fbunk, fadr.fbank, fadr.frow, fadr.fcol);
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if (cfg0.sec_err) {
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edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 0, 0, 0, -1, -1, -1,
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msg, "");
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cfg0.intr_sec_ena = -1; /* Done, re-arm */
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}
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if (cfg0.ded_err) {
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edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0, -1, -1, -1,
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msg, "");
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cfg0.intr_ded_ena = -1; /* Done, re-arm */
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}
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writeq(cfg0.u64, lmc_base + LMC_MEM_CFG0);
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}
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static int __devinit co_lmc_probe(struct platform_device *pdev)
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{
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struct mem_ctl_info *mci;
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union lmc_mem_cfg0 cfg0;
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int res = 0;
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mci = edac_mc_alloc(0, 0, 0, 0);
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if (!mci)
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return -ENOMEM;
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mci->pdev = &pdev->dev;
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platform_set_drvdata(pdev, mci);
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mci->dev_name = dev_name(&pdev->dev);
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mci->mod_name = "octeon-lmc";
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mci->ctl_name = "co_lmc_err";
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mci->edac_check = co_lmc_poll;
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if (edac_mc_add_mc(mci) > 0) {
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pr_err("%s: edac_mc_add_mc() failed\n", __func__);
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goto err;
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}
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cfg0.u64 = readq(lmc_base + LMC_MEM_CFG0); /* We poll */
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cfg0.intr_ded_ena = 0;
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cfg0.intr_sec_ena = 0;
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writeq(cfg0.u64, lmc_base + LMC_MEM_CFG0);
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mc_cavium = mci;
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return 0;
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err:
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edac_mc_free(mci);
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return res;
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}
|
||||
|
||||
static int co_lmc_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct mem_ctl_info *mci = platform_get_drvdata(pdev);
|
||||
|
||||
mc_cavium = NULL;
|
||||
edac_mc_del_mc(&pdev->dev);
|
||||
edac_mc_free(mci);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver co_lmc_driver = {
|
||||
.probe = co_lmc_probe,
|
||||
.remove = co_lmc_remove,
|
||||
.driver = {
|
||||
.name = "co_lmc_edac",
|
||||
}
|
||||
};
|
||||
|
||||
static int __init co_edac_init(void)
|
||||
{
|
||||
union lmc_mem_cfg0 cfg0;
|
||||
int ret;
|
||||
|
||||
lmc_base = ioremap_nocache(LMC_BASE, LMC_SIZE);
|
||||
if (!lmc_base)
|
||||
return -ENOMEM;
|
||||
|
||||
cfg0.u64 = readq(lmc_base + LMC_MEM_CFG0);
|
||||
if (!cfg0.ecc_ena) {
|
||||
pr_info(EDAC_MOD_STR " LMC EDAC: ECC disabled, good bye\n");
|
||||
ret = -ENODEV;
|
||||
goto out;
|
||||
}
|
||||
|
||||
ret = platform_driver_register(&co_lmc_driver);
|
||||
if (ret) {
|
||||
pr_warning(EDAC_MOD_STR " LMC EDAC failed to register\n");
|
||||
goto out;
|
||||
}
|
||||
|
||||
return ret;
|
||||
|
||||
out:
|
||||
iounmap(lmc_base);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void __exit co_edac_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&co_lmc_driver);
|
||||
iounmap(lmc_base);
|
||||
}
|
||||
|
||||
module_init(co_edac_init);
|
||||
module_exit(co_edac_exit);
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
|
||||
|
|
@ -0,0 +1,78 @@
|
|||
/*
|
||||
* LMC Registers, see chapter 2.5
|
||||
*
|
||||
* These are RSL Type registers and are accessed indirectly across the
|
||||
* I/O bus, so accesses are slowish. Not that it matters. Any size load is
|
||||
* ok but stores must be 64-bit.
|
||||
*/
|
||||
#define LMC_BASE 0x0001180088000000
|
||||
#define LMC_SIZE 0xb8
|
||||
|
||||
#define LMC_MEM_CFG0 0x0000000000000000
|
||||
#define LMC_MEM_CFG1 0x0000000000000008
|
||||
#define LMC_CTL 0x0000000000000010
|
||||
#define LMC_DDR2_CTL 0x0000000000000018
|
||||
#define LMC_FADR 0x0000000000000020
|
||||
#define LMC_FADR_FDIMM
|
||||
#define LMC_FADR_FBUNK
|
||||
#define LMC_FADR_FBANK
|
||||
#define LMC_FADR_FROW
|
||||
#define LMC_FADR_FCOL
|
||||
#define LMC_COMP_CTL 0x0000000000000028
|
||||
#define LMC_WODT_CTL 0x0000000000000030
|
||||
#define LMC_ECC_SYND 0x0000000000000038
|
||||
#define LMC_IFB_CNT_LO 0x0000000000000048
|
||||
#define LMC_IFB_CNT_HI 0x0000000000000050
|
||||
#define LMC_OPS_CNT_LO 0x0000000000000058
|
||||
#define LMC_OPS_CNT_HI 0x0000000000000060
|
||||
#define LMC_DCLK_CNT_LO 0x0000000000000068
|
||||
#define LMC_DCLK_CNT_HI 0x0000000000000070
|
||||
#define LMC_DELAY_CFG 0x0000000000000088
|
||||
#define LMC_CTL1 0x0000000000000090
|
||||
#define LMC_DUAL_MEM_CONFIG 0x0000000000000098
|
||||
#define LMC_RODT_COMP_CTL 0x00000000000000A0
|
||||
#define LMC_PLL_CTL 0x00000000000000A8
|
||||
#define LMC_PLL_STATUS 0x00000000000000B0
|
||||
|
||||
union lmc_mem_cfg0 {
|
||||
uint64_t u64;
|
||||
struct {
|
||||
uint64_t reserved_32_63:32;
|
||||
uint64_t reset:1;
|
||||
uint64_t silo_qc:1;
|
||||
uint64_t bunk_ena:1;
|
||||
uint64_t ded_err:4;
|
||||
uint64_t sec_err:4;
|
||||
uint64_t intr_ded_ena:1;
|
||||
uint64_t intr_sec_ena:1;
|
||||
uint64_t reserved_15_18:4;
|
||||
uint64_t ref_int:5;
|
||||
uint64_t pbank_lsb:4;
|
||||
uint64_t row_lsb:3;
|
||||
uint64_t ecc_ena:1;
|
||||
uint64_t init_start:1;
|
||||
};
|
||||
};
|
||||
|
||||
union lmc_fadr {
|
||||
uint64_t u64;
|
||||
struct {
|
||||
uint64_t reserved_32_63:32;
|
||||
uint64_t fdimm:2;
|
||||
uint64_t fbunk:1;
|
||||
uint64_t fbank:3;
|
||||
uint64_t frow:14;
|
||||
uint64_t fcol:12;
|
||||
};
|
||||
};
|
||||
|
||||
union lmc_ecc_synd {
|
||||
uint64_t u64;
|
||||
struct {
|
||||
uint64_t reserved_32_63:32;
|
||||
uint64_t mrdsyn3:8;
|
||||
uint64_t mrdsyn2:8;
|
||||
uint64_t mrdsyn1:8;
|
||||
uint64_t mrdsyn0:8;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,140 @@
|
|||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2009 Wind River Systems,
|
||||
* written by Ralf Baechle <ralf@linux-mips.org>
|
||||
*/
|
||||
#include <linux/module.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/edac.h>
|
||||
|
||||
#include "edac_core.h"
|
||||
#include "edac_module.h"
|
||||
|
||||
#include <asm/octeon/cvmx.h>
|
||||
#include <asm/mipsregs.h>
|
||||
|
||||
#define EDAC_MOD_STR "octeon"
|
||||
|
||||
extern int register_co_cache_error_notifier(struct notifier_block *nb);
|
||||
extern int unregister_co_cache_error_notifier(struct notifier_block *nb);
|
||||
|
||||
extern unsigned long long cache_err_dcache[NR_CPUS];
|
||||
|
||||
static struct edac_device_ctl_info *ed_cavium;
|
||||
|
||||
/*
|
||||
* EDAC CPU cache error callback
|
||||
*
|
||||
*/
|
||||
|
||||
static int co_cache_error_event(struct notifier_block *this,
|
||||
unsigned long event, void *ptr)
|
||||
{
|
||||
unsigned int core = cvmx_get_core_num();
|
||||
unsigned int cpu = smp_processor_id();
|
||||
uint64_t icache_err = read_octeon_c0_icacheerr();
|
||||
struct edac_device_ctl_info *ed = ed_cavium;
|
||||
|
||||
edac_device_printk(ed, KERN_ERR,
|
||||
"Cache error exception on core %d / processor %d:\n",
|
||||
core, cpu);
|
||||
edac_device_printk(ed, KERN_ERR,
|
||||
"cp0_errorepc == %lx\n", read_c0_errorepc());
|
||||
if (icache_err & 1) {
|
||||
edac_device_printk(ed, KERN_ERR, "CacheErr (Icache) == %llx\n",
|
||||
(unsigned long long)icache_err);
|
||||
write_octeon_c0_icacheerr(0);
|
||||
edac_device_handle_ce(ed, 0, 0, ed->ctl_name);
|
||||
}
|
||||
if (cache_err_dcache[core] & 1) {
|
||||
edac_device_printk(ed, KERN_ERR, "CacheErr (Dcache) == %llx\n",
|
||||
(unsigned long long)cache_err_dcache[core]);
|
||||
cache_err_dcache[core] = 0;
|
||||
edac_device_handle_ue(ed, 0, 0, ed->ctl_name);
|
||||
}
|
||||
|
||||
return NOTIFY_DONE;
|
||||
}
|
||||
|
||||
static struct notifier_block co_cache_error_notifier = {
|
||||
.notifier_call = co_cache_error_event,
|
||||
};
|
||||
|
||||
static int __devinit co_cache_error_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct edac_device_ctl_info *ed;
|
||||
int res = 0;
|
||||
|
||||
ed = edac_device_alloc_ctl_info(0, "cpu", 1, NULL, 0, 0, NULL, 0,
|
||||
edac_device_alloc_index());
|
||||
|
||||
ed->dev = &pdev->dev;
|
||||
platform_set_drvdata(pdev, ed);
|
||||
ed->dev_name = dev_name(&pdev->dev);
|
||||
|
||||
ed->mod_name = "octeon-cpu";
|
||||
ed->ctl_name = "co_cpu_err";
|
||||
|
||||
if (edac_device_add_device(ed) > 0) {
|
||||
pr_err("%s: edac_device_add_device() failed\n", __func__);
|
||||
goto err;
|
||||
}
|
||||
|
||||
register_co_cache_error_notifier(&co_cache_error_notifier);
|
||||
ed_cavium = ed;
|
||||
|
||||
return 0;
|
||||
|
||||
err:
|
||||
edac_device_free_ctl_info(ed);
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
static int co_cache_error_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct edac_device_ctl_info *ed = platform_get_drvdata(pdev);
|
||||
|
||||
unregister_co_cache_error_notifier(&co_cache_error_notifier);
|
||||
ed_cavium = NULL;
|
||||
edac_device_del_device(&pdev->dev);
|
||||
edac_device_free_ctl_info(ed);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver co_cache_error_driver = {
|
||||
.probe = co_cache_error_probe,
|
||||
.remove = co_cache_error_remove,
|
||||
.driver = {
|
||||
.name = "co_pc_edac",
|
||||
}
|
||||
};
|
||||
|
||||
static int __init co_edac_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = platform_driver_register(&co_cache_error_driver);
|
||||
if (ret)
|
||||
pr_warning(EDAC_MOD_STR "CPU err failed to register\n");
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void __exit co_edac_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&co_cache_error_driver);
|
||||
}
|
||||
|
||||
module_init(co_edac_init);
|
||||
module_exit(co_edac_exit);
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
|
||||
|
|
@ -0,0 +1,135 @@
|
|||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2009 Wind River Systems,
|
||||
* written by Ralf Baechle <ralf@linux-mips.org>
|
||||
*/
|
||||
#include <linux/module.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/edac.h>
|
||||
|
||||
#include <asm/octeon/cvmx.h>
|
||||
#include <asm/octeon/cvmx-npi-defs.h>
|
||||
#include <asm/octeon/cvmx-pci-defs.h>
|
||||
#include <asm/octeon/octeon.h>
|
||||
|
||||
#include "edac_core.h"
|
||||
#include "edac_module.h"
|
||||
|
||||
#define EDAC_MOD_STR "octeon"
|
||||
|
||||
static void co_pci_poll(struct edac_pci_ctl_info *pci)
|
||||
{
|
||||
union cvmx_pci_cfg01 cfg01;
|
||||
|
||||
cfg01.u32 = octeon_npi_read32(CVMX_NPI_PCI_CFG01);
|
||||
if (cfg01.s.dpe) { /* Detected parity error */
|
||||
edac_pci_handle_pe(pci, pci->ctl_name);
|
||||
cfg01.s.dpe = 1; /* Reset */
|
||||
octeon_npi_write32(CVMX_NPI_PCI_CFG01, cfg01.u32);
|
||||
}
|
||||
if (cfg01.s.sse) {
|
||||
edac_pci_handle_npe(pci, "Signaled System Error");
|
||||
cfg01.s.sse = 1; /* Reset */
|
||||
octeon_npi_write32(CVMX_NPI_PCI_CFG01, cfg01.u32);
|
||||
}
|
||||
if (cfg01.s.rma) {
|
||||
edac_pci_handle_npe(pci, "Received Master Abort");
|
||||
cfg01.s.rma = 1; /* Reset */
|
||||
octeon_npi_write32(CVMX_NPI_PCI_CFG01, cfg01.u32);
|
||||
}
|
||||
if (cfg01.s.rta) {
|
||||
edac_pci_handle_npe(pci, "Received Target Abort");
|
||||
cfg01.s.rta = 1; /* Reset */
|
||||
octeon_npi_write32(CVMX_NPI_PCI_CFG01, cfg01.u32);
|
||||
}
|
||||
if (cfg01.s.sta) {
|
||||
edac_pci_handle_npe(pci, "Signaled Target Abort");
|
||||
cfg01.s.sta = 1; /* Reset */
|
||||
octeon_npi_write32(CVMX_NPI_PCI_CFG01, cfg01.u32);
|
||||
}
|
||||
if (cfg01.s.mdpe) {
|
||||
edac_pci_handle_npe(pci, "Master Data Parity Error");
|
||||
cfg01.s.mdpe = 1; /* Reset */
|
||||
octeon_npi_write32(CVMX_NPI_PCI_CFG01, cfg01.u32);
|
||||
}
|
||||
if (cfg01.s.mdpe) {
|
||||
edac_pci_handle_npe(pci, "Master Data Parity Error");
|
||||
cfg01.s.mdpe = 1; /* Reset */
|
||||
octeon_npi_write32(CVMX_NPI_PCI_CFG01, cfg01.u32);
|
||||
}
|
||||
}
|
||||
|
||||
static int __devinit co_pci_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct edac_pci_ctl_info *pci;
|
||||
int res = 0;
|
||||
|
||||
pci = edac_pci_alloc_ctl_info(0, "octeon_pci_err");
|
||||
if (!pci)
|
||||
return -ENOMEM;
|
||||
|
||||
pci->dev = &pdev->dev;
|
||||
platform_set_drvdata(pdev, pci);
|
||||
pci->dev_name = dev_name(&pdev->dev);
|
||||
|
||||
pci->mod_name = "octeon-pci";
|
||||
pci->ctl_name = "octeon_pci_err";
|
||||
pci->edac_check = co_pci_poll;
|
||||
|
||||
if (edac_pci_add_device(pci, 0) > 0) {
|
||||
pr_err("%s: edac_pci_add_device() failed\n", __func__);
|
||||
goto err;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err:
|
||||
edac_pci_free_ctl_info(pci);
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
static int co_pci_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct edac_pci_ctl_info *pci = platform_get_drvdata(pdev);
|
||||
|
||||
edac_pci_del_device(&pdev->dev);
|
||||
edac_pci_free_ctl_info(pci);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver co_pci_driver = {
|
||||
.probe = co_pci_probe,
|
||||
.remove = co_pci_remove,
|
||||
.driver = {
|
||||
.name = "co_pci_edac",
|
||||
}
|
||||
};
|
||||
|
||||
static int __init co_edac_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = platform_driver_register(&co_pci_driver);
|
||||
if (ret)
|
||||
pr_warning(EDAC_MOD_STR " PCI EDAC failed to register\n");
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void __exit co_edac_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&co_pci_driver);
|
||||
}
|
||||
|
||||
module_init(co_edac_init);
|
||||
module_exit(co_edac_exit);
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
|
||||
Reference in New Issue