Blackfin: add MDMA defines to make cross-variant coding easier
Add some defines to make the BF538/BF561 look like most other Blackfin parts in that it has a MDMA0 channel available for low level init. Signed-off-by: Graf Yang <graf.yang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Graf Yang
Mike Frysinger
parent
f339f46b05
commit
f5879fda09
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@ -68,25 +68,6 @@
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#define OFFSET_SCR 0x1C /* SCR Scratch Register */
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#define OFFSET_GCTL 0x24 /* Global Control Register */
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#define bfin_write_MDMA_D0_IRQ_STATUS bfin_write_MDMA0_D0_IRQ_STATUS
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#define bfin_write_MDMA_D0_START_ADDR bfin_write_MDMA0_D0_START_ADDR
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#define bfin_write_MDMA_S0_START_ADDR bfin_write_MDMA0_S0_START_ADDR
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#define bfin_write_MDMA_D0_X_COUNT bfin_write_MDMA0_D0_X_COUNT
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#define bfin_write_MDMA_S0_X_COUNT bfin_write_MDMA0_S0_X_COUNT
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#define bfin_write_MDMA_D0_Y_COUNT bfin_write_MDMA0_D0_Y_COUNT
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#define bfin_write_MDMA_S0_Y_COUNT bfin_write_MDMA0_S0_Y_COUNT
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#define bfin_write_MDMA_D0_X_MODIFY bfin_write_MDMA0_D0_X_MODIFY
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#define bfin_write_MDMA_S0_X_MODIFY bfin_write_MDMA0_S0_X_MODIFY
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#define bfin_write_MDMA_D0_Y_MODIFY bfin_write_MDMA0_D0_Y_MODIFY
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#define bfin_write_MDMA_S0_Y_MODIFY bfin_write_MDMA0_S0_Y_MODIFY
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#define bfin_write_MDMA_S0_CONFIG bfin_write_MDMA0_S0_CONFIG
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#define bfin_write_MDMA_D0_CONFIG bfin_write_MDMA0_D0_CONFIG
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#define bfin_read_MDMA_S0_CONFIG bfin_read_MDMA0_S0_CONFIG
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#define bfin_read_MDMA_D0_IRQ_STATUS bfin_read_MDMA0_D0_IRQ_STATUS
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#define bfin_write_MDMA_S0_IRQ_STATUS bfin_write_MDMA0_S0_IRQ_STATUS
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/* DPMC*/
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#define bfin_read_STOPCK_OFF() bfin_read_STOPCK()
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#define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val)
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@ -1247,6 +1247,65 @@
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#define bfin_write_MDMA1_S1_CURR_X_COUNT(val) bfin_write16(MDMA1_S1_CURR_X_COUNT, val)
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#define bfin_read_MDMA1_S1_CURR_Y_COUNT() bfin_read16(MDMA1_S1_CURR_Y_COUNT)
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#define bfin_write_MDMA1_S1_CURR_Y_COUNT(val) bfin_write16(MDMA1_S1_CURR_Y_COUNT, val)
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#define bfin_read_MDMA_S0_CONFIG() bfin_read_MDMA0_S0_CONFIG()
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#define bfin_write_MDMA_S0_CONFIG(val) bfin_write_MDMA0_S0_CONFIG(val)
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#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read_MDMA0_S0_IRQ_STATUS()
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#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write_MDMA0_S0_IRQ_STATUS(val)
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#define bfin_read_MDMA_S0_X_MODIFY() bfin_read_MDMA0_S0_X_MODIFY()
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#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write_MDMA0_S0_X_MODIFY(val)
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#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read_MDMA0_S0_Y_MODIFY()
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#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write_MDMA0_S0_Y_MODIFY(val)
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#define bfin_read_MDMA_S0_X_COUNT() bfin_read_MDMA0_S0_X_COUNT()
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#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write_MDMA0_S0_X_COUNT(val)
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#define bfin_read_MDMA_S0_Y_COUNT() bfin_read_MDMA0_S0_Y_COUNT()
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#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write_MDMA0_S0_Y_COUNT(val)
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#define bfin_read_MDMA_S0_START_ADDR() bfin_read_MDMA0_S0_START_ADDR()
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#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write_MDMA0_S0_START_ADDR(val)
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#define bfin_read_MDMA_D0_CONFIG() bfin_read_MDMA0_D0_CONFIG()
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#define bfin_write_MDMA_D0_CONFIG(val) bfin_write_MDMA0_D0_CONFIG(val)
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#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read_MDMA0_D0_IRQ_STATUS()
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#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write_MDMA0_D0_IRQ_STATUS(val)
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#define bfin_read_MDMA_D0_X_MODIFY() bfin_read_MDMA0_D0_X_MODIFY()
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#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write_MDMA0_D0_X_MODIFY(val)
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#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read_MDMA0_D0_Y_MODIFY()
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#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write_MDMA0_D0_Y_MODIFY(val)
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#define bfin_read_MDMA_D0_X_COUNT() bfin_read_MDMA0_D0_X_COUNT()
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#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write_MDMA0_D0_X_COUNT(val)
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#define bfin_read_MDMA_D0_Y_COUNT() bfin_read_MDMA0_D0_Y_COUNT()
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#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write_MDMA0_D0_Y_COUNT(val)
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#define bfin_read_MDMA_D0_START_ADDR() bfin_read_MDMA0_D0_START_ADDR()
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#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write_MDMA0_D0_START_ADDR(val)
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#define bfin_read_MDMA_S1_CONFIG() bfin_read_MDMA0_S1_CONFIG()
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#define bfin_write_MDMA_S1_CONFIG(val) bfin_write_MDMA0_S1_CONFIG(val)
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#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read_MDMA0_S1_IRQ_STATUS()
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#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write_MDMA0_S1_IRQ_STATUS(val)
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#define bfin_read_MDMA_S1_X_MODIFY() bfin_read_MDMA0_S1_X_MODIFY()
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#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write_MDMA0_S1_X_MODIFY(val)
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#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read_MDMA0_S1_Y_MODIFY()
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#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write_MDMA0_S1_Y_MODIFY(val)
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#define bfin_read_MDMA_S1_X_COUNT() bfin_read_MDMA0_S1_X_COUNT()
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#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write_MDMA0_S1_X_COUNT(val)
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#define bfin_read_MDMA_S1_Y_COUNT() bfin_read_MDMA0_S1_Y_COUNT()
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#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write_MDMA0_S1_Y_COUNT(val)
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#define bfin_read_MDMA_S1_START_ADDR() bfin_read_MDMA0_S1_START_ADDR()
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#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write_MDMA0_S1_START_ADDR(val)
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#define bfin_read_MDMA_D1_CONFIG() bfin_read_MDMA0_D1_CONFIG()
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#define bfin_write_MDMA_D1_CONFIG(val) bfin_write_MDMA0_D1_CONFIG(val)
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#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read_MDMA0_D1_IRQ_STATUS()
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#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write_MDMA0_D1_IRQ_STATUS(val)
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#define bfin_read_MDMA_D1_X_MODIFY() bfin_read_MDMA0_D1_X_MODIFY()
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#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write_MDMA0_D1_X_MODIFY(val)
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#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read_MDMA0_D1_Y_MODIFY()
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#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write_MDMA0_D1_Y_MODIFY(val)
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#define bfin_read_MDMA_D1_X_COUNT() bfin_read_MDMA0_D1_X_COUNT()
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#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write_MDMA0_D1_X_COUNT(val)
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#define bfin_read_MDMA_D1_Y_COUNT() bfin_read_MDMA0_D1_Y_COUNT()
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#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write_MDMA0_D1_Y_COUNT(val)
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#define bfin_read_MDMA_D1_START_ADDR() bfin_read_MDMA0_D1_START_ADDR()
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#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write_MDMA0_D1_START_ADDR(val)
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#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
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#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val)
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#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
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@ -412,6 +412,62 @@
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#define MDMA0_S1_CURR_X_COUNT 0xFFC00EF0 /* MemDMA0 Stream 1 Source Current X Count Register */
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#define MDMA0_S1_CURR_Y_COUNT 0xFFC00EF8 /* MemDMA0 Stream 1 Source Current Y Count Register */
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#define MDMA_D0_NEXT_DESC_PTR MDMA0_D0_NEXT_DESC_PTR
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#define MDMA_D0_START_ADDR MDMA0_D0_START_ADDR
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#define MDMA_D0_CONFIG MDMA0_D0_CONFIG
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#define MDMA_D0_X_COUNT MDMA0_D0_X_COUNT
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#define MDMA_D0_X_MODIFY MDMA0_D0_X_MODIFY
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#define MDMA_D0_Y_COUNT MDMA0_D0_Y_COUNT
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#define MDMA_D0_Y_MODIFY MDMA0_D0_Y_MODIFY
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#define MDMA_D0_CURR_DESC_PTR MDMA0_D0_CURR_DESC_PTR
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#define MDMA_D0_CURR_ADDR MDMA0_D0_CURR_ADDR
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#define MDMA_D0_IRQ_STATUS MDMA0_D0_IRQ_STATUS
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#define MDMA_D0_PERIPHERAL_MAP MDMA0_D0_PERIPHERAL_MAP
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#define MDMA_D0_CURR_X_COUNT MDMA0_D0_CURR_X_COUNT
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#define MDMA_D0_CURR_Y_COUNT MDMA0_D0_CURR_Y_COUNT
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#define MDMA_S0_NEXT_DESC_PTR MDMA0_S0_NEXT_DESC_PTR
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#define MDMA_S0_START_ADDR MDMA0_S0_START_ADDR
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#define MDMA_S0_CONFIG MDMA0_S0_CONFIG
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#define MDMA_S0_X_COUNT MDMA0_S0_X_COUNT
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#define MDMA_S0_X_MODIFY MDMA0_S0_X_MODIFY
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#define MDMA_S0_Y_COUNT MDMA0_S0_Y_COUNT
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#define MDMA_S0_Y_MODIFY MDMA0_S0_Y_MODIFY
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#define MDMA_S0_CURR_DESC_PTR MDMA0_S0_CURR_DESC_PTR
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#define MDMA_S0_CURR_ADDR MDMA0_S0_CURR_ADDR
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#define MDMA_S0_IRQ_STATUS MDMA0_S0_IRQ_STATUS
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#define MDMA_S0_PERIPHERAL_MAP MDMA0_S0_PERIPHERAL_MAP
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#define MDMA_S0_CURR_X_COUNT MDMA0_S0_CURR_X_COUNT
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#define MDMA_S0_CURR_Y_COUNT MDMA0_S0_CURR_Y_COUNT
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#define MDMA_D1_NEXT_DESC_PTR MDMA0_D1_NEXT_DESC_PTR
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#define MDMA_D1_START_ADDR MDMA0_D1_START_ADDR
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#define MDMA_D1_CONFIG MDMA0_D1_CONFIG
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#define MDMA_D1_X_COUNT MDMA0_D1_X_COUNT
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#define MDMA_D1_X_MODIFY MDMA0_D1_X_MODIFY
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#define MDMA_D1_Y_COUNT MDMA0_D1_Y_COUNT
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#define MDMA_D1_Y_MODIFY MDMA0_D1_Y_MODIFY
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#define MDMA_D1_CURR_DESC_PTR MDMA0_D1_CURR_DESC_PTR
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#define MDMA_D1_CURR_ADDR MDMA0_D1_CURR_ADDR
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#define MDMA_D1_IRQ_STATUS MDMA0_D1_IRQ_STATUS
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#define MDMA_D1_PERIPHERAL_MAP MDMA0_D1_PERIPHERAL_MAP
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#define MDMA_D1_CURR_X_COUNT MDMA0_D1_CURR_X_COUNT
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#define MDMA_D1_CURR_Y_COUNT MDMA0_D1_CURR_Y_COUNT
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#define MDMA_S1_NEXT_DESC_PTR MDMA0_S1_NEXT_DESC_PTR
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#define MDMA_S1_START_ADDR MDMA0_S1_START_ADDR
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#define MDMA_S1_CONFIG MDMA0_S1_CONFIG
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#define MDMA_S1_X_COUNT MDMA0_S1_X_COUNT
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#define MDMA_S1_X_MODIFY MDMA0_S1_X_MODIFY
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#define MDMA_S1_Y_COUNT MDMA0_S1_Y_COUNT
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#define MDMA_S1_Y_MODIFY MDMA0_S1_Y_MODIFY
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#define MDMA_S1_CURR_DESC_PTR MDMA0_S1_CURR_DESC_PTR
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#define MDMA_S1_CURR_ADDR MDMA0_S1_CURR_ADDR
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#define MDMA_S1_IRQ_STATUS MDMA0_S1_IRQ_STATUS
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#define MDMA_S1_PERIPHERAL_MAP MDMA0_S1_PERIPHERAL_MAP
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#define MDMA_S1_CURR_X_COUNT MDMA0_S1_CURR_X_COUNT
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#define MDMA_S1_CURR_Y_COUNT MDMA0_S1_CURR_Y_COUNT
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/* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */
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#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
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#define bfin_read_MDMA_D0_START_ADDR() bfin_read_MDMA1_D0_START_ADDR()
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#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write_MDMA1_D0_START_ADDR(val)
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#define bfin_read_MDMA_S1_CONFIG() bfin_read_MDMA1_S1_CONFIG()
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#define bfin_write_MDMA_S1_CONFIG(val) bfin_write_MDMA1_S1_CONFIG(val)
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#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read_MDMA1_S1_IRQ_STATUS()
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#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write_MDMA1_S1_IRQ_STATUS(val)
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#define bfin_read_MDMA_S1_X_MODIFY() bfin_read_MDMA1_S1_X_MODIFY()
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#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write_MDMA1_S1_X_MODIFY(val)
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#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read_MDMA1_S1_Y_MODIFY()
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#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write_MDMA1_S1_Y_MODIFY(val)
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#define bfin_read_MDMA_S1_X_COUNT() bfin_read_MDMA1_S1_X_COUNT()
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#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write_MDMA1_S1_X_COUNT(val)
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#define bfin_read_MDMA_S1_Y_COUNT() bfin_read_MDMA1_S1_Y_COUNT()
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#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write_MDMA1_S1_Y_COUNT(val)
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#define bfin_read_MDMA_S1_START_ADDR() bfin_read_MDMA1_S1_START_ADDR()
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#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write_MDMA1_S1_START_ADDR(val)
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#define bfin_read_MDMA_D1_CONFIG() bfin_read_MDMA1_D1_CONFIG()
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#define bfin_write_MDMA_D1_CONFIG(val) bfin_write_MDMA1_D1_CONFIG(val)
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#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read_MDMA1_D1_IRQ_STATUS()
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#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write_MDMA1_D1_IRQ_STATUS(val)
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#define bfin_read_MDMA_D1_X_MODIFY() bfin_read_MDMA1_D1_X_MODIFY()
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#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write_MDMA1_D1_X_MODIFY(val)
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#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read_MDMA1_D1_Y_MODIFY()
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#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write_MDMA1_D1_Y_MODIFY(val)
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#define bfin_read_MDMA_D1_X_COUNT() bfin_read_MDMA1_D1_X_COUNT()
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#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write_MDMA1_D1_X_COUNT(val)
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#define bfin_read_MDMA_D1_Y_COUNT() bfin_read_MDMA1_D1_Y_COUNT()
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#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write_MDMA1_D1_Y_COUNT(val)
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#define bfin_read_MDMA_D1_START_ADDR() bfin_read_MDMA1_D1_START_ADDR()
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#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write_MDMA1_D1_START_ADDR(val)
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/* These need to be last due to the cdef/linux inter-dependencies */
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#include <asm/irq.h>
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#define MDMA2_S1_IRQ_STATUS 0xFFC00FE8 /*MemDMA2 Stream 1 Source Interrupt/Status Register */
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#define MDMA2_S1_PERIPHERAL_MAP 0xFFC00FEC /*MemDMA2 Stream 1 Source Peripheral Map register */
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#define MDMA_D0_NEXT_DESC_PTR MDMA1_D0_NEXT_DESC_PTR
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#define MDMA_D0_START_ADDR MDMA1_D0_START_ADDR
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#define MDMA_D0_CONFIG MDMA1_D0_CONFIG
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#define MDMA_D0_X_COUNT MDMA1_D0_X_COUNT
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#define MDMA_D0_X_MODIFY MDMA1_D0_X_MODIFY
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#define MDMA_D0_Y_COUNT MDMA1_D0_Y_COUNT
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#define MDMA_D0_Y_MODIFY MDMA1_D0_Y_MODIFY
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#define MDMA_D0_CURR_DESC_PTR MDMA1_D0_CURR_DESC_PTR
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#define MDMA_D0_CURR_ADDR MDMA1_D0_CURR_ADDR
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#define MDMA_D0_IRQ_STATUS MDMA1_D0_IRQ_STATUS
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#define MDMA_D0_PERIPHERAL_MAP MDMA1_D0_PERIPHERAL_MAP
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#define MDMA_D0_CURR_X_COUNT MDMA1_D0_CURR_X_COUNT
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#define MDMA_D0_CURR_Y_COUNT MDMA1_D0_CURR_Y_COUNT
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#define MDMA_S0_NEXT_DESC_PTR MDMA1_S0_NEXT_DESC_PTR
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#define MDMA_S0_START_ADDR MDMA1_S0_START_ADDR
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#define MDMA_S0_CONFIG MDMA1_S0_CONFIG
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#define MDMA_S0_X_COUNT MDMA1_S0_X_COUNT
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#define MDMA_S0_X_MODIFY MDMA1_S0_X_MODIFY
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#define MDMA_S0_Y_COUNT MDMA1_S0_Y_COUNT
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#define MDMA_S0_Y_MODIFY MDMA1_S0_Y_MODIFY
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#define MDMA_S0_CURR_DESC_PTR MDMA1_S0_CURR_DESC_PTR
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#define MDMA_S0_CURR_ADDR MDMA1_S0_CURR_ADDR
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#define MDMA_S0_IRQ_STATUS MDMA1_S0_IRQ_STATUS
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#define MDMA_S0_PERIPHERAL_MAP MDMA1_S0_PERIPHERAL_MAP
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#define MDMA_S0_CURR_X_COUNT MDMA1_S0_CURR_X_COUNT
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#define MDMA_S0_CURR_Y_COUNT MDMA1_S0_CURR_Y_COUNT
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#define MDMA_D1_NEXT_DESC_PTR MDMA1_D1_NEXT_DESC_PTR
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#define MDMA_D1_START_ADDR MDMA1_D1_START_ADDR
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#define MDMA_D1_CONFIG MDMA1_D1_CONFIG
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#define MDMA_D1_X_COUNT MDMA1_D1_X_COUNT
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#define MDMA_D1_X_MODIFY MDMA1_D1_X_MODIFY
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#define MDMA_D1_Y_COUNT MDMA1_D1_Y_COUNT
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#define MDMA_D1_Y_MODIFY MDMA1_D1_Y_MODIFY
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#define MDMA_D1_CURR_DESC_PTR MDMA1_D1_CURR_DESC_PTR
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#define MDMA_D1_CURR_ADDR MDMA1_D1_CURR_ADDR
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#define MDMA_D1_IRQ_STATUS MDMA1_D1_IRQ_STATUS
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#define MDMA_D1_PERIPHERAL_MAP MDMA1_D1_PERIPHERAL_MAP
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#define MDMA_D1_CURR_X_COUNT MDMA1_D1_CURR_X_COUNT
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#define MDMA_D1_CURR_Y_COUNT MDMA1_D1_CURR_Y_COUNT
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#define MDMA_S1_NEXT_DESC_PTR MDMA1_S1_NEXT_DESC_PTR
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#define MDMA_S1_START_ADDR MDMA1_S1_START_ADDR
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#define MDMA_S1_CONFIG MDMA1_S1_CONFIG
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#define MDMA_S1_X_COUNT MDMA1_S1_X_COUNT
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#define MDMA_S1_X_MODIFY MDMA1_S1_X_MODIFY
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#define MDMA_S1_Y_COUNT MDMA1_S1_Y_COUNT
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#define MDMA_S1_Y_MODIFY MDMA1_S1_Y_MODIFY
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#define MDMA_S1_CURR_DESC_PTR MDMA1_S1_CURR_DESC_PTR
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#define MDMA_S1_CURR_ADDR MDMA1_S1_CURR_ADDR
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#define MDMA_S1_IRQ_STATUS MDMA1_S1_IRQ_STATUS
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#define MDMA_S1_PERIPHERAL_MAP MDMA1_S1_PERIPHERAL_MAP
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#define MDMA_S1_CURR_X_COUNT MDMA1_S1_CURR_X_COUNT
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#define MDMA_S1_CURR_Y_COUNT MDMA1_S1_CURR_Y_COUNT
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|
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/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */
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#define IMDMA_D0_CONFIG 0xFFC01808 /*IMDMA Stream 0 Destination Configuration */
|
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#define IMDMA_D0_NEXT_DESC_PTR 0xFFC01800 /*IMDMA Stream 0 Destination Next Descriptor Ptr Reg */
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|
|
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Reference in New Issue