[PATCH] shpchp: fix improper write to Command Completion Detect bit
Current SHPCHP driver writes a '0' to the Command Completion Detect bit to clear the Command Complete Interrupt Pending. But according to the SHPC spec (See 4.7.3.1 System Interrupts), SHPCHP driver must write '1'. This patch fixes this bug. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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1 changed files with 2 additions and 2 deletions
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@ -1058,11 +1058,11 @@ static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs)
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if (intr_loc & 0x0001) {
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/*
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* Command Complete Interrupt Pending
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* RO only - clear by writing 0 to the Command Completion
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* RO only - clear by writing 1 to the Command Completion
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* Detect bit in Controller SERR-INT register
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*/
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temp_dword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
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temp_dword &= 0xfffeffff;
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temp_dword &= 0xfffdffff;
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writel(temp_dword, php_ctlr->creg + SERR_INTR_ENABLE);
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wake_up_interruptible(&ctrl->queue);
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}
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