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Blackfin: increase NR_IRQS beyond NR on-chip IRQs 

This makes room for off-chip IRQ controllers.

Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Michael Hennerich 2010-01-19 14:45:38 +00:00 committed by Mike Frysinger
parent 5e8d3210b5
commit f3dec78333
9 changed files with 18 additions and 8 deletions
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3
arch/blackfin/include/asm/irq.h
View File

@ -12,6 +12,9 @@
#include <linux/irqflags.h>
/* IRQs that may be used by external irq_chip controllers */
#define NR_SPARE_IRQS 32
#include <mach/anomaly.h>
/* SYS_IRQS and NR_IRQS are defined in <mach-bf5xx/irq.h> */

3
arch/blackfin/mach-bf518/include/mach/irq.h
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@ -151,7 +151,8 @@
#define GPIO_IRQ_BASE IRQ_PF0
#define NR_IRQS (IRQ_PH15 + 1)
#define NR_MACH_IRQS (IRQ_PH15 + 1)
#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
#define IVG7 7
#define IVG8 8

3
arch/blackfin/mach-bf527/include/mach/irq.h
View File

@ -151,7 +151,8 @@
#define GPIO_IRQ_BASE IRQ_PF0
#define NR_IRQS (IRQ_PH15+1)
#define NR_MACH_IRQS (IRQ_PH15 + 1)
#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
#define IVG7 7
#define IVG8 8

3
arch/blackfin/mach-bf533/include/mach/irq.h
View File

@ -104,7 +104,8 @@ Core Emulation **
#define GPIO_IRQ_BASE IRQ_PF0
#define NR_IRQS (IRQ_PF15+1)
#define NR_MACH_IRQS (IRQ_PF15 + 1)
#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
#define IVG7 7
#define IVG8 8

3
arch/blackfin/mach-bf537/include/mach/irq.h
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@ -134,7 +134,8 @@
#define GPIO_IRQ_BASE IRQ_PF0
#define NR_IRQS (IRQ_PH15+1)
#define NR_MACH_IRQS (IRQ_PH15 + 1)
#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
#define IVG7 7
#define IVG8 8

3
arch/blackfin/mach-bf538/include/mach/irq.h
View File

@ -110,7 +110,8 @@
#define GPIO_IRQ_BASE IRQ_PF0
#define NR_IRQS (IRQ_PF15+1)
#define NR_MACH_IRQS (IRQ_PF15 + 1)
#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
#define IVG7 7
#define IVG8 8

3
arch/blackfin/mach-bf548/include/mach/irq.h
View File

@ -317,7 +317,8 @@ Events (highest priority) EMU 0
#define GPIO_IRQ_BASE IRQ_PA0
#define NR_IRQS (IRQ_PJ15+1)
#define NR_MACH_IRQS (IRQ_PJ15 + 1)
#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
/* For compatibility reasons with existing code */

3
arch/blackfin/mach-bf561/include/mach/irq.h
View File

@ -265,7 +265,8 @@
#define GPIO_IRQ_BASE IRQ_PF0
#define NR_IRQS (IRQ_PF47 + 1)
#define NR_MACH_IRQS (IRQ_PF47 + 1)
#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
#define IVG7 7
#define IVG8 8

2
arch/blackfin/mach-common/ints-priority.c
View File

@ -1114,7 +1114,7 @@ int __init init_arch_irq(void)
#endif
/* if configured as edge, then will be changed to do_edge_IRQ */
for (irq = GPIO_IRQ_BASE; irq < NR_IRQS; irq++)
for (irq = GPIO_IRQ_BASE; irq < NR_MACH_IRQS; irq++)
set_irq_chip_and_handler(irq, &bfin_gpio_irqchip,
handle_level_irq);