OMAP: DMA: Convert DMA library into platform driver
Convert DMA library into DMA platform driver and make use of platform data provided by hwmod data base for OMAP2+ onwards. For OMAP1 processors, the DMA driver in mach-omap uses resource structures for getting platform data. Thanks to Tony Lindgren <tony@atomide.com> for fixing various omap1 issues and testing the same on OSK5912 board. Signed-off-by: G, Manjunath Kondaiah <manjugk@ti.com> Tested-by: Kevin Hilman <khilman@deeprootsystems.com> Acked-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
G, Manjunath Kondaiah
Tony Lindgren
parent
59de3cf1ce
commit
f31cc9622d
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@ -3,7 +3,7 @@
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#
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# Common support
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obj-y := io.o id.o sram.o irq.o mux.o flash.o serial.o devices.o
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obj-y := io.o id.o sram.o irq.o mux.o flash.o serial.o devices.o dma.o
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obj-y += clock.o clock_data.o opp_data.o
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obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
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@ -30,6 +30,57 @@
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#include <plat/irqs.h>
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#define OMAP1_DMA_BASE (0xfffed800)
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#define OMAP1_LOGICAL_DMA_CH_COUNT 17
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#define OMAP1_DMA_STRIDE 0x40
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static u32 errata;
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static u32 enable_1510_mode;
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static u8 dma_stride;
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static enum omap_reg_offsets dma_common_ch_start, dma_common_ch_end;
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static u16 reg_map[] = {
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[GCR] = 0x400,
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[GSCR] = 0x404,
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[GRST1] = 0x408,
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[HW_ID] = 0x442,
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[PCH2_ID] = 0x444,
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[PCH0_ID] = 0x446,
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[PCH1_ID] = 0x448,
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[PCHG_ID] = 0x44a,
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[PCHD_ID] = 0x44c,
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[CAPS_0] = 0x44e,
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[CAPS_1] = 0x452,
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[CAPS_2] = 0x456,
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[CAPS_3] = 0x458,
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[CAPS_4] = 0x45a,
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[PCH2_SR] = 0x460,
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[PCH0_SR] = 0x480,
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[PCH1_SR] = 0x482,
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[PCHD_SR] = 0x4c0,
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/* Common Registers */
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[CSDP] = 0x00,
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[CCR] = 0x02,
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[CICR] = 0x04,
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[CSR] = 0x06,
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[CEN] = 0x10,
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[CFN] = 0x12,
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[CSFI] = 0x14,
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[CSEI] = 0x16,
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[CPC] = 0x18, /* 15xx only */
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[CSAC] = 0x18,
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[CDAC] = 0x1a,
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[CDEI] = 0x1c,
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[CDFI] = 0x1e,
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[CLNK_CTRL] = 0x28,
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/* Channel specific register offsets */
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[CSSA] = 0x08,
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[CDSA] = 0x0c,
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[COLOR] = 0x20,
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[CCR2] = 0x24,
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[LCH_CTRL] = 0x2a,
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};
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static struct resource res[] __initdata = {
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[0] = {
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@ -67,6 +118,7 @@ static struct resource res[] __initdata = {
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.start = INT_DMA_CH5,
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.flags = IORESOURCE_IRQ,
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},
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/* Handled in lcd_dma.c */
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[7] = {
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.name = "6",
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.start = INT_1610_DMA_CH6,
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@ -125,9 +177,100 @@ static struct resource res[] __initdata = {
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},
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};
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static void __iomem *dma_base;
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static inline void dma_write(u32 val, int reg, int lch)
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{
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u8 stride;
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u32 offset;
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stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
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offset = reg_map[reg] + (stride * lch);
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__raw_writew(val, dma_base + offset);
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if ((reg > CLNK_CTRL && reg < CCEN) ||
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(reg > PCHD_ID && reg < CAPS_2)) {
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u32 offset2 = reg_map[reg] + 2 + (stride * lch);
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__raw_writew(val >> 16, dma_base + offset2);
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}
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}
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static inline u32 dma_read(int reg, int lch)
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{
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u8 stride;
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u32 offset, val;
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stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
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offset = reg_map[reg] + (stride * lch);
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val = __raw_readw(dma_base + offset);
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if ((reg > CLNK_CTRL && reg < CCEN) ||
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(reg > PCHD_ID && reg < CAPS_2)) {
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u16 upper;
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u32 offset2 = reg_map[reg] + 2 + (stride * lch);
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upper = __raw_readw(dma_base + offset2);
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val |= (upper << 16);
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}
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return val;
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}
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static void omap1_clear_lch_regs(int lch)
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{
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int i = dma_common_ch_start;
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for (; i <= dma_common_ch_end; i += 1)
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dma_write(0, i, lch);
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}
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static void omap1_clear_dma(int lch)
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{
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u32 l;
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l = dma_read(CCR, lch);
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l &= ~OMAP_DMA_CCR_EN;
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dma_write(l, CCR, lch);
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/* Clear pending interrupts */
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l = dma_read(CSR, lch);
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}
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static void omap1_show_dma_caps(void)
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{
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if (enable_1510_mode) {
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printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
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} else {
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u16 w;
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printk(KERN_INFO "OMAP DMA hardware version %d\n",
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dma_read(HW_ID, 0));
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printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
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dma_read(CAPS_0, 0), dma_read(CAPS_1, 0),
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dma_read(CAPS_2, 0), dma_read(CAPS_3, 0),
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dma_read(CAPS_4, 0));
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/* Disable OMAP 3.0/3.1 compatibility mode. */
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w = dma_read(GSCR, 0);
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w |= 1 << 3;
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dma_write(w, GSCR, 0);
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}
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return;
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}
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static u32 configure_dma_errata(void)
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{
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/*
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* Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is
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* read before the DMA controller finished disabling the channel.
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*/
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if (!cpu_is_omap15xx())
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SET_DMA_ERRATA(DMA_ERRATA_3_3);
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return errata;
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}
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static int __init omap1_system_dma_init(void)
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{
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struct omap_system_dma_plat_info *p;
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struct omap_dma_dev_attr *d;
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struct platform_device *pdev;
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int ret;
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@ -138,6 +281,12 @@ static int __init omap1_system_dma_init(void)
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return -ENOMEM;
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}
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dma_base = ioremap(res[0].start, resource_size(&res[0]));
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if (!dma_base) {
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pr_err("%s: Unable to ioremap\n", __func__);
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return -ENODEV;
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}
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ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res));
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if (ret) {
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dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
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@ -153,22 +302,84 @@ static int __init omap1_system_dma_init(void)
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goto exit_device_put;
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}
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d = kzalloc(sizeof(struct omap_dma_dev_attr), GFP_KERNEL);
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if (!d) {
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dev_err(&pdev->dev, "%s: Unable to allocate 'd' for %s\n",
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__func__, pdev->name);
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ret = -ENOMEM;
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goto exit_release_p;
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}
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d->lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
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/* Valid attributes for omap1 plus processors */
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if (cpu_is_omap15xx())
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d->dev_caps = ENABLE_1510_MODE;
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enable_1510_mode = d->dev_caps & ENABLE_1510_MODE;
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d->dev_caps |= SRC_PORT;
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d->dev_caps |= DST_PORT;
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d->dev_caps |= SRC_INDEX;
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d->dev_caps |= DST_INDEX;
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d->dev_caps |= IS_BURST_ONLY4;
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d->dev_caps |= CLEAR_CSR_ON_READ;
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d->dev_caps |= IS_WORD_16;
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d->chan = kzalloc(sizeof(struct omap_dma_lch) *
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(d->lch_count), GFP_KERNEL);
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if (!d->chan) {
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dev_err(&pdev->dev, "%s: Memory allocation failed"
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"for d->chan!!!\n", __func__);
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goto exit_release_d;
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}
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if (cpu_is_omap15xx())
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d->chan_count = 9;
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else if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
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if (!(d->dev_caps & ENABLE_1510_MODE))
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d->chan_count = 16;
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else
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d->chan_count = 9;
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}
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p->dma_attr = d;
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p->show_dma_caps = omap1_show_dma_caps;
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p->clear_lch_regs = omap1_clear_lch_regs;
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p->clear_dma = omap1_clear_dma;
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p->dma_write = dma_write;
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p->dma_read = dma_read;
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p->disable_irq_lch = NULL;
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p->errata = configure_dma_errata();
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ret = platform_device_add_data(pdev, p, sizeof(*p));
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if (ret) {
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dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
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__func__, pdev->name, pdev->id);
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goto exit_device_put;
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goto exit_release_chan;
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}
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ret = platform_device_add(pdev);
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if (ret) {
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dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
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__func__, pdev->name, pdev->id);
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goto exit_device_put;
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goto exit_release_chan;
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}
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dma_stride = OMAP1_DMA_STRIDE;
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dma_common_ch_start = CPC;
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dma_common_ch_end = COLOR;
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return ret;
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exit_release_chan:
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kfree(d->chan);
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exit_release_d:
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kfree(d);
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exit_release_p:
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kfree(p);
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exit_device_put:
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platform_device_put(pdev);
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exit_device_del:
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@ -4,7 +4,7 @@
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# Common support
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obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o pm.o \
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common.o gpio.o
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common.o gpio.o dma.o
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omap-2-3-common = irq.o sdrc.o prm2xxx_3xxx.o
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hwmod-common = omap_hwmod.o \
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@ -32,6 +32,61 @@
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#include <plat/omap_device.h>
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#include <plat/dma.h>
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#define OMAP2_DMA_STRIDE 0x60
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static u32 errata;
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static u8 dma_stride;
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static struct omap_dma_dev_attr *d;
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static enum omap_reg_offsets dma_common_ch_start, dma_common_ch_end;
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static u16 reg_map[] = {
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[REVISION] = 0x00,
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[GCR] = 0x78,
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[IRQSTATUS_L0] = 0x08,
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[IRQSTATUS_L1] = 0x0c,
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[IRQSTATUS_L2] = 0x10,
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[IRQSTATUS_L3] = 0x14,
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[IRQENABLE_L0] = 0x18,
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[IRQENABLE_L1] = 0x1c,
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[IRQENABLE_L2] = 0x20,
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[IRQENABLE_L3] = 0x24,
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[SYSSTATUS] = 0x28,
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[OCP_SYSCONFIG] = 0x2c,
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[CAPS_0] = 0x64,
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[CAPS_2] = 0x6c,
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[CAPS_3] = 0x70,
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[CAPS_4] = 0x74,
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/* Common register offsets */
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[CCR] = 0x80,
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[CLNK_CTRL] = 0x84,
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[CICR] = 0x88,
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[CSR] = 0x8c,
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[CSDP] = 0x90,
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[CEN] = 0x94,
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[CFN] = 0x98,
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[CSEI] = 0xa4,
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[CSFI] = 0xa8,
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[CDEI] = 0xac,
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[CDFI] = 0xb0,
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[CSAC] = 0xb4,
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[CDAC] = 0xb8,
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/* Channel specific register offsets */
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[CSSA] = 0x9c,
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[CDSA] = 0xa0,
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[CCEN] = 0xbc,
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[CCFN] = 0xc0,
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[COLOR] = 0xc4,
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/* OMAP4 specific registers */
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[CDP] = 0xd0,
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[CNDP] = 0xd4,
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[CCDN] = 0xd8,
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};
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static struct omap_device_pm_latency omap2_dma_latency[] = {
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{
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.deactivate_func = omap_device_idle_hwmods,
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@ -40,13 +95,151 @@ static struct omap_device_pm_latency omap2_dma_latency[] = {
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},
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};
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static void __iomem *dma_base;
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static inline void dma_write(u32 val, int reg, int lch)
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{
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u8 stride;
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u32 offset;
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stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
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offset = reg_map[reg] + (stride * lch);
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__raw_writel(val, dma_base + offset);
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}
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static inline u32 dma_read(int reg, int lch)
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{
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u8 stride;
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u32 offset, val;
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stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
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offset = reg_map[reg] + (stride * lch);
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val = __raw_readl(dma_base + offset);
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return val;
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}
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static inline void omap2_disable_irq_lch(int lch)
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{
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u32 val;
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val = dma_read(IRQENABLE_L0, lch);
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val &= ~(1 << lch);
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dma_write(val, IRQENABLE_L0, lch);
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}
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static void omap2_clear_dma(int lch)
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{
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int i = dma_common_ch_start;
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for (; i <= dma_common_ch_end; i += 1)
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dma_write(0, i, lch);
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}
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static void omap2_show_dma_caps(void)
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{
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u8 revision = dma_read(REVISION, 0) & 0xff;
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printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
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revision >> 4, revision & 0xf);
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return;
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}
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static u32 configure_dma_errata(void)
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{
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/*
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* Errata applicable for OMAP2430ES1.0 and all omap2420
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*
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* I.
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* Erratum ID: Not Available
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* Inter Frame DMA buffering issue DMA will wrongly
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* buffer elements if packing and bursting is enabled. This might
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* result in data gets stalled in FIFO at the end of the block.
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* Workaround: DMA channels must have BUFFERING_DISABLED bit set to
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* guarantee no data will stay in the DMA FIFO in case inter frame
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* buffering occurs
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*
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* II.
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* Erratum ID: Not Available
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* DMA may hang when several channels are used in parallel
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* In the following configuration, DMA channel hanging can occur:
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* a. Channel i, hardware synchronized, is enabled
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* b. Another channel (Channel x), software synchronized, is enabled.
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* c. Channel i is disabled before end of transfer
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* d. Channel i is reenabled.
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* e. Steps 1 to 4 are repeated a certain number of times.
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* f. A third channel (Channel y), software synchronized, is enabled.
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* Channel x and Channel y may hang immediately after step 'f'.
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* Workaround:
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* For any channel used - make sure NextLCH_ID is set to the value j.
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*/
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if (cpu_is_omap2420() || (cpu_is_omap2430() &&
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(omap_type() == OMAP2430_REV_ES1_0))) {
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SET_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING);
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SET_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS);
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}
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/*
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* Erratum ID: i378: OMAP2+: sDMA Channel is not disabled
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* after a transaction error.
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* Workaround: SW should explicitely disable the channel.
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*/
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if (cpu_class_is_omap2())
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SET_DMA_ERRATA(DMA_ERRATA_i378);
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/*
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* Erratum ID: i541: sDMA FIFO draining does not finish
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* If sDMA channel is disabled on the fly, sDMA enters standby even
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* through FIFO Drain is still in progress
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* Workaround: Put sDMA in NoStandby more before a logical channel is
|
||||
* disabled, then put it back to SmartStandby right after the channel
|
||||
* finishes FIFO draining.
|
||||
*/
|
||||
if (cpu_is_omap34xx())
|
||||
SET_DMA_ERRATA(DMA_ERRATA_i541);
|
||||
|
||||
/*
|
||||
* Erratum ID: i88 : Special programming model needed to disable DMA
|
||||
* before end of block.
|
||||
* Workaround: software must ensure that the DMA is configured in No
|
||||
* Standby mode(DMAx_OCP_SYSCONFIG.MIDLEMODE = "01")
|
||||
*/
|
||||
if (omap_type() == OMAP3430_REV_ES1_0)
|
||||
SET_DMA_ERRATA(DMA_ERRATA_i88);
|
||||
|
||||
/*
|
||||
* Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is
|
||||
* read before the DMA controller finished disabling the channel.
|
||||
*/
|
||||
SET_DMA_ERRATA(DMA_ERRATA_3_3);
|
||||
|
||||
/*
|
||||
* Erratum ID: Not Available
|
||||
* A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared
|
||||
* after secure sram context save and restore.
|
||||
* Work around: Hence we need to manually clear those IRQs to avoid
|
||||
* spurious interrupts. This affects only secure devices.
|
||||
*/
|
||||
if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
|
||||
SET_DMA_ERRATA(DMA_ROMCODE_BUG);
|
||||
|
||||
return errata;
|
||||
}
|
||||
|
||||
/* One time initializations */
|
||||
static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
|
||||
{
|
||||
struct omap_device *od;
|
||||
struct omap_system_dma_plat_info *p;
|
||||
struct resource *mem;
|
||||
char *name = "omap_dma_system";
|
||||
|
||||
dma_stride = OMAP2_DMA_STRIDE;
|
||||
dma_common_ch_start = CSDP;
|
||||
if (cpu_is_omap3630() || cpu_is_omap4430())
|
||||
dma_common_ch_end = CCDN;
|
||||
else
|
||||
dma_common_ch_end = CCFN;
|
||||
|
||||
p = kzalloc(sizeof(struct omap_system_dma_plat_info), GFP_KERNEL);
|
||||
if (!p) {
|
||||
pr_err("%s: Unable to allocate pdata for %s:%s\n",
|
||||
|
|
@ -54,6 +247,17 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
|
|||
return -ENOMEM;
|
||||
}
|
||||
|
||||
p->dma_attr = (struct omap_dma_dev_attr *)oh->dev_attr;
|
||||
p->disable_irq_lch = omap2_disable_irq_lch;
|
||||
p->show_dma_caps = omap2_show_dma_caps;
|
||||
p->clear_dma = omap2_clear_dma;
|
||||
p->dma_write = dma_write;
|
||||
p->dma_read = dma_read;
|
||||
|
||||
p->clear_lch_regs = NULL;
|
||||
|
||||
p->errata = configure_dma_errata();
|
||||
|
||||
od = omap_device_build(name, 0, oh, p, sizeof(*p),
|
||||
omap2_dma_latency, ARRAY_SIZE(omap2_dma_latency), 0);
|
||||
kfree(p);
|
||||
|
|
@ -63,6 +267,25 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
|
|||
return IS_ERR(od);
|
||||
}
|
||||
|
||||
mem = platform_get_resource(&od->pdev, IORESOURCE_MEM, 0);
|
||||
if (!mem) {
|
||||
dev_err(&od->pdev.dev, "%s: no mem resource\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
dma_base = ioremap(mem->start, resource_size(mem));
|
||||
if (!dma_base) {
|
||||
dev_err(&od->pdev.dev, "%s: ioremap fail\n", __func__);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
d = oh->dev_attr;
|
||||
d->chan = kzalloc(sizeof(struct omap_dma_lch) *
|
||||
(d->lch_count), GFP_KERNEL);
|
||||
|
||||
if (!d->chan) {
|
||||
dev_err(&od->pdev.dev, "%s: kzalloc fail\n", __func__);
|
||||
return -ENOMEM;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -21,20 +21,16 @@
|
|||
#ifndef __ASM_ARCH_DMA_H
|
||||
#define __ASM_ARCH_DMA_H
|
||||
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
/*
|
||||
* TODO: These dma channel defines should go away once all
|
||||
* the omap drivers hwmod adapted.
|
||||
*/
|
||||
|
||||
/* Move omap4 specific defines to dma-44xx.h */
|
||||
#include "dma-44xx.h"
|
||||
|
||||
/* Hardware registers for omap1 */
|
||||
#define OMAP1_DMA_BASE (0xfffed800)
|
||||
|
||||
/* Hardware registers for omap2 and omap3 */
|
||||
#define OMAP24XX_DMA4_BASE (L4_24XX_BASE + 0x56000)
|
||||
#define OMAP34XX_DMA4_BASE (L4_34XX_BASE + 0x56000)
|
||||
#define OMAP44XX_DMA4_BASE (L4_44XX_BASE + 0x56000)
|
||||
|
||||
#define OMAP1_LOGICAL_DMA_CH_COUNT 17
|
||||
#define OMAP_DMA4_LOGICAL_DMA_CH_COUNT 32 /* REVISIT: Is this 32 + 2? */
|
||||
|
||||
/* DMA channels for omap1 */
|
||||
#define OMAP_DMA_NO_DEVICE 0
|
||||
#define OMAP_DMA_MCSI1_TX 1
|
||||
|
|
@ -302,6 +298,14 @@
|
|||
#define IS_CSSA_32 BIT(0x3)
|
||||
#define IS_CDSA_32 BIT(0x4)
|
||||
#define IS_RW_PRIORITY BIT(0x5)
|
||||
#define ENABLE_1510_MODE BIT(0x6)
|
||||
#define SRC_PORT BIT(0x7)
|
||||
#define DST_PORT BIT(0x8)
|
||||
#define SRC_INDEX BIT(0x9)
|
||||
#define DST_INDEX BIT(0xA)
|
||||
#define IS_BURST_ONLY4 BIT(0xB)
|
||||
#define CLEAR_CSR_ON_READ BIT(0xC)
|
||||
#define IS_WORD_16 BIT(0xD)
|
||||
|
||||
enum omap_reg_offsets {
|
||||
|
||||
|
|
@ -397,9 +401,40 @@ struct omap_dma_channel_params {
|
|||
#endif
|
||||
};
|
||||
|
||||
struct omap_dma_lch {
|
||||
int next_lch;
|
||||
int dev_id;
|
||||
u16 saved_csr;
|
||||
u16 enabled_irqs;
|
||||
const char *dev_name;
|
||||
void (*callback)(int lch, u16 ch_status, void *data);
|
||||
void *data;
|
||||
long flags;
|
||||
/* required for Dynamic chaining */
|
||||
int prev_linked_ch;
|
||||
int next_linked_ch;
|
||||
int state;
|
||||
int chain_id;
|
||||
int status;
|
||||
};
|
||||
|
||||
struct omap_dma_dev_attr {
|
||||
u32 dev_caps;
|
||||
u16 lch_count;
|
||||
u16 chan_count;
|
||||
struct omap_dma_lch *chan;
|
||||
};
|
||||
|
||||
/* System DMA platform data structure */
|
||||
struct omap_system_dma_plat_info {
|
||||
struct omap_dma_dev_attr *dma_attr;
|
||||
u32 errata;
|
||||
void (*disable_irq_lch)(int lch);
|
||||
void (*show_dma_caps)(void);
|
||||
void (*clear_lch_regs)(int lch);
|
||||
void (*clear_dma)(int lch);
|
||||
void (*dma_write)(u32 val, int reg, int lch);
|
||||
u32 (*dma_read)(int reg, int lch);
|
||||
};
|
||||
|
||||
extern void omap_set_dma_priority(int lch, int dst_port, int priority);
|
||||
|
|
|
|||
Reference in New Issue