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[ARM] 4876/1: i.MXC family: Clean up 

From: Juergen Beisert <j.beisert@pengutronix.de>

Clean up current header files from doxygen style comments. There are
probably more such comments left, but we start with these.

Things happend since last review:
 - needless blank lines removed (note by Russell King)
 - re-format comments (note by Ross Wille)

Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de>
Signed-off-by: Ross Wille <wille@freescale.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Robert Schwebel 2008-03-28 10:59:08 +01:00 committed by Russell King
parent 05dda977f2
commit f304fc422d
9 changed files with 61 additions and 161 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

124
include/asm-arm/arch-mxc/board-mx31ads.h
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@ -11,107 +11,77 @@
#ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__
#define __ASM_ARCH_MXC_BOARD_MX31ADS_H__
/*!
* @name PBC Controller parameters
*/
/*! @{ */
/*!
* Base address of PBC controller
*/
/* Base address of PBC controller */
#define PBC_BASE_ADDRESS IO_ADDRESS(CS4_BASE_ADDR)
/* Offsets for the PBC Controller register */
/*!
* PBC Board status register offset
*/
/* PBC Board status register offset */
#define PBC_BSTAT 0x000002
/*!
* PBC Board control register 1 set address.
*/
/* PBC Board control register 1 set address */
#define PBC_BCTRL1_SET 0x000004
/*!
* PBC Board control register 1 clear address.
*/
/* PBC Board control register 1 clear address */
#define PBC_BCTRL1_CLEAR 0x000006
/*!
* PBC Board control register 2 set address.
*/
/* PBC Board control register 2 set address */
#define PBC_BCTRL2_SET 0x000008
/*!
* PBC Board control register 2 clear address.
*/
/* PBC Board control register 2 clear address */
#define PBC_BCTRL2_CLEAR 0x00000A
/*!
* PBC Board control register 3 set address.
*/
/* PBC Board control register 3 set address */
#define PBC_BCTRL3_SET 0x00000C
/*!
* PBC Board control register 3 clear address.
*/
/* PBC Board control register 3 clear address */
#define PBC_BCTRL3_CLEAR 0x00000E
/*!
* PBC Board control register 4 set address.
*/
/* PBC Board control register 4 set address */
#define PBC_BCTRL4_SET 0x000010
/*!
* PBC Board control register 4 clear address.
*/
/* PBC Board control register 4 clear address */
#define PBC_BCTRL4_CLEAR 0x000012
/*!
* PBC Board status register 1.
*/
/* PBC Board status register 1 */
#define PBC_BSTAT1 0x000014
/*!
* PBC Board interrupt status register.
*/
/* PBC Board interrupt status register */
#define PBC_INTSTATUS 0x000016
/*!
* PBC Board interrupt current status register.
*/
/* PBC Board interrupt current status register */
#define PBC_INTCURR_STATUS 0x000018
/*!
* PBC Interrupt mask register set address.
*/
/* PBC Interrupt mask register set address */
#define PBC_INTMASK_SET 0x00001A
/*!
* PBC Interrupt mask register clear address.
*/
/* PBC Interrupt mask register clear address */
#define PBC_INTMASK_CLEAR 0x00001C
/*!
* External UART A.
*/
/* External UART A */
#define PBC_SC16C652_UARTA 0x010000
/*!
* External UART B.
*/
/* External UART B */
#define PBC_SC16C652_UARTB 0x010010
/*!
* Ethernet Controller IO base address.
*/
/* Ethernet Controller IO base address */
#define PBC_CS8900A_IOBASE 0x020000
/*!
* Ethernet Controller Memory base address.
*/
/* Ethernet Controller Memory base address */
#define PBC_CS8900A_MEMBASE 0x021000
/*!
* Ethernet Controller DMA base address.
*/
/* Ethernet Controller DMA base address */
#define PBC_CS8900A_DMABASE 0x022000
/*!
* External chip select 0.
*/
/* External chip select 0 */
#define PBC_XCS0 0x040000
/*!
* LCD Display enable.
*/
/* LCD Display enable */
#define PBC_LCD_EN_B 0x060000
/*!
* Code test debug enable.
*/
/* Code test debug enable */
#define PBC_CODE_B 0x070000
/*!
* PSRAM memory select.
*/
/* PSRAM memory select */
#define PBC_PSRAM_B 0x5000000
#define PBC_INTSTATUS_REG (PBC_INTSTATUS + PBC_BASE_ADDRESS)
@ -139,4 +109,4 @@
#define MXC_MAX_EXP_IO_LINES 16
#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */
#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */

7
include/asm-arm/arch-mxc/dma.h
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@ -11,11 +11,4 @@
#ifndef __ASM_ARCH_MXC_DMA_H__
#define __ASM_ARCH_MXC_DMA_H__
/*!
* @file dma.h
* @brief This file contains Unified DMA API for all MXC platforms.
* The API is platform independent.
*
* @ingroup SDMA
*/
#endif

8
include/asm-arm/arch-mxc/hardware.h
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@ -8,12 +8,6 @@
* published by the Free Software Foundation.
*/
/*!
* @file hardware.h
* @brief This file contains the hardware definitions of the board.
*
* @ingroup System
*/
#ifndef __ASM_ARCH_MXC_HARDWARE_H__
#define __ASM_ARCH_MXC_HARDWARE_H__
@ -49,4 +43,4 @@
MXC_MAX_EXP_IO_LINES + \
MXC_MAX_VIRTUAL_INTS)
#endif /* __ASM_ARCH_MXC_HARDWARE_H__ */
#endif /* __ASM_ARCH_MXC_HARDWARE_H__ */

15
include/asm-arm/arch-mxc/io.h
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@ -8,24 +8,13 @@
* published by the Free Software Foundation.
*/
/*!
* @file io.h
* @brief This file contains some memory mapping macros.
* @note There is no real ISA or PCI buses. But have to define these macros
* for some drivers to compile.
*
* @ingroup System
*/
#ifndef __ASM_ARCH_MXC_IO_H__
#define __ASM_ARCH_MXC_IO_H__
/*! Allow IO space to be anywhere in the memory */
/* Allow IO space to be anywhere in the memory */
#define IO_SPACE_LIMIT 0xffffffff
/*!
* io address mapping macro
*/
/* io address mapping macro */
#define __io(a) ((void __iomem *)(a))
#define __mem_pci(a) (a)

17
include/asm-arm/arch-mxc/irqs.h
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@ -13,26 +13,15 @@
#include <asm/hardware.h>
/*!
* @file irqs.h
* @brief This file defines the number of normal interrupts and fast interrupts
*
* @ingroup Interrupt
*/
#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE)
#define MXC_IRQ_TO_GPIO(irq) ((irq) - MXC_GPIO_INT_BASE)
#define MXC_GPIO_TO_IRQ(x) (MXC_GPIO_INT_BASE + x)
/*!
* Number of normal interrupts
*/
/* Number of normal interrupts */
#define NR_IRQS MXC_MAX_INTS
/*!
* Number of fast interrupts
*/
/* Number of fast interrupts */
#define NR_FIQS MXC_MAX_INTS
#endif /* __ASM_ARCH_MXC_IRQS_H__ */
#endif /* __ASM_ARCH_MXC_IRQS_H__ */

13
include/asm-arm/arch-mxc/memory.h
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@ -13,24 +13,17 @@
#include <asm/hardware.h>
/*!
* @file memory.h
* @brief This file contains macros needed by the Linux kernel and drivers.
*
* @ingroup Memory
*/
/*!
/*
* Virtual view <-> DMA view memory address translations
* This macro is used to translate the virtual address to an address
* suitable to be passed to set_dma_addr()
*/
#define __virt_to_bus(a) __virt_to_phys(a)
/*!
/*
* Used to convert an address for DMA operations to an address that the
* kernel can use.
*/
#define __bus_to_virt(a) __phys_to_virt(a)
#endif /* __ASM_ARCH_MXC_MEMORY_H__ */
#endif /* __ASM_ARCH_MXC_MEMORY_H__ */

6
include/asm-arm/arch-mxc/mxc.h
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@ -31,9 +31,7 @@
#define MXC_GPT_GPTICR2 IO_ADDRESS(GPT1_BASE_ADDR + 0x20)
#define MXC_GPT_GPTCNT IO_ADDRESS(GPT1_BASE_ADDR + 0x24)
/*!
* GPT Control register bit definitions
*/
/* GPT Control register bit definitions */
#define GPTCR_FO3 (1 << 31)
#define GPTCR_FO2 (1 << 30)
#define GPTCR_FO1 (1 << 29)
@ -146,4 +144,4 @@
#define IIM_PROD_REV_SH 3
#define IIM_PROD_REV_LEN 5
#endif /* __ASM_ARCH_MXC_H__ */
#endif /* __ASM_ARCH_MXC_H__ */

18
include/asm-arm/arch-mxc/system.h
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@ -21,30 +21,14 @@
#ifndef __ASM_ARCH_MXC_SYSTEM_H__
#define __ASM_ARCH_MXC_SYSTEM_H__
/*!
* @file system.h
* @brief This file contains idle and reset functions.
*
* @ingroup System
*/
/*!
* This function puts the CPU into idle mode. It is called by default_idle()
* in process.c file.
*/
static inline void arch_idle(void)
{
cpu_do_idle();
}
/*
* This function resets the system. It is called by machine_restart().
*
* @param mode indicates different kinds of resets
*/
static inline void arch_reset(char mode)
{
cpu_reset(0);
}
#endif /* __ASM_ARCH_MXC_SYSTEM_H__ */
#endif /* __ASM_ARCH_MXC_SYSTEM_H__ */

14
include/asm-arm/arch-mxc/vmalloc.h
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@ -20,17 +20,7 @@
#ifndef __ASM_ARCH_MXC_VMALLOC_H__
#define __ASM_ARCH_MXC_VMALLOC_H__
/*!
* @file vmalloc.h
*
* @brief This file contains platform specific macros for vmalloc.
*
* @ingroup System
*/
/*!
* vmalloc ending address
*/
/* vmalloc ending address */
#define VMALLOC_END 0xF4000000
#endif /* __ASM_ARCH_MXC_VMALLOC_H__ */
#endif /* __ASM_ARCH_MXC_VMALLOC_H__ */