[PATCH] ppc64: add 970MP PVR
Add PVR value and tests for 970MP. Also switch to a simpler (but slightly longer) check at init time for simplicity. Signed-off-by: Olof Johansson <olof@austin.ibm.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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@ -31,10 +31,13 @@ _GLOBAL(__970_cpu_preinit)
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*/
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*/
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mfspr r0,SPRN_PVR
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mfspr r0,SPRN_PVR
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srwi r0,r0,16
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srwi r0,r0,16
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cmpwi cr0,r0,0x39
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cmpwi r0,0x39
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cmpwi cr1,r0,0x3c
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beq 1f
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cror 4*cr0+eq,4*cr0+eq,4*cr1+eq
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cmpwi r0,0x3c
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beq 1f
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cmpwi r0,0x44
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bnelr
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bnelr
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1:
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/* Make sure HID4:rm_ci is off before MMU is turned off, that large
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/* Make sure HID4:rm_ci is off before MMU is turned off, that large
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* pages are enabled with HID4:61 and clear HID5:DCBZ_size and
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* pages are enabled with HID4:61 and clear HID5:DCBZ_size and
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@ -133,12 +136,14 @@ _GLOBAL(__save_cpu_setup)
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/* We only deal with 970 for now */
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/* We only deal with 970 for now */
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mfspr r0,SPRN_PVR
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mfspr r0,SPRN_PVR
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srwi r0,r0,16
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srwi r0,r0,16
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cmpwi cr0,r0,0x39
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cmpwi r0,0x39
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cmpwi cr1,r0,0x3c
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beq 1f
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cror 4*cr0+eq,4*cr0+eq,4*cr1+eq
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cmpwi r0,0x3c
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bne 1f
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beq 1f
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cmpwi r0,0x44
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bne 2f
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/* Save HID0,1,4 and 5 */
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1: /* Save HID0,1,4 and 5 */
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mfspr r3,SPRN_HID0
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mfspr r3,SPRN_HID0
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std r3,CS_HID0(r5)
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std r3,CS_HID0(r5)
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mfspr r3,SPRN_HID1
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mfspr r3,SPRN_HID1
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@ -148,7 +153,7 @@ _GLOBAL(__save_cpu_setup)
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mfspr r3,SPRN_HID5
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mfspr r3,SPRN_HID5
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std r3,CS_HID5(r5)
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std r3,CS_HID5(r5)
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1:
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2:
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mtcr r7
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mtcr r7
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blr
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blr
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@ -165,12 +170,14 @@ _GLOBAL(__restore_cpu_setup)
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/* We only deal with 970 for now */
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/* We only deal with 970 for now */
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mfspr r0,SPRN_PVR
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mfspr r0,SPRN_PVR
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srwi r0,r0,16
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srwi r0,r0,16
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cmpwi cr0,r0,0x39
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cmpwi r0,0x39
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cmpwi cr1,r0,0x3c
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beq 1f
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cror 4*cr0+eq,4*cr0+eq,4*cr1+eq
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cmpwi r0,0x3c
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bne 1f
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beq 1f
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cmpwi r0,0x44
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bnelr
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/* Before accessing memory, we make sure rm_ci is clear */
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1: /* Before accessing memory, we make sure rm_ci is clear */
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li r0,0
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li r0,0
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mfspr r3,SPRN_HID4
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mfspr r3,SPRN_HID4
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rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */
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rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */
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@ -223,6 +230,5 @@ _GLOBAL(__restore_cpu_setup)
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mtspr SPRN_HID5,r3
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mtspr SPRN_HID5,r3
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sync
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sync
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isync
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isync
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1:
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blr
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blr
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@ -183,6 +183,21 @@ struct cpu_spec cpu_specs[] = {
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.cpu_setup = __setup_cpu_ppc970,
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.cpu_setup = __setup_cpu_ppc970,
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.firmware_features = COMMON_PPC64_FW,
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.firmware_features = COMMON_PPC64_FW,
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},
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},
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{ /* PPC970MP */
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.pvr_mask = 0xffff0000,
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.pvr_value = 0x00440000,
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.cpu_name = "PPC970MP",
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.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
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CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
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CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
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CPU_FTR_CAN_NAP | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
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.cpu_user_features = COMMON_USER_PPC64 |
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PPC_FEATURE_HAS_ALTIVEC_COMP,
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.icache_bsize = 128,
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.dcache_bsize = 128,
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.cpu_setup = __setup_cpu_ppc970,
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.firmware_features = COMMON_PPC64_FW,
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},
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{ /* Power5 */
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{ /* Power5 */
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.pvr_mask = 0xffff0000,
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.pvr_mask = 0xffff0000,
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.pvr_value = 0x003a0000,
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.pvr_value = 0x003a0000,
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