[ARM] pxa: move GPIOx_BASE and GPIO register offsets to gpio.c
Signed-off-by: Eric Miao <eric.miao@marvell.com>
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2 changed files with 12 additions and 28 deletions
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@ -25,6 +25,18 @@
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#include "generic.h"
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#define GPIO0_BASE ((void __iomem *)io_p2v(0x40E00000))
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#define GPIO1_BASE ((void __iomem *)io_p2v(0x40E00004))
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#define GPIO2_BASE ((void __iomem *)io_p2v(0x40E00008))
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#define GPIO3_BASE ((void __iomem *)io_p2v(0x40E00100))
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#define GPLR_OFFSET 0x00
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#define GPDR_OFFSET 0x0C
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#define GPSR_OFFSET 0x18
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#define GPCR_OFFSET 0x24
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#define GRER_OFFSET 0x30
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#define GFER_OFFSET 0x3C
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#define GEDR_OFFSET 0x48
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struct pxa_gpio_chip {
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struct gpio_chip chip;
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@ -203,19 +203,6 @@
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* General Purpose I/O
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*/
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#define GPIO0_BASE ((void __iomem *)io_p2v(0x40E00000))
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#define GPIO1_BASE ((void __iomem *)io_p2v(0x40E00004))
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#define GPIO2_BASE ((void __iomem *)io_p2v(0x40E00008))
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#define GPIO3_BASE ((void __iomem *)io_p2v(0x40E00100))
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#define GPLR_OFFSET 0x00
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#define GPDR_OFFSET 0x0C
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#define GPSR_OFFSET 0x18
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#define GPCR_OFFSET 0x24
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#define GRER_OFFSET 0x30
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#define GFER_OFFSET 0x3C
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#define GEDR_OFFSET 0x48
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#define GPLR0 __REG(0x40E00000) /* GPIO Pin-Level Register GPIO<31:0> */
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#define GPLR1 __REG(0x40E00004) /* GPIO Pin-Level Register GPIO<63:32> */
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#define GPLR2 __REG(0x40E00008) /* GPIO Pin-Level Register GPIO<80:64> */
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@ -265,10 +252,6 @@
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#define GPIO_bit(x) (1 << ((x) & 0x1f))
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#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
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/* Interrupt Controller */
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#define _GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3)
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#define _GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3)
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#define _GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3)
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@ -287,18 +270,7 @@
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#define GEDR(x) (*((((x) & 0x7f) < 96) ? &_GEDR(x) : &GEDR3))
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#define GAFR(x) (*((((x) & 0x7f) < 96) ? &_GAFR(x) : \
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((((x) & 0x7f) < 112) ? &GAFR3_L : &GAFR3_U)))
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#else
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#define GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3)
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#define GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3)
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#define GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3)
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#define GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3)
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#define GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3)
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#define GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3)
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#define GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3)
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#define GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2)
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#endif
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/*
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* Power Manager - see pxa2xx-regs.h
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