V4L/DVB (9510): cx18: Fix write retries for registers that always change - part 2.
cx18: Fix write retries for registers that always change - part 2. Some registers, especially interrupt related ones, will never read back the value just written. Modified interrupt register readback checks to make sure the intended effect was achieved. Signed-off-by: Andy Walls <awalls@radix.net> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
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58ae1c2318
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f056d29eeb
4 changed files with 45 additions and 12 deletions
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@ -88,6 +88,19 @@ void cx18_writel_retry(struct cx18 *cx, u32 val, void __iomem *addr)
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cx18_log_write_retries(cx, i, addr);
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}
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void _cx18_writel_expect(struct cx18 *cx, u32 val, void __iomem *addr,
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u32 eval, u32 mask)
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{
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int i;
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eval &= mask;
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for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
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cx18_writel_noretry(cx, val, addr);
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if (eval == (cx18_readl_noretry(cx, addr) & mask))
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break;
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}
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cx18_log_write_retries(cx, i, addr);
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}
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void cx18_writew_retry(struct cx18 *cx, u16 val, void __iomem *addr)
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{
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int i;
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@ -218,7 +231,7 @@ void cx18_memset_io(struct cx18 *cx, void __iomem *addr, int val, size_t count)
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void cx18_sw1_irq_enable(struct cx18 *cx, u32 val)
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{
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u32 r;
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cx18_write_reg_noretry(cx, val, SW1_INT_STATUS);
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cx18_write_reg_expect(cx, val, SW1_INT_STATUS, ~val, val);
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r = cx18_read_reg(cx, SW1_INT_ENABLE_PCI);
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cx18_write_reg(cx, r | val, SW1_INT_ENABLE_PCI);
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}
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@ -233,7 +246,7 @@ void cx18_sw1_irq_disable(struct cx18 *cx, u32 val)
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void cx18_sw2_irq_enable(struct cx18 *cx, u32 val)
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{
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u32 r;
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cx18_write_reg_noretry(cx, val, SW2_INT_STATUS);
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cx18_write_reg_expect(cx, val, SW2_INT_STATUS, ~val, val);
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r = cx18_read_reg(cx, SW2_INT_ENABLE_PCI);
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cx18_write_reg(cx, r | val, SW2_INT_ENABLE_PCI);
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}
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@ -133,6 +133,8 @@ static inline void cx18_writel(struct cx18 *cx, u32 val, void __iomem *addr)
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cx18_writel_noretry(cx, val, addr);
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}
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void _cx18_writel_expect(struct cx18 *cx, u32 val, void __iomem *addr,
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u32 eval, u32 mask);
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static inline
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void cx18_writew_noretry(struct cx18 *cx, u16 val, void __iomem *addr)
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@ -271,6 +273,21 @@ static inline void cx18_write_reg(struct cx18 *cx, u32 val, u32 reg)
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cx18_write_reg_noretry(cx, val, reg);
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}
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static inline void _cx18_write_reg_expect(struct cx18 *cx, u32 val, u32 reg,
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u32 eval, u32 mask)
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{
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_cx18_writel_expect(cx, val, cx->reg_mem + reg, eval, mask);
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}
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static inline void cx18_write_reg_expect(struct cx18 *cx, u32 val, u32 reg,
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u32 eval, u32 mask)
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{
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if (cx18_retry_mmio)
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_cx18_write_reg_expect(cx, val, reg, eval, mask);
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else
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cx18_write_reg_noretry(cx, val, reg);
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}
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static inline u32 cx18_read_reg_noretry(struct cx18 *cx, u32 reg)
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{
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@ -142,16 +142,19 @@ irqreturn_t cx18_irq_handler(int irq, void *dev_id)
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spin_lock(&cx->dma_reg_lock);
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hw2_mask = cx18_read_reg(cx, HW2_INT_MASK5_PCI);
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hw2 = cx18_read_reg(cx, HW2_INT_CLR_STATUS) & hw2_mask;
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sw2_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI) | IRQ_EPU_TO_HPU_ACK;
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sw2 = cx18_read_reg(cx, SW2_INT_STATUS) & sw2_mask;
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sw1_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI) | IRQ_EPU_TO_HPU;
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sw1 = cx18_read_reg(cx, SW1_INT_STATUS) & sw1_mask;
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sw2_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI) | IRQ_EPU_TO_HPU_ACK;
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sw2 = cx18_read_reg(cx, SW2_INT_STATUS) & sw2_mask;
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hw2_mask = cx18_read_reg(cx, HW2_INT_MASK5_PCI);
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hw2 = cx18_read_reg(cx, HW2_INT_CLR_STATUS) & hw2_mask;
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cx18_write_reg_noretry(cx, sw2&sw2_mask, SW2_INT_STATUS);
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cx18_write_reg_noretry(cx, sw1&sw1_mask, SW1_INT_STATUS);
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cx18_write_reg_noretry(cx, hw2&hw2_mask, HW2_INT_CLR_STATUS);
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if (sw1)
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cx18_write_reg_expect(cx, sw1, SW1_INT_STATUS, ~sw1, sw1);
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if (sw2)
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cx18_write_reg_expect(cx, sw2, SW2_INT_STATUS, ~sw2, sw2);
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if (hw2)
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cx18_write_reg_expect(cx, hw2, HW2_INT_CLR_STATUS, ~hw2, hw2);
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if (sw1 || sw2 || hw2)
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CX18_DEBUG_HI_IRQ("SW1: %x SW2: %x HW2: %x\n", sw1, sw2, hw2);
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@ -178,5 +181,5 @@ irqreturn_t cx18_irq_handler(int irq, void *dev_id)
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hpu_cmd(cx, sw1);
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spin_unlock(&cx->dma_reg_lock);
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return (hw2 | sw1 | sw2) ? IRQ_HANDLED : IRQ_NONE;
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return (sw1 || sw2 || hw2) ? IRQ_HANDLED : IRQ_NONE;
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}
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@ -176,7 +176,7 @@ long cx18_mb_ack(struct cx18 *cx, const struct cx18_mailbox *mb)
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cx18_setup_page(cx, SCB_OFFSET);
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cx18_write_sync(cx, mb->request, &ack_mb->ack);
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cx18_write_reg_noretry(cx, ack_irq, SW2_INT_SET);
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cx18_write_reg_expect(cx, ack_irq, SW2_INT_SET, ack_irq, ack_irq);
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return 0;
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}
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@ -225,7 +225,7 @@ static int cx18_api_call(struct cx18 *cx, u32 cmd, int args, u32 data[])
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}
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if (info->flags & API_FAST)
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timeout /= 2;
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cx18_write_reg_noretry(cx, irq, SW1_INT_SET);
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cx18_write_reg_expect(cx, irq, SW1_INT_SET, irq, irq);
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while (!sig && cx18_readl(cx, &mb->ack) != cx18_readl(cx, &mb->request)
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&& cnt < 660) {
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