[SPARC64]: Use different cache sizing defaults on SUN4V.
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
parent
329c68b218
commit
f03b8a5468
2 changed files with 48 additions and 14 deletions
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@ -200,7 +200,8 @@ void __init device_scan(void)
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#ifndef CONFIG_SMP
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{
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int err, cpu_node;
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int err, cpu_node, def;
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err = cpu_find_by_instance(0, &cpu_node, NULL);
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if (err) {
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prom_printf("No cpu nodes, cannot continue\n");
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@ -209,21 +210,40 @@ void __init device_scan(void)
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cpu_data(0).clock_tick = prom_getintdefault(cpu_node,
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"clock-frequency",
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0);
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def = ((tlb_type == hypervisor) ?
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(8 * 1024) :
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(16 * 1024));
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cpu_data(0).dcache_size = prom_getintdefault(cpu_node,
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"dcache-size",
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16 * 1024);
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def);
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def = 32;
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cpu_data(0).dcache_line_size =
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prom_getintdefault(cpu_node, "dcache-line-size", 32);
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prom_getintdefault(cpu_node, "dcache-line-size",
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def);
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def = 16 * 1024;
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cpu_data(0).icache_size = prom_getintdefault(cpu_node,
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"icache-size",
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16 * 1024);
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def);
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def = 32;
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cpu_data(0).icache_line_size =
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prom_getintdefault(cpu_node, "icache-line-size", 32);
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prom_getintdefault(cpu_node, "icache-line-size",
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def);
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def = ((tlb_type == hypervisor) ?
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(3 * 1024 * 1024) :
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(4 * 1024 * 1024));
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cpu_data(0).ecache_size = prom_getintdefault(cpu_node,
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"ecache-size",
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4 * 1024 * 1024);
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def);
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def = 64;
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cpu_data(0).ecache_line_size =
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prom_getintdefault(cpu_node, "ecache-line-size", 64);
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prom_getintdefault(cpu_node, "ecache-line-size",
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def);
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printk("CPU[0]: Caches "
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"D[sz(%d):line_sz(%d)] "
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"I[sz(%d):line_sz(%d)] "
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@ -78,7 +78,7 @@ void smp_bogo(struct seq_file *m)
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void __init smp_store_cpu_info(int id)
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{
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int cpu_node;
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int cpu_node, def;
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/* multiplier and counter set by
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smp_setup_percpu_timer() */
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@ -90,18 +90,32 @@ void __init smp_store_cpu_info(int id)
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cpu_data(id).idle_volume = 1;
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def = ((tlb_type == hypervisor) ? (8 * 1024) : (16 * 1024));
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cpu_data(id).dcache_size = prom_getintdefault(cpu_node, "dcache-size",
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16 * 1024);
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def);
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def = 32;
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cpu_data(id).dcache_line_size =
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prom_getintdefault(cpu_node, "dcache-line-size", 32);
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prom_getintdefault(cpu_node, "dcache-line-size", def);
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def = 16 * 1024;
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cpu_data(id).icache_size = prom_getintdefault(cpu_node, "icache-size",
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16 * 1024);
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def);
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def = 32;
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cpu_data(id).icache_line_size =
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prom_getintdefault(cpu_node, "icache-line-size", 32);
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prom_getintdefault(cpu_node, "icache-line-size", def);
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def = ((tlb_type == hypervisor) ?
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(3 * 1024 * 1024) :
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(4 * 1024 * 1024));
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cpu_data(id).ecache_size = prom_getintdefault(cpu_node, "ecache-size",
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4 * 1024 * 1024);
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def);
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def = 64;
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cpu_data(id).ecache_line_size =
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prom_getintdefault(cpu_node, "ecache-line-size", 64);
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prom_getintdefault(cpu_node, "ecache-line-size", def);
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printk("CPU[%d]: Caches "
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"D[sz(%d):line_sz(%d)] "
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"I[sz(%d):line_sz(%d)] "
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