Staging: solo6x10: Support for tw2865 in cascade/full modes
Finally got ahold of a card with a tw2865 video/audio multiplexer and the spec sheet to go along with it. Signed-off-by: Ben Collins <bcollins@bluecherry.net> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Ben Collins
Greg Kroah-Hartman
parent
6227157f0c
commit
ee6351f56a
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@ -69,6 +69,76 @@ static u8 tbl_tw2864_template[] = {
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0x64, 0x11, 0x40, 0xaf, 0xff, 0x00, 0x00, 0x00,
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};
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static u8 tbl_tw2865_ntsc_template[] = {
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0x00, 0xf0, 0x70, 0x30, 0x80, 0x80, 0x00, 0x02, // 0x00
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0x12, 0xff, 0x09, 0xd0, 0x00, 0x00, 0x00, 0x7f,
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0x00, 0xf0, 0x70, 0x30, 0x80, 0x80, 0x00, 0x02, // 0x10
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0x12, 0xff, 0x09, 0xd0, 0x00, 0x00, 0x00, 0x7f,
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0x00, 0xf0, 0x70, 0x30, 0x80, 0x80, 0x00, 0x02, // 0x20
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0x12, 0xff, 0x09, 0xd0, 0x00, 0x00, 0x00, 0x7f,
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0x00, 0xf0, 0x70, 0x48, 0x80, 0x80, 0x00, 0x02, // 0x30
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0x12, 0xff, 0x09, 0xd0, 0x00, 0x00, 0x00, 0x7f,
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0x00, 0x00, 0x90, 0x68, 0x00, 0x38, 0x80, 0x80, // 0x40
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0x80, 0x80, 0x77, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 0x50
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x45, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 0x60
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x21, 0x43,
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0x08, 0x00, 0x00, 0x01, 0xf1, 0x03, 0xEF, 0x03, // 0x70
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0xE9, 0x03, 0xD9, 0x15, 0x15, 0xE4, 0xA3, 0x80,
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0x00, 0x02, 0x00, 0xCC, 0x00, 0x80, 0x44, 0x50, // 0x80
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0x22, 0x01, 0xD8, 0xBC, 0xB8, 0x44, 0x38, 0x00,
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0x00, 0x78, 0x44, 0x3D, 0x14, 0xA5, 0xE0, 0x05, // 0x90
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0x00, 0x28, 0x44, 0x44, 0xA0, 0x90, 0x52, 0x13,
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0x08, 0x08, 0x08, 0x08, 0x1A, 0x1A, 0x1B, 0x1A, // 0xa0
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0x00, 0x00, 0x00, 0xF0, 0xF0, 0xF0, 0xF0, 0x44,
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0x44, 0x4A, 0x00, 0xFF, 0xEF, 0xEF, 0xEF, 0xEF, // 0xb0
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0xFF, 0xE7, 0xE9, 0xE9, 0xEB, 0xFF, 0xD6, 0xD8,
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0xD8, 0xD7, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 0xc0
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0x00, 0x00, 0x55, 0x00, 0xE4, 0x39, 0x00, 0x80,
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0x77, 0x77, 0x03, 0x20, 0x57, 0x9b, 0xdf, 0x31, // 0xd0
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0x64, 0xa8, 0xec, 0xd1, 0x0f, 0x11, 0x11, 0x81,
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0x10, 0xC0, 0xAA, 0xAA, 0x00, 0x11, 0x00, 0x00, // 0xe0
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0x11, 0x00, 0x00, 0x11, 0x00, 0x00, 0x11, 0x00,
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0x83, 0xB5, 0x09, 0x78, 0x85, 0x00, 0x01, 0x20, // 0xf0
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0x64, 0x51, 0x40, 0xaf, 0xFF, 0xF0, 0x00, 0xC0,
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};
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static u8 tbl_tw2865_pal_template[] = {
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0x00, 0xf0, 0x70, 0x30, 0x80, 0x80, 0x00, 0x12, // 0x00
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0x11, 0xff, 0x01, 0xc3, 0x00, 0x00, 0x01, 0x7f,
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0x00, 0xf0, 0x70, 0x30, 0x80, 0x80, 0x00, 0x12, // 0x10
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0x11, 0xff, 0x01, 0xc3, 0x00, 0x00, 0x01, 0x7f,
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0x00, 0xf0, 0x70, 0x30, 0x80, 0x80, 0x00, 0x12, // 0x20
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0x11, 0xff, 0x01, 0xc3, 0x00, 0x00, 0x01, 0x7f,
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0x00, 0xf0, 0x70, 0x30, 0x80, 0x80, 0x00, 0x12, // 0x30
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0x11, 0xff, 0x01, 0xc3, 0x00, 0x00, 0x01, 0x7f,
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0x00, 0x94, 0x90, 0x48, 0x00, 0x38, 0x7F, 0x80, // 0x40
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0x80, 0x80, 0x77, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 0x50
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x45, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 0x60
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x21, 0x43,
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0x08, 0x00, 0x00, 0x01, 0xf1, 0x03, 0xEF, 0x03, // 0x70
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0xEA, 0x03, 0xD9, 0x15, 0x15, 0xE4, 0xA3, 0x80,
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0x00, 0x02, 0x00, 0xCC, 0x00, 0x80, 0x44, 0x50, // 0x80
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0x22, 0x01, 0xD8, 0xBC, 0xB8, 0x44, 0x38, 0x00,
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0x00, 0x78, 0x44, 0x3D, 0x14, 0xA5, 0xE0, 0x05, // 0x90
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0x00, 0x28, 0x44, 0x44, 0xA0, 0x90, 0x52, 0x13,
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0x08, 0x08, 0x08, 0x08, 0x1A, 0x1A, 0x1A, 0x1A, // 0xa0
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0x00, 0x00, 0x00, 0xF0, 0xF0, 0xF0, 0xF0, 0x44,
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0x44, 0x4A, 0x00, 0xFF, 0xEF, 0xEF, 0xEF, 0xEF, // 0xb0
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0xFF, 0xE7, 0xE9, 0xE9, 0xE9, 0xFF, 0xD7, 0xD8,
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0xD9, 0xD8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 0xc0
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0x00, 0x00, 0x55, 0x00, 0xE4, 0x39, 0x00, 0x80,
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0x77, 0x77, 0x03, 0x20, 0x57, 0x9b, 0xdf, 0x31, // 0xd0
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0x64, 0xa8, 0xec, 0xd1, 0x0f, 0x11, 0x11, 0x81,
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0x10, 0xC0, 0xAA, 0xAA, 0x00, 0x11, 0x00, 0x00, // 0xe0
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0x11, 0x00, 0x00, 0x11, 0x00, 0x00, 0x11, 0x00,
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0x83, 0xB5, 0x09, 0x00, 0xA0, 0x00, 0x01, 0x20, // 0xf0
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0x64, 0x51, 0x40, 0xaf, 0xFF, 0xF0, 0x00, 0xC0,
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};
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#define is_tw286x(__solo, __id) (!(__solo->tw2815 & (1 << __id)))
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static u8 tw_readbyte(struct solo6010_dev *solo_dev, int chip_id, u8 tw6x_off,
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@ -111,38 +181,109 @@ static void tw_write_and_verify(struct solo6010_dev *solo_dev, u8 addr, u8 off,
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msleep_interruptible(1);
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}
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printk("solo6010/tw28: Error writing register: %02x->%02x [%02x]\n",
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addr, off, val);
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// printk("solo6010/tw28: Error writing register: %02x->%02x [%02x]\n",
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// addr, off, val);
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}
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static int tw2865_setup(struct solo6010_dev *solo_dev, u8 dev_addr)
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{
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u8 tbl_tw2865_common[256];
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int i;
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if (solo_dev->video_type == SOLO_VO_FMT_TYPE_PAL)
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memcpy(tbl_tw2865_common, tbl_tw2865_pal_template,
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sizeof(tbl_tw2865_common));
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else
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memcpy(tbl_tw2865_common, tbl_tw2865_ntsc_template,
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sizeof(tbl_tw2865_common));
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/* ALINK Mode */
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if (solo_dev->nr_chans == 4) {
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tbl_tw2865_common[0xd2] = 0x01;
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tbl_tw2865_common[0xcf] = 0x00;
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} else if (solo_dev->nr_chans == 8) {
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tbl_tw2865_common[0xd2] = 0x02;
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if (dev_addr == TW_CHIP_OFFSET_ADDR(1))
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tbl_tw2865_common[0xcf] = 0x80;
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} else if (solo_dev->nr_chans == 16) {
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tbl_tw2865_common[0xd2] = 0x03;
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if (dev_addr == TW_CHIP_OFFSET_ADDR(1))
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tbl_tw2865_common[0xcf] = 0x83;
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else if (dev_addr == TW_CHIP_OFFSET_ADDR(2))
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tbl_tw2865_common[0xcf] = 0x83;
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else if (dev_addr == TW_CHIP_OFFSET_ADDR(3))
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tbl_tw2865_common[0xcf] = 0x80;
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}
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for (i = 0; i < 0xff; i++) {
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/* Skip read only registers */
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if (i >= 0xb8 && i <= 0xc1 )
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continue;
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if ((i & ~0x30) == 0x00 ||
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(i & ~0x30) == 0x0c ||
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(i & ~0x30) == 0x0d)
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continue;
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if (i >= 0xc4 && i <= 0xc7)
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continue;
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if (i == 0xfd)
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continue;
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tw_write_and_verify(solo_dev, dev_addr, i,
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tbl_tw2865_common[i]);
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}
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return 0;
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}
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static int tw2864_setup(struct solo6010_dev *solo_dev, u8 dev_addr)
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{
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u8 tbl_tw2864_common[256];
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u8 tbl_tw2864_common[sizeof(tbl_tw2864_template)];
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int i;
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memcpy(tbl_tw2864_common, tbl_tw2864_template,
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sizeof(tbl_tw2864_common));
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/* IRQ Mode */
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if (solo_dev->nr_chans == 4) {
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tbl_tw2864_common[0xd2] = 0x01;
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tbl_tw2864_common[0xcf] = 0x00;
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} else if (solo_dev->nr_chans == 8) {
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tbl_tw2864_common[0xd2] = 0x02;
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if (dev_addr == TW_CHIP_OFFSET_ADDR(0))
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tbl_tw2864_common[0xcf] = 0x43;
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else if (dev_addr == TW_CHIP_OFFSET_ADDR(1))
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tbl_tw2864_common[0xcf] = 0x40;
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} else if (solo_dev->nr_chans == 16) {
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tbl_tw2864_common[0xd2] = 0x03;
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if (dev_addr == TW_CHIP_OFFSET_ADDR(0))
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tbl_tw2864_common[0xcf] = 0x43;
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else if (dev_addr == TW_CHIP_OFFSET_ADDR(1))
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tbl_tw2864_common[0xcf] = 0x43;
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else if (dev_addr == TW_CHIP_OFFSET_ADDR(2))
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tbl_tw2864_common[0xcf] = 0x43;
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else if (dev_addr == TW_CHIP_OFFSET_ADDR(3))
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tbl_tw2864_common[0xcf] = 0x40;
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if (solo_dev->tw2865 == 0) {
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/* IRQ Mode */
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if (solo_dev->nr_chans == 4) {
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tbl_tw2864_common[0xd2] = 0x01;
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tbl_tw2864_common[0xcf] = 0x00;
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} else if (solo_dev->nr_chans == 8) {
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tbl_tw2864_common[0xd2] = 0x02;
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if (dev_addr == TW_CHIP_OFFSET_ADDR(0))
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tbl_tw2864_common[0xcf] = 0x43;
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else if (dev_addr == TW_CHIP_OFFSET_ADDR(1))
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tbl_tw2864_common[0xcf] = 0x40;
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} else if (solo_dev->nr_chans == 16) {
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tbl_tw2864_common[0xd2] = 0x03;
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if (dev_addr == TW_CHIP_OFFSET_ADDR(0))
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tbl_tw2864_common[0xcf] = 0x43;
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else if (dev_addr == TW_CHIP_OFFSET_ADDR(1))
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tbl_tw2864_common[0xcf] = 0x43;
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else if (dev_addr == TW_CHIP_OFFSET_ADDR(2))
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tbl_tw2864_common[0xcf] = 0x43;
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else if (dev_addr == TW_CHIP_OFFSET_ADDR(3))
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tbl_tw2864_common[0xcf] = 0x40;
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}
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} else {
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/* ALINK Mode. Assumes that the first tw28xx is a
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* 2865 and these are in cascade. */
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for (i = 0; i <= 4; i++)
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tbl_tw2864_common[0x08 | i << 4] = 0x12;
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if (solo_dev->nr_chans == 8) {
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tbl_tw2864_common[0xd2] = 0x02;
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if (dev_addr == TW_CHIP_OFFSET_ADDR(1))
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tbl_tw2864_common[0xcf] = 0x80;
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} else if (solo_dev->nr_chans == 16) {
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tbl_tw2864_common[0xd2] = 0x03;
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if (dev_addr == TW_CHIP_OFFSET_ADDR(1))
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tbl_tw2864_common[0xcf] = 0x83;
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else if (dev_addr == TW_CHIP_OFFSET_ADDR(2))
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tbl_tw2864_common[0xcf] = 0x83;
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else if (dev_addr == TW_CHIP_OFFSET_ADDR(3))
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tbl_tw2864_common[0xcf] = 0x80;
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}
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}
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/* NTSC or PAL */
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@ -170,8 +311,8 @@ static int tw2864_setup(struct solo6010_dev *solo_dev, u8 dev_addr)
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if (i == 0x74 || i == 0x77 || i == 0x78 ||
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i == 0x79 || i == 0x7a)
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continue;
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if (i == 0xfd)
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continue;
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if (i == 0xfd)
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continue;
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tw_write_and_verify(solo_dev, dev_addr, i,
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tbl_tw2864_common[i]);
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@ -411,8 +552,8 @@ int solo_tw28_init(struct solo6010_dev *solo_dev)
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switch (value >> 3) {
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case 0x18:
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printk("solo6010: 2865 support not enabled\n");
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return -EINVAL;
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solo_dev->tw2865 |= 1 << i;
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solo_dev->tw28_cnt++;
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break;
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case 0x0c:
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solo_dev->tw2864 |= 1 << i;
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@ -434,7 +575,9 @@ int solo_tw28_init(struct solo6010_dev *solo_dev)
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saa7128_setup(solo_dev);
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for (i = 0; i < solo_dev->tw28_cnt; i++) {
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if ((solo_dev->tw2864 & (1 << i)))
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if ((solo_dev->tw2865 & (1 << i)))
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tw2865_setup(solo_dev, TW_CHIP_OFFSET_ADDR(i));
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else if ((solo_dev->tw2864 & (1 << i)))
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tw2864_setup(solo_dev, TW_CHIP_OFFSET_ADDR(i));
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else
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tw2815_setup(solo_dev, TW_CHIP_OFFSET_ADDR(i));
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@ -443,6 +586,8 @@ int solo_tw28_init(struct solo6010_dev *solo_dev)
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dev_info(&solo_dev->pdev->dev, "Initialized %d tw28xx chip%s:",
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solo_dev->tw28_cnt, solo_dev->tw28_cnt == 1 ? "" : "s");
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if (solo_dev->tw2865)
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printk(" tw2865[%d]", hweight32(solo_dev->tw2865));
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if (solo_dev->tw2864)
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printk(" tw2864[%d]", hweight32(solo_dev->tw2864));
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if (solo_dev->tw2815)
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@ -577,7 +722,7 @@ int tw28_get_ctrl_val(struct solo6010_dev *solo_dev, u32 ctrl, u8 ch,
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case V4L2_CID_SHARPNESS:
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/* Only 286x has sharpness */
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if (is_tw286x(solo_dev, chip_num)) {
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rval = solo_i2c_readbyte(solo_dev, SOLO_I2C_TW,
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rval = solo_i2c_readbyte(solo_dev, SOLO_I2C_TW,
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TW_CHIP_OFFSET_ADDR(chip_num),
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TW286x_SHARPNESS(chip_num));
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*val = rval & 0x0f;
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@ -178,7 +178,7 @@ struct solo6010_dev {
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spinlock_t reg_io_lock;
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/* tw28xx accounting */
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u8 tw2864, tw2815;
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u8 tw2865, tw2864, tw2815;
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u8 tw28_cnt;
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/* i2c related items */
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