drm/nve0/graph: fix fuc, and enable acceleration on all known chipsets
Also adds GK106 to chipsets known by ucode. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
parent
902530693e
commit
eca15296a9
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@ -57,6 +57,11 @@ chipsets:
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.b16 #nve4_gpc_mmio_tail
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.b16 #nve4_tpc_mmio_head
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.b16 #nve4_tpc_mmio_tail
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.b8 0xe6 0 0 0
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.b16 #nve4_gpc_mmio_head
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.b16 #nve4_gpc_mmio_tail
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.b16 #nve4_tpc_mmio_head
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.b16 #nve4_tpc_mmio_tail
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.b8 0 0 0 0
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// GPC mmio lists
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@ -34,13 +34,16 @@ uint32_t nve0_grgpc_data[] = {
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0x00000000,
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/* 0x0064: chipsets */
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0x000000e4,
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0x01040080,
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0x014c0104,
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0x0110008c,
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0x01580110,
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0x000000e7,
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0x01040080,
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0x014c0104,
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0x0110008c,
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0x01580110,
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0x000000e6,
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0x0110008c,
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0x01580110,
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0x00000000,
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/* 0x0080: nve4_gpc_mmio_head */
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/* 0x008c: nve4_gpc_mmio_head */
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0x00000380,
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0x04000400,
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0x0800040c,
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@ -74,8 +77,8 @@ uint32_t nve0_grgpc_data[] = {
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0x14003100,
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0x000031d0,
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0x040031e0,
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/* 0x0104: nve4_gpc_mmio_tail */
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/* 0x0104: nve4_tpc_mmio_head */
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/* 0x0110: nve4_gpc_mmio_tail */
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/* 0x0110: nve4_tpc_mmio_head */
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0x00000048,
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0x00000064,
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0x00000088,
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@ -44,6 +44,9 @@ chipsets:
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.b8 0xe7 0 0 0
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.b16 #nve4_hub_mmio_head
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.b16 #nve4_hub_mmio_tail
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.b8 0xe6 0 0 0
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.b16 #nve4_hub_mmio_head
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.b16 #nve4_hub_mmio_tail
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.b8 0 0 0 0
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nve4_hub_mmio_head:
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@ -680,6 +683,16 @@ ctx_mmio_exec:
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// on load it means: "a save preceeded this load"
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//
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ctx_xfer:
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// according to mwk, some kind of wait for idle
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mov $r15 0xc00
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shl b32 $r15 6
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mov $r14 4
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iowr I[$r15 + 0x200] $r14
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ctx_xfer_idle:
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iord $r14 I[$r15 + 0x000]
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and $r14 0x2000
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bra ne #ctx_xfer_idle
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bra not $p1 #ctx_xfer_pre
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bra $p2 #ctx_xfer_pre_load
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ctx_xfer_pre:
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@ -30,11 +30,13 @@ uint32_t nve0_grhub_data[] = {
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0x00000000,
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/* 0x005c: chipsets */
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0x000000e4,
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0x013c0070,
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0x01440078,
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0x000000e7,
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0x013c0070,
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0x01440078,
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0x000000e6,
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0x01440078,
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0x00000000,
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/* 0x0070: nve4_hub_mmio_head */
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/* 0x0078: nve4_hub_mmio_head */
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0x0417e91c,
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0x04400204,
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0x18404010,
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@ -86,9 +88,7 @@ uint32_t nve0_grhub_data[] = {
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0x00408840,
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0x08408900,
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0x00408980,
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/* 0x013c: nve4_hub_mmio_tail */
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0x00000000,
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0x00000000,
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/* 0x0144: nve4_hub_mmio_tail */
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0x00000000,
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0x00000000,
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0x00000000,
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@ -781,77 +781,78 @@ uint32_t nve0_grhub_code[] = {
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0x0613f002,
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0xf80601fa,
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/* 0x07fb: ctx_xfer */
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0xf400f803,
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0x02f40611,
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/* 0x0801: ctx_xfer_pre */
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0x10f7f00d,
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0x067221f5,
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/* 0x080b: ctx_xfer_pre_load */
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0xf01c11f4,
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0x21f502f7,
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0x21f50631,
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0x21f50640,
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0xf4bd0652,
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0x063121f5,
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0x069221f5,
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/* 0x0824: ctx_xfer_exec */
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0xf1160198,
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0xb6041427,
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0x20d00624,
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0x00e7f100,
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0x41e3f0a5,
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0xf4021fb9,
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0xe0b68d21,
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0x01fcf004,
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0xb6022cf0,
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0xf2fd0124,
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0x8d21f405,
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0x4afc17f1,
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0xf00213f0,
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0x12d00c27,
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0x0721f500,
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0xfc27f102,
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0x0223f047,
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0xf00020d0,
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0x20b6012c,
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0x0012d003,
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0xf001acf0,
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0xb7f006a5,
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0x140c9800,
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0xf0150d98,
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0x21f500e7,
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0xa7f0015c,
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0x0321f508,
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0x0721f501,
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0x2201f402,
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0xf40ca7f0,
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0x17f1c921,
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0x14b60a10,
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0x0527f006,
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/* 0x08ab: ctx_xfer_post_save_wait */
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0xcf0012d0,
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0x22fd0012,
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0xfa1bf405,
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/* 0x08b7: ctx_xfer_post */
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0xf02e02f4,
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0x21f502f7,
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0xf4bd0631,
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0x067221f5,
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0x022621f5,
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0x064021f5,
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0x21f5f4bd,
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0x11f40631,
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0x80019810,
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0xf40511fd,
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0x21f5070b,
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/* 0x08e2: ctx_xfer_no_post_mmio */
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/* 0x08e2: ctx_xfer_done */
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0x00f807b1,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0xf100f803,
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0xb60c00f7,
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0xe7f006f4,
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0x80fed004,
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/* 0x0808: ctx_xfer_idle */
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0xf100fecf,
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0xf42000e4,
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0x11f4f91b,
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0x0d02f406,
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/* 0x0818: ctx_xfer_pre */
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0xf510f7f0,
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0xf4067221,
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/* 0x0822: ctx_xfer_pre_load */
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0xf7f01c11,
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0x3121f502,
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0x4021f506,
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0x5221f506,
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0xf5f4bd06,
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0xf5063121,
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/* 0x083b: ctx_xfer_exec */
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0x98069221,
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0x27f11601,
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0x24b60414,
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0x0020d006,
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0xa500e7f1,
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0xb941e3f0,
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0x21f4021f,
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0x04e0b68d,
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0xf001fcf0,
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0x24b6022c,
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0x05f2fd01,
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0xf18d21f4,
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0xf04afc17,
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0x27f00213,
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0x0012d00c,
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0x020721f5,
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0x47fc27f1,
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0xd00223f0,
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0x2cf00020,
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0x0320b601,
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0xf00012d0,
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0xa5f001ac,
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0x00b7f006,
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0x98140c98,
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0xe7f0150d,
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0x5c21f500,
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0x08a7f001,
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0x010321f5,
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0x020721f5,
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0xf02201f4,
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0x21f40ca7,
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0x1017f1c9,
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0x0614b60a,
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0xd00527f0,
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/* 0x08c2: ctx_xfer_post_save_wait */
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0x12cf0012,
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0x0522fd00,
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0xf4fa1bf4,
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/* 0x08ce: ctx_xfer_post */
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0xf7f02e02,
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0x3121f502,
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0xf5f4bd06,
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0xf5067221,
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0xf5022621,
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0xbd064021,
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0x3121f5f4,
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0x1011f406,
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0xfd800198,
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0x0bf40511,
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0xb121f507,
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/* 0x08f9: ctx_xfer_no_post_mmio */
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/* 0x08f9: ctx_xfer_done */
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0x0000f807,
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0x00000000,
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};
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@ -203,7 +203,7 @@ nve0_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
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struct nvc0_graph_priv *priv;
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int ret, i;
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ret = nouveau_graph_create(parent, engine, oclass, false, &priv);
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ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
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*pobject = nv_object(priv);
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if (ret)
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return ret;
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